42 lines
1.3 KiB
Diff
42 lines
1.3 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Fri, 3 Nov 2023 20:05:05 +0200
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Subject: arm64: dts: rockchip: Make use of HDMI0 PHY PLL on rock-5b
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The initial vop2 support for rk3588 in mainline is not able to handle
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all display modes supported by connected displays, e.g.
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2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz.
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Additionally, it doesn't cope with non-integer refresh rates like 59.94,
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29.97, 23.98, etc.
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Make use of the HDMI0 PHY PLL to support the additional display modes.
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Note this requires commit "drm/rockchip: vop2: Improve display modes
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handling on rk3588", which needs a rework to be upstreamable.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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---
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arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++
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1 file changed, 5 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
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index 111111111111..222222222222 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
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@@ -186,6 +186,11 @@ &gpu {
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status = "okay";
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};
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+&display_subsystem {
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+ clocks = <&hdptxphy_hdmi0>;
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+ clock-names = "hdmi0_phy_pll";
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+};
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+
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&hdmi0 {
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status = "okay";
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};
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--
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Armbian
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