diff --git a/atf.patches/feat-rk3588-support-rk3588.patch b/atf.patches/feat-rk3588-support-rk3588.patch new file mode 100644 index 0000000..aea9674 --- /dev/null +++ b/atf.patches/feat-rk3588-support-rk3588.patch @@ -0,0 +1,6516 @@ +From 0ea6a6560e38121242dfe5298071d3cdedb63a09 Mon Sep 17 00:00:00 2001 +From: XiaoDong Huang +Date: Mon, 26 Jun 2023 16:43:30 +0800 +Subject: [PATCH] feat(rk3588): support rk3588 + +rk3588 is a eight-core soc and Cortex-a55/a76 inside. +This patch supports the following functions: +1. basic platform setup +2. power up/off cpus +3. suspend/resume cpus +4. suspend/resume system +5. reset system +6. power off system + +Signed-off-by: XiaoDong Huang +Change-Id: I598109f15a2efd5b33aedd176cf708c08cb1dcf4 +--- + +diff --git a/docs/plat/rockchip.rst b/docs/plat/rockchip.rst +index 53f63b5..384cd73 100644 +--- a/docs/plat/rockchip.rst ++++ b/docs/plat/rockchip.rst +@@ -11,6 +11,7 @@ + - rk3368: Octa-Core Cortex-A53 + - rk3399: Hexa-Core Cortex-A53/A72 + - rk3566/rk3568: Quad-Core Cortex-A55 ++- rk3588: Octa-Core Cortex-A55/A76 + + + Boot Sequence +diff --git a/plat/rockchip/rk3588/drivers/pmu/plat_pmu_macros.S b/plat/rockchip/rk3588/drivers/pmu/plat_pmu_macros.S +new file mode 100644 +index 0000000..c278899 +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/pmu/plat_pmu_macros.S +@@ -0,0 +1,21 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++#include ++ ++.globl clst_warmboot_data ++ ++.macro func_rockchip_clst_warmboot ++.endm ++ ++.macro rockchip_clst_warmboot_data ++clst_warmboot_data: ++ .rept PLATFORM_CLUSTER_COUNT ++ .word 0 ++ .endr ++.endm +diff --git a/plat/rockchip/rk3588/drivers/pmu/pm_pd_regs.c b/plat/rockchip/rk3588/drivers/pmu/pm_pd_regs.c +new file mode 100644 +index 0000000..78e8500 +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/pmu/pm_pd_regs.c +@@ -0,0 +1,555 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define WMSK_VAL 0xffff0000 ++ ++static struct reg_region qos_reg_rgns[] = { ++ [QOS_ISP0_MWO] = REG_REGION(0x08, 0x18, 4, 0xfdf40500, 0), ++ [QOS_ISP0_MRO] = REG_REGION(0x08, 0x18, 4, 0xfdf40400, 0), ++ [QOS_ISP1_MWO] = REG_REGION(0x08, 0x18, 4, 0xfdf41000, 0), ++ [QOS_ISP1_MRO] = REG_REGION(0x08, 0x18, 4, 0xfdf41100, 0), ++ [QOS_VICAP_M0] = REG_REGION(0x08, 0x18, 4, 0xfdf40600, 0), ++ [QOS_VICAP_M1] = REG_REGION(0x08, 0x18, 4, 0xfdf40800, 0), ++ [QOS_FISHEYE0] = REG_REGION(0x08, 0x18, 4, 0xfdf40000, 0), ++ [QOS_FISHEYE1] = REG_REGION(0x08, 0x18, 4, 0xfdf40200, 0), ++ [QOS_VOP_M0] = REG_REGION(0x08, 0x18, 4, 0xfdf82000, 0), ++ [QOS_VOP_M1] = REG_REGION(0x08, 0x18, 4, 0xfdf82200, 0), ++ [QOS_RKVDEC0] = REG_REGION(0x08, 0x18, 4, 0xfdf62000, 0), ++ [QOS_RKVDEC1] = REG_REGION(0x08, 0x18, 4, 0xfdf63000, 0), ++ [QOS_AV1] = REG_REGION(0x08, 0x18, 4, 0xfdf64000, 0), ++ [QOS_RKVENC0_M0RO] = REG_REGION(0x08, 0x18, 4, 0xfdf60000, 0), ++ [QOS_RKVENC0_M1RO] = REG_REGION(0x08, 0x18, 4, 0xfdf60200, 0), ++ [QOS_RKVENC0_M2WO] = REG_REGION(0x08, 0x18, 4, 0xfdf60400, 0), ++ [QOS_RKVENC1_M0RO] = REG_REGION(0x08, 0x18, 4, 0xfdf61000, 0), ++ [QOS_RKVENC1_M1RO] = REG_REGION(0x08, 0x18, 4, 0xfdf61200, 0), ++ [QOS_RKVENC1_M2WO] = REG_REGION(0x08, 0x18, 4, 0xfdf61400, 0), ++ [QOS_DSU_M0] = REG_REGION(0x08, 0x18, 4, 0xfe008000, 0), ++ [QOS_DSU_M1] = REG_REGION(0x08, 0x18, 4, 0xfe008800, 0), ++ [QOS_DSU_MP] = REG_REGION(0x08, 0x18, 4, 0xfdf34200, 0), ++ [QOS_DEBUG] = REG_REGION(0x08, 0x18, 4, 0xfdf34400, 0), ++ [QOS_GPU_M0] = REG_REGION(0x08, 0x18, 4, 0xfdf35000, 0), ++ [QOS_GPU_M1] = REG_REGION(0x08, 0x18, 4, 0xfdf35200, 0), ++ [QOS_GPU_M2] = REG_REGION(0x08, 0x18, 4, 0xfdf35400, 0), ++ [QOS_GPU_M3] = REG_REGION(0x08, 0x18, 4, 0xfdf35600, 0), ++ [QOS_NPU1] = REG_REGION(0x08, 0x18, 4, 0xfdf70000, 0), ++ [QOS_NPU0_MRO] = REG_REGION(0x08, 0x18, 4, 0xfdf72200, 0), ++ [QOS_NPU2] = REG_REGION(0x08, 0x18, 4, 0xfdf71000, 0), ++ [QOS_NPU0_MWR] = REG_REGION(0x08, 0x18, 4, 0xfdf72000, 0), ++ [QOS_MCU_NPU] = REG_REGION(0x08, 0x18, 4, 0xfdf72400, 0), ++ [QOS_JPEG_DEC] = REG_REGION(0x08, 0x18, 4, 0xfdf66200, 0), ++ [QOS_JPEG_ENC0] = REG_REGION(0x08, 0x18, 4, 0xfdf66400, 0), ++ [QOS_JPEG_ENC1] = REG_REGION(0x08, 0x18, 4, 0xfdf66600, 0), ++ [QOS_JPEG_ENC2] = REG_REGION(0x08, 0x18, 4, 0xfdf66800, 0), ++ [QOS_JPEG_ENC3] = REG_REGION(0x08, 0x18, 4, 0xfdf66a00, 0), ++ [QOS_RGA2_MRO] = REG_REGION(0x08, 0x18, 4, 0xfdf66c00, 0), ++ [QOS_RGA2_MWO] = REG_REGION(0x08, 0x18, 4, 0xfdf66e00, 0), ++ [QOS_RGA3_0] = REG_REGION(0x08, 0x18, 4, 0xfdf67000, 0), ++ [QOS_RGA3_1] = REG_REGION(0x08, 0x18, 4, 0xfdf36000, 0), ++ [QOS_VDPU] = REG_REGION(0x08, 0x18, 4, 0xfdf67200, 0), ++ [QOS_IEP] = REG_REGION(0x08, 0x18, 4, 0xfdf66000, 0), ++ [QOS_HDCP0] = REG_REGION(0x08, 0x18, 4, 0xfdf80000, 0), ++ [QOS_HDCP1] = REG_REGION(0x08, 0x18, 4, 0xfdf81000, 0), ++ [QOS_HDMIRX] = REG_REGION(0x08, 0x18, 4, 0xfdf81200, 0), ++ [QOS_GIC600_M0] = REG_REGION(0x08, 0x18, 4, 0xfdf3a000, 0), ++ [QOS_GIC600_M1] = REG_REGION(0x08, 0x18, 4, 0xfdf3a200, 0), ++ [QOS_MMU600PCIE_TCU] = REG_REGION(0x08, 0x18, 4, 0xfdf3a400, 0), ++ [QOS_MMU600PHP_TBU] = REG_REGION(0x08, 0x18, 4, 0xfdf3a600, 0), ++ [QOS_MMU600PHP_TCU] = REG_REGION(0x08, 0x18, 4, 0xfdf3a800, 0), ++ [QOS_USB3_0] = REG_REGION(0x08, 0x18, 4, 0xfdf3e200, 0), ++ [QOS_USB3_1] = REG_REGION(0x08, 0x18, 4, 0xfdf3e000, 0), ++ [QOS_USBHOST_0] = REG_REGION(0x08, 0x18, 4, 0xfdf3e400, 0), ++ [QOS_USBHOST_1] = REG_REGION(0x08, 0x18, 4, 0xfdf3e600, 0), ++ [QOS_EMMC] = REG_REGION(0x08, 0x18, 4, 0xfdf38200, 0), ++ [QOS_FSPI] = REG_REGION(0x08, 0x18, 4, 0xfdf38000, 0), ++ [QOS_SDIO] = REG_REGION(0x08, 0x18, 4, 0xfdf39000, 0), ++ [QOS_DECOM] = REG_REGION(0x08, 0x18, 4, 0xfdf32000, 0), ++ [QOS_DMAC0] = REG_REGION(0x08, 0x18, 4, 0xfdf32200, 0), ++ [QOS_DMAC1] = REG_REGION(0x08, 0x18, 4, 0xfdf32400, 0), ++ [QOS_DMAC2] = REG_REGION(0x08, 0x18, 4, 0xfdf32600, 0), ++ [QOS_GIC600M] = REG_REGION(0x08, 0x18, 4, 0xfdf32800, 0), ++ [QOS_DMA2DDR] = REG_REGION(0x08, 0x18, 4, 0xfdf52000, 0), ++ [QOS_MCU_DDR] = REG_REGION(0x08, 0x18, 4, 0xfdf52200, 0), ++ [QOS_VAD] = REG_REGION(0x08, 0x18, 4, 0xfdf3b200, 0), ++ [QOS_MCU_PMU] = REG_REGION(0x08, 0x18, 4, 0xfdf3b000, 0), ++ [QOS_CRYPTOS] = REG_REGION(0x08, 0x18, 4, 0xfdf3d200, 0), ++ [QOS_CRYPTONS] = REG_REGION(0x08, 0x18, 4, 0xfdf3d000, 0), ++ [QOS_DCF] = REG_REGION(0x08, 0x18, 4, 0xfdf3d400, 0), ++ [QOS_SDMMC] = REG_REGION(0x08, 0x18, 4, 0xfdf3d800, 0), ++}; ++ ++static struct reg_region pd_crypto_reg_rgns[] = { ++ /* SECURE CRU */ ++ REG_REGION(0x300, 0x30c, 4, SCRU_BASE, WMSK_VAL), ++ REG_REGION(0x800, 0x80c, 4, SCRU_BASE, WMSK_VAL), ++ REG_REGION(0xa00, 0xa0c, 4, SCRU_BASE, WMSK_VAL), ++ REG_REGION(0xd00, 0xd20, 8, SCRU_BASE, 0), ++ REG_REGION(0xd04, 0xd24, 8, SCRU_BASE, WMSK_VAL), ++ ++ /* S TIMER0 6 channel */ ++ REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x00, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x00, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x20, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x20, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x40, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x40, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x60, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x60, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x80, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x80, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0xa0, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0xa0, 0), ++ ++ /* S TIMER1 6 channel */ ++ REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x00, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x00, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x20, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x20, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x40, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x40, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x60, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x60, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x80, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x80, 0), ++ REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0xa0, 0), ++ REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0xa0, 0), ++ ++ /* wdt_s */ ++ REG_REGION(0x04, 0x04, 4, WDT_S_BASE, 0), ++ REG_REGION(0x00, 0x00, 4, WDT_S_BASE, 0), ++}; ++ ++static struct reg_region pd_dsu_reg_rgns[] = { ++ /* dsucru */ ++ REG_REGION(0x040, 0x054, 4, DSUCRU_BASE, WMSK_VAL), ++ REG_REGION(0x300, 0x31c, 4, DSUCRU_BASE, WMSK_VAL), ++ REG_REGION(0x800, 0x80c, 4, DSUCRU_BASE, WMSK_VAL), ++ REG_REGION(0xa00, 0xa0c, 4, DSUCRU_BASE, WMSK_VAL), ++ REG_REGION(0xd00, 0xd20, 8, DSUCRU_BASE, 0), ++ REG_REGION(0xd04, 0xd24, 8, DSUCRU_BASE, WMSK_VAL), ++ REG_REGION(0xf00, 0xf00, 4, DSUCRU_BASE, WMSK_VAL), ++ REG_REGION(0xf10, 0xf1c, 4, DSUCRU_BASE, 0), ++ ++ /* bcore0cru */ ++ REG_REGION(0x000, 0x014, 4, BIGCORE0CRU_BASE, WMSK_VAL), ++ REG_REGION(0x300, 0x304, 4, BIGCORE0CRU_BASE, WMSK_VAL), ++ REG_REGION(0x800, 0x804, 4, BIGCORE0CRU_BASE, WMSK_VAL), ++ REG_REGION(0xa00, 0xa04, 4, BIGCORE0CRU_BASE, WMSK_VAL), ++ REG_REGION(0xcc0, 0xcc4, 4, BIGCORE0CRU_BASE, 0), ++ REG_REGION(0xd00, 0xd00, 4, BIGCORE0CRU_BASE, 0), ++ REG_REGION(0xd04, 0xd04, 4, BIGCORE0CRU_BASE, WMSK_VAL), ++ ++ /* bcore1cru */ ++ REG_REGION(0x020, 0x034, 4, BIGCORE1CRU_BASE, WMSK_VAL), ++ REG_REGION(0x300, 0x304, 4, BIGCORE1CRU_BASE, WMSK_VAL), ++ REG_REGION(0x800, 0x804, 4, BIGCORE1CRU_BASE, WMSK_VAL), ++ REG_REGION(0xa00, 0xa04, 4, BIGCORE1CRU_BASE, WMSK_VAL), ++ REG_REGION(0xcc0, 0xcc4, 4, BIGCORE1CRU_BASE, 0), ++ REG_REGION(0xd00, 0xd00, 4, BIGCORE1CRU_BASE, 0), ++ REG_REGION(0xd04, 0xd04, 4, BIGCORE1CRU_BASE, WMSK_VAL), ++ ++ /* dsugrf */ ++ REG_REGION(0x00, 0x18, 4, DSUGRF_BASE, WMSK_VAL), ++ REG_REGION(0x20, 0x20, 4, DSUGRF_BASE, WMSK_VAL), ++ REG_REGION(0x28, 0x30, 4, DSUGRF_BASE, WMSK_VAL), ++ REG_REGION(0x38, 0x38, 4, DSUGRF_BASE, WMSK_VAL), ++ ++ /* lcore_grf */ ++ REG_REGION(0x20, 0x20, 4, LITCOREGRF_BASE, WMSK_VAL), ++ REG_REGION(0x28, 0x30, 4, LITCOREGRF_BASE, WMSK_VAL), ++ ++ /* bcore0_grf */ ++ REG_REGION(0x20, 0x20, 4, BIGCORE0GRF_BASE, WMSK_VAL), ++ REG_REGION(0x28, 0x30, 4, BIGCORE0GRF_BASE, WMSK_VAL), ++ ++ /* bcore1_grf */ ++ REG_REGION(0x20, 0x20, 4, BIGCORE1GRF_BASE, WMSK_VAL), ++ REG_REGION(0x28, 0x28, 4, BIGCORE1GRF_BASE, WMSK_VAL), ++}; ++ ++static struct reg_region pd_php_reg_rgns[] = { ++ /* php_grf */ ++ REG_REGION(0x000, 0x008, 4, PHPGRF_BASE, WMSK_VAL), ++ REG_REGION(0x014, 0x024, 4, PHPGRF_BASE, WMSK_VAL), ++ REG_REGION(0x028, 0x02c, 4, PHPGRF_BASE, 0), ++ REG_REGION(0x030, 0x03c, 4, PHPGRF_BASE, WMSK_VAL), ++ REG_REGION(0x05c, 0x060, 4, PHPGRF_BASE, WMSK_VAL), ++ REG_REGION(0x064, 0x068, 4, PHPGRF_BASE, 0), ++ REG_REGION(0x070, 0x070, 4, PHPGRF_BASE, WMSK_VAL), ++ REG_REGION(0x074, 0x0d0, 4, PHPGRF_BASE, 0), ++ REG_REGION(0x0d4, 0x0d4, 4, PHPGRF_BASE, WMSK_VAL), ++ REG_REGION(0x0e0, 0x0e0, 4, PHPGRF_BASE, 0), ++ REG_REGION(0x0e4, 0x0ec, 4, PHPGRF_BASE, WMSK_VAL), ++ REG_REGION(0x100, 0x104, 4, PHPGRF_BASE, WMSK_VAL), ++ REG_REGION(0x10c, 0x130, 4, PHPGRF_BASE, 0), ++ REG_REGION(0x138, 0x138, 4, PHPGRF_BASE, WMSK_VAL), ++ REG_REGION(0x144, 0x168, 4, PHPGRF_BASE, 0), ++ REG_REGION(0x16c, 0x174, 4, PHPGRF_BASE, WMSK_VAL), ++ ++ /* php_cru */ ++ REG_REGION(0x200, 0x218, 4, PHP_CRU_BASE, WMSK_VAL), ++ REG_REGION(0x800, 0x800, 4, PHP_CRU_BASE, WMSK_VAL), ++ REG_REGION(0xa00, 0xa00, 4, PHP_CRU_BASE, WMSK_VAL), ++ ++ /* pcie3phy_grf_cmn_con0 */ ++ REG_REGION(0x00, 0x00, 4, PCIE3PHYGRF_BASE, WMSK_VAL), ++}; ++ ++void qos_save(void) ++{ ++ uint32_t pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)); ++ ++ if ((pmu_pd_st0 & BIT(PD_GPU)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GPU_M0], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GPU_M1], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GPU_M2], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GPU_M3], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_NPU1)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_NPU1], 1); ++ if ((pmu_pd_st0 & BIT(PD_NPU2)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_NPU2], 1); ++ if ((pmu_pd_st0 & BIT(PD_NPUTOP)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_NPU0_MRO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_NPU0_MWR], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_MCU_NPU], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_RKVDEC1)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVDEC1], 1); ++ if ((pmu_pd_st0 & BIT(PD_RKVDEC0)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVDEC0], 1); ++ ++ if ((pmu_pd_st0 & BIT(PD_VENC1)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC1_M0RO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC1_M1RO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC1_M2WO], 1); ++ } ++ if ((pmu_pd_st0 & BIT(PD_VENC0)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC0_M0RO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC0_M1RO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC0_M2WO], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_RGA30)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RGA3_0], 1); ++ if ((pmu_pd_st0 & BIT(PD_AV1)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_AV1], 1); ++ if ((pmu_pd_st0 & BIT(PD_VDPU)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_DEC], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_ENC0], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_ENC1], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_ENC2], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_ENC3], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RGA2_MRO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RGA2_MWO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VDPU], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_IEP], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_VO0)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_HDCP0], 1); ++ if ((pmu_pd_st0 & BIT(PD_VO1)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_HDCP1], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_HDMIRX], 1); ++ } ++ if ((pmu_pd_st0 & BIT(PD_VOP)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VOP_M0], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VOP_M1], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_FEC)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_FISHEYE0], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_FISHEYE1], 1); ++ } ++ if ((pmu_pd_st0 & BIT(PD_ISP1)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_ISP1_MWO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_ISP1_MRO], 1); ++ } ++ if ((pmu_pd_st0 & BIT(PD_VI)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_ISP0_MWO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_ISP0_MRO], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VICAP_M0], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VICAP_M1], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_RGA31)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RGA3_1], 1); ++ ++ if ((pmu_pd_st0 & BIT(PD_USB)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_USB3_0], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_USB3_1], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_USBHOST_0], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_USBHOST_1], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_PHP)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GIC600_M0], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GIC600_M1], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_MMU600PCIE_TCU], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_MMU600PHP_TBU], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_MMU600PHP_TCU], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_SDIO)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_SDIO], 1); ++ if ((pmu_pd_st0 & BIT(PD_NVM0)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_FSPI], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_EMMC], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_SDMMC)) == 0) ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_SDMMC], 1); ++ ++ if ((pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) { ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_CRYPTONS], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_CRYPTOS], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DCF], 1); ++ } ++ ++ /* PD_DSU */ ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DSU_M0], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DSU_M1], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DSU_MP], 1); ++ rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DEBUG], 1); ++} ++ ++void qos_restore(void) ++{ ++ uint32_t pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)); ++ ++ if ((pmu_pd_st0 & BIT(PD_GPU)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GPU_M0], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GPU_M1], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GPU_M2], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GPU_M3], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_NPU1)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_NPU1], 1); ++ if ((pmu_pd_st0 & BIT(PD_NPU2)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_NPU2], 1); ++ if ((pmu_pd_st0 & BIT(PD_NPUTOP)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_NPU0_MRO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_NPU0_MWR], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_MCU_NPU], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_RKVDEC1)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVDEC1], 1); ++ if ((pmu_pd_st0 & BIT(PD_RKVDEC0)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVDEC0], 1); ++ ++ if ((pmu_pd_st0 & BIT(PD_VENC1)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC1_M0RO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC1_M1RO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC1_M2WO], 1); ++ } ++ if ((pmu_pd_st0 & BIT(PD_VENC0)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC0_M0RO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC0_M1RO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC0_M2WO], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_RGA30)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RGA3_0], 1); ++ if ((pmu_pd_st0 & BIT(PD_AV1)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_AV1], 1); ++ if ((pmu_pd_st0 & BIT(PD_VDPU)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_DEC], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_ENC0], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_ENC1], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_ENC2], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_ENC3], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RGA2_MRO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RGA2_MWO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VDPU], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_IEP], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_VO0)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_HDCP0], 1); ++ if ((pmu_pd_st0 & BIT(PD_VO1)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_HDCP1], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_HDMIRX], 1); ++ } ++ if ((pmu_pd_st0 & BIT(PD_VOP)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VOP_M0], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VOP_M1], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_FEC)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_FISHEYE0], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_FISHEYE1], 1); ++ } ++ if ((pmu_pd_st0 & BIT(PD_ISP1)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_ISP1_MWO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_ISP1_MRO], 1); ++ } ++ if ((pmu_pd_st0 & BIT(PD_VI)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_ISP0_MWO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_ISP0_MRO], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VICAP_M0], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VICAP_M1], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_RGA31)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RGA3_1], 1); ++ ++ if ((pmu_pd_st0 & BIT(PD_USB)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_USB3_0], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_USB3_1], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_USBHOST_0], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_USBHOST_1], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_PHP)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GIC600_M0], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GIC600_M1], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_MMU600PCIE_TCU], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_MMU600PHP_TBU], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_MMU600PHP_TCU], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_SDIO)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_SDIO], 1); ++ if ((pmu_pd_st0 & BIT(PD_NVM0)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_FSPI], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_EMMC], 1); ++ } ++ ++ if ((pmu_pd_st0 & BIT(PD_SDMMC)) == 0) ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_SDMMC], 1); ++ ++ if ((pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) { ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_CRYPTONS], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_CRYPTOS], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DCF], 1); ++ } ++ ++ /* PD_DSU */ ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DSU_M0], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DSU_M1], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DSU_MP], 1); ++ rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DEBUG], 1); ++} ++ ++void pd_crypto_save(void) ++{ ++ rockchip_reg_rgn_save(pd_crypto_reg_rgns, ARRAY_SIZE(pd_crypto_reg_rgns)); ++} ++ ++void pd_crypto_restore(void) ++{ ++ rockchip_reg_rgn_restore(pd_crypto_reg_rgns, ARRAY_SIZE(pd_crypto_reg_rgns)); ++} ++ ++static uint32_t b0_cru_mode; ++static uint32_t b1_cru_mode; ++static uint32_t dsu_cru_mode; ++static uint32_t bcore0_cru_sel_con2, bcore1_cru_sel_con2; ++ ++void pd_dsu_core_save(void) ++{ ++ b0_cru_mode = mmio_read_32(BIGCORE0CRU_BASE + 0x280); ++ b1_cru_mode = mmio_read_32(BIGCORE1CRU_BASE + 0x280); ++ dsu_cru_mode = mmio_read_32(DSUCRU_BASE + 0x280); ++ bcore0_cru_sel_con2 = mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2)); ++ bcore1_cru_sel_con2 = mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2)); ++ ++ rockchip_reg_rgn_save(pd_dsu_reg_rgns, ARRAY_SIZE(pd_dsu_reg_rgns)); ++} ++ ++void pd_dsu_core_restore(void) ++{ ++ /* switch bcore0/1 pclk root to 24M */ ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), ++ BITS_WITH_WMASK(2, 0x3, 0)); ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), ++ BITS_WITH_WMASK(2, 0x3, 0)); ++ ++ /* slow mode */ ++ mmio_write_32(BIGCORE0CRU_BASE + 0x280, 0x00030000); ++ mmio_write_32(BIGCORE1CRU_BASE + 0x280, 0x00030000); ++ mmio_write_32(DSUCRU_BASE + 0x280, 0x00030000); ++ ++ rockchip_reg_rgn_restore(pd_dsu_reg_rgns, ARRAY_SIZE(pd_dsu_reg_rgns)); ++ ++ /* trigger dsu/lcore/bcore mem_cfg */ ++ mmio_write_32(DSUGRF_BASE + 0x18, BITS_WITH_WMASK(1, 0x1, 14)); ++ mmio_write_32(LITCOREGRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5)); ++ mmio_write_32(BIGCORE0GRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5)); ++ mmio_write_32(BIGCORE1GRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5)); ++ udelay(1); ++ mmio_write_32(DSUGRF_BASE + 0x18, BITS_WITH_WMASK(0, 0x1, 14)); ++ mmio_write_32(LITCOREGRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5)); ++ mmio_write_32(BIGCORE0GRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5)); ++ mmio_write_32(BIGCORE1GRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5)); ++ ++ /* wait lock */ ++ pm_pll_wait_lock(BIGCORE0CRU_BASE + 0x00); ++ pm_pll_wait_lock(BIGCORE1CRU_BASE + 0x20); ++ pm_pll_wait_lock(DSUCRU_BASE + 0x40); ++ ++ /* restore mode */ ++ mmio_write_32(BIGCORE0CRU_BASE + 0x280, WITH_16BITS_WMSK(b0_cru_mode)); ++ mmio_write_32(BIGCORE1CRU_BASE + 0x280, WITH_16BITS_WMSK(b1_cru_mode)); ++ mmio_write_32(DSUCRU_BASE + 0x280, WITH_16BITS_WMSK(dsu_cru_mode)); ++ ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), ++ WITH_16BITS_WMSK(bcore0_cru_sel_con2)); ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), ++ WITH_16BITS_WMSK(bcore1_cru_sel_con2)); ++} ++ ++static uint32_t php_ppll_con0; ++ ++void pd_php_save(void) ++{ ++ php_ppll_con0 = mmio_read_32(PHP_CRU_BASE + 0x200); ++ ++ /* php_ppll bypass */ ++ mmio_write_32(PHP_CRU_BASE + 0x200, BITS_WITH_WMASK(1u, 1u, 15)); ++ dsb(); ++ isb(); ++ rockchip_reg_rgn_save(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns)); ++} ++ ++void pd_php_restore(void) ++{ ++ rockchip_reg_rgn_restore(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns)); ++ ++ pm_pll_wait_lock(PHP_CRU_BASE + 0x200); ++ ++ /* restore php_ppll bypass */ ++ mmio_write_32(PHP_CRU_BASE + 0x200, WITH_16BITS_WMSK(php_ppll_con0)); ++} ++ ++void pm_reg_rgns_init(void) ++{ ++ rockchip_alloc_region_mem(qos_reg_rgns, ARRAY_SIZE(qos_reg_rgns)); ++ rockchip_alloc_region_mem(pd_crypto_reg_rgns, ARRAY_SIZE(pd_crypto_reg_rgns)); ++ rockchip_alloc_region_mem(pd_dsu_reg_rgns, ARRAY_SIZE(pd_dsu_reg_rgns)); ++ rockchip_alloc_region_mem(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns)); ++} +diff --git a/plat/rockchip/rk3588/drivers/pmu/pm_pd_regs.h b/plat/rockchip/rk3588/drivers/pmu/pm_pd_regs.h +new file mode 100644 +index 0000000..8baf69a +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/pmu/pm_pd_regs.h +@@ -0,0 +1,23 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef PM_PD_REGS_H ++#define PM_PD_REGS_H ++ ++#include ++ ++void qos_save(void); ++void qos_restore(void); ++void pd_crypto_save(void); ++void pd_crypto_restore(void); ++void pd_dsu_core_save(void); ++void pd_dsu_core_restore(void); ++void pd_php_save(void); ++void pd_php_restore(void); ++ ++void pm_reg_rgns_init(void); ++ ++#endif +diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c +new file mode 100644 +index 0000000..83d6cad +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c +@@ -0,0 +1,1439 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PSRAM_SP_TOP ((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf) ++#define NONBOOT_CPUS_OFF_LOOP (500000) ++ ++#define DSUGRF_REG_CNT (0x78 / 4 + 1) ++#define BCORE_GRF_REG_CNT (0x30 / 4 + 1) ++#define LCORE_GRF_REG_CNT (0x30 / 4 + 1) ++ ++#define CENTER_GRF_REG_CNT (0x20 / 4 + 1) ++ ++static struct psram_data_t *psram_sleep_cfg = ++ (struct psram_data_t *)&sys_sleep_flag_sram; ++ ++static int8_t pd_repair_map[] = { ++ [PD_GPU] = PD_RPR_GPU, ++ [PD_NPU] = -1, ++ [PD_VCODEC] = -1, ++ [PD_NPUTOP] = PD_RPR_NPUTOP, ++ [PD_NPU1] = PD_RPR_NPU1, ++ [PD_NPU2] = PD_RPR_NPU2, ++ [PD_VENC0] = PD_RPR_VENC0, ++ [PD_VENC1] = PD_RPR_VENC1, ++ [PD_RKVDEC0] = PD_RPR_RKVDEC0, ++ [PD_RKVDEC1] = PD_RPR_RKVDEC1, ++ [PD_VDPU] = PD_RPR_VDPU, ++ [PD_RGA30] = PD_RPR_RGA30, ++ [PD_AV1] = PD_RPR_AV1, ++ [PD_VI] = PD_RPR_VI, ++ [PD_FEC] = PD_RPR_FEC, ++ [PD_ISP1] = PD_RPR_ISP1, ++ [PD_RGA31] = PD_RPR_RGA31, ++ [PD_VOP] = PD_RPR_VOP, ++ [PD_VO0] = PD_RPR_VO0, ++ [PD_VO1] = PD_RPR_VO1, ++ [PD_AUDIO] = PD_RPR_AUDIO, ++ [PD_PHP] = PD_RPR_PHP, ++ [PD_GMAC] = PD_RPR_GMAC, ++ [PD_PCIE] = PD_RPR_PCIE, ++ [PD_NVM] = -1, ++ [PD_NVM0] = PD_RPR_NVM0, ++ [PD_SDIO] = PD_RPR_SDIO, ++ [PD_USB] = PD_RPR_USB, ++ [PD_SECURE] = -1, ++ [PD_SDMMC] = PD_RPR_SDMMC, ++ [PD_CRYPTO] = PD_RPR_CRYPTO, ++ [PD_CENTER] = PD_RPR_CENTER, ++ [PD_DDR01] = PD_RPR_DDR01, ++ [PD_DDR23] = PD_RPR_DDR23, ++}; ++ ++struct rk3588_sleep_ddr_data { ++ uint32_t gpio0a_iomux_l, gpio0a_iomux_h, gpio0b_iomux_l; ++ uint32_t pmu_pd_st0, bus_idle_st0, qch_pwr_st; ++ uint32_t pmu2_vol_gate_con[3], pmu2_submem_gate_sft_con0; ++ uint32_t pmu2_bisr_con0; ++ uint32_t cpll_con0; ++ uint32_t cru_mode_con, busscru_mode_con; ++ uint32_t bussgrf_soc_con7; ++ uint32_t pmu0grf_soc_con0, pmu0grf_soc_con1, pmu0grf_soc_con3; ++ uint32_t pmu1grf_soc_con2, pmu1grf_soc_con7, pmu1grf_soc_con8, pmu1grf_soc_con9; ++ uint32_t pmu0sgrf_soc_con1; ++ uint32_t pmu1sgrf_soc_con14; ++ uint32_t ddrgrf_chn_con0[4], ddrgrf_chn_con1[4], ++ ddrgrf_chn_con2[4], pmu1_ddr_pwr_sft_con[4]; ++ uint32_t pmu1cru_clksel_con1; ++}; ++ ++static struct rk3588_sleep_ddr_data ddr_data; ++ ++struct rk3588_sleep_pmusram_data { ++ uint32_t dsusgrf_soc_con[DSUSGRF_SOC_CON_CNT], ++ dsusgrf_ddr_hash_con[DSUSGRF_DDR_HASH_CON_CNT]; ++ uint32_t dsu_ddr_fw_rgn_reg[FIREWALL_DSU_RGN_CNT], ++ dsu_ddr_fw_mst_reg[FIREWALL_DSU_MST_CNT], ++ dsu_ddr_fw_con_reg[FIREWALL_DSU_CON_CNT]; ++ uint32_t busioc_gpio0b_iomux_h; ++}; ++ ++static __pmusramdata struct rk3588_sleep_pmusram_data pmusram_data; ++ ++static __pmusramfunc void dsu_restore_early(void) ++{ ++ int i; ++ ++ /* dsusgrf */ ++ for (i = 0; i < DSUSGRF_SOC_CON_CNT; i++) ++ mmio_write_32(DSUSGRF_BASE + DSUSGRF_SOC_CON(i), ++ WITH_16BITS_WMSK(pmusram_data.dsusgrf_soc_con[i])); ++ ++ for (i = 0; i < DSUSGRF_DDR_HASH_CON_CNT; i++) ++ mmio_write_32(DSUSGRF_BASE + DSUSGRF_DDR_HASH_CON(i), ++ pmusram_data.dsusgrf_ddr_hash_con[i]); ++ ++ /* dsu ddr firewall */ ++ for (i = 0; i < FIREWALL_DSU_RGN_CNT; i++) ++ mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(i), ++ pmusram_data.dsu_ddr_fw_rgn_reg[i]); ++ ++ for (i = 0; i < FIREWALL_DSU_MST_CNT; i++) ++ mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(i), ++ pmusram_data.dsu_ddr_fw_mst_reg[i]); ++ ++ for (i = 0; i < FIREWALL_DSU_CON_CNT; i++) ++ mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i), ++ pmusram_data.dsu_ddr_fw_con_reg[i]); ++} ++ ++static __pmusramfunc void ddr_resume(void) ++{ ++ dsu_restore_early(); ++} ++ ++static void dsu_core_save(void) ++{ ++ int i; ++ ++ /* dsusgrf */ ++ for (i = 0; i < DSUSGRF_SOC_CON_CNT; i++) ++ pmusram_data.dsusgrf_soc_con[i] = ++ mmio_read_32(DSUSGRF_BASE + DSUSGRF_SOC_CON(i)); ++ ++ for (i = 0; i < DSUSGRF_DDR_HASH_CON_CNT; i++) ++ pmusram_data.dsusgrf_ddr_hash_con[i] = ++ mmio_read_32(DSUSGRF_BASE + DSUSGRF_DDR_HASH_CON(i)); ++ ++ /* dsu ddr firewall */ ++ for (i = 0; i < FIREWALL_DSU_RGN_CNT; i++) ++ pmusram_data.dsu_ddr_fw_rgn_reg[i] = ++ mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(i)); ++ ++ for (i = 0; i < FIREWALL_DSU_MST_CNT; i++) ++ pmusram_data.dsu_ddr_fw_mst_reg[i] = ++ mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(i)); ++ ++ for (i = 0; i < FIREWALL_DSU_CON_CNT; i++) ++ pmusram_data.dsu_ddr_fw_con_reg[i] = ++ mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i)); ++ ++ pvtplls_suspend(); ++ pd_dsu_core_save(); ++} ++ ++static void dsu_core_restore(void) ++{ ++ pd_dsu_core_restore(); ++ pvtplls_resume(); ++} ++ ++static uint32_t clk_save[CRU_CLKGATE_CON_CNT + PHPCRU_CLKGATE_CON_CNT + ++ SECURECRU_CLKGATE_CON_CNT + PMU1CRU_CLKGATE_CON_CNT]; ++ ++void clk_gate_con_save(void) ++{ ++ int i, j = 0; ++ ++ for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) ++ clk_save[j] = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); ++ ++ clk_save[j] = mmio_read_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON); ++ ++ for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++, j++) ++ clk_save[j] = mmio_read_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i)); ++ ++ for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) ++ clk_save[j] = mmio_read_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i)); ++} ++ ++void clk_gate_con_disable(void) ++{ ++ int i; ++ ++ for (i = 0; i < CRU_CLKGATE_CON_CNT; i++) ++ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); ++ ++ mmio_write_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON, 0xffff0000); ++ ++ for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++) ++ mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), 0xffff0000); ++ ++ for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++) ++ mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); ++} ++ ++void clk_gate_con_restore(void) ++{ ++ int i, j = 0; ++ ++ for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) ++ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), ++ WITH_16BITS_WMSK(clk_save[j])); ++ ++ mmio_write_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON, ++ WITH_16BITS_WMSK(clk_save[j])); ++ ++ for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++, j++) ++ mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), ++ WITH_16BITS_WMSK(clk_save[j])); ++ ++ for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) ++ mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), ++ WITH_16BITS_WMSK(clk_save[j])); ++} ++ ++static void pmu_bus_idle_req(uint32_t bus, uint32_t state) ++{ ++ uint32_t wait_cnt = 0; ++ ++ mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON(bus / 16), ++ BITS_WITH_WMASK(state, 0x1, bus % 16)); ++ ++ while (pmu_bus_idle_st(bus) != state || ++ pmu_bus_idle_ack(bus) != state) { ++ if (++wait_cnt > BUS_IDLE_LOOP) ++ break; ++ udelay(1); ++ } ++ ++ if (wait_cnt > BUS_IDLE_LOOP) ++ WARN("%s: can't wait state %d for bus %d (0x%x)\n", ++ __func__, state, bus, ++ mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(bus / 32))); ++} ++ ++static void pmu_qch_pwr_ctlr(uint32_t msk, uint32_t state) ++{ ++ uint32_t wait_cnt = 0; ++ ++ if (state != 0) ++ state = msk; ++ ++ mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_SFTCON, ++ BITS_WITH_WMASK(state, msk, 0)); ++ ++ while ((mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & msk) != state) { ++ if (++wait_cnt > QCH_PWR_LOOP) ++ break; ++ udelay(1); ++ } ++ ++ if (wait_cnt > BUS_IDLE_LOOP) ++ WARN("%s: can't wait qch:0x%x to state:0x%x (0x%x)\n", ++ __func__, msk, state, ++ mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS)); ++} ++ ++static inline uint32_t pmu_power_domain_chain_st(uint32_t pd) ++{ ++ return mmio_read_32(PMU_BASE + PMU2_PWR_CHAIN1_ST(pd / 32)) & BIT(pd % 32) ? ++ pmu_pd_on : ++ pmu_pd_off; ++} ++ ++static inline uint32_t pmu_power_domain_mem_st(uint32_t pd) ++{ ++ return mmio_read_32(PMU_BASE + PMU2_PWR_MEM_ST(pd / 32)) & BIT(pd % 32) ? ++ pmu_pd_off : ++ pmu_pd_on; ++} ++ ++static inline uint32_t pmu_power_domain_st(uint32_t pd) ++{ ++ int8_t pd_repair = pd_repair_map[pd]; ++ ++ if (pd_repair >= 0) ++ return mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4)) & BIT(pd_repair) ? ++ pmu_pd_on : ++ pmu_pd_off; ++ else ++ return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(pd / 32)) & BIT(pd % 32) ? ++ pmu_pd_off : ++ pmu_pd_on; ++} ++ ++static int pmu_power_domain_pd_to_mem_st(uint32_t pd, uint32_t *pd_mem_st) ++{ ++ uint32_t mem_st; ++ ++ switch (pd) { ++ case PD_NPUTOP: ++ mem_st = PD_NPU_TOP_MEM_ST; ++ break; ++ case PD_NPU1: ++ mem_st = PD_NPU1_MEM_ST; ++ break; ++ case PD_NPU2: ++ mem_st = PD_NPU2_MEM_ST; ++ break; ++ case PD_VENC0: ++ mem_st = PD_VENC0_MEM_ST; ++ break; ++ case PD_VENC1: ++ mem_st = PD_VENC1_MEM_ST; ++ break; ++ case PD_RKVDEC0: ++ mem_st = PD_RKVDEC0_MEM_ST; ++ break; ++ case PD_RKVDEC1: ++ mem_st = PD_RKVDEC1_MEM_ST; ++ break; ++ case PD_RGA30: ++ mem_st = PD_RGA30_MEM_ST; ++ break; ++ case PD_AV1: ++ mem_st = PD_AV1_MEM_ST; ++ break; ++ case PD_VI: ++ mem_st = PD_VI_MEM_ST; ++ break; ++ case PD_FEC: ++ mem_st = PD_FEC_MEM_ST; ++ break; ++ case PD_ISP1: ++ mem_st = PD_ISP1_MEM_ST; ++ break; ++ case PD_RGA31: ++ mem_st = PD_RGA31_MEM_ST; ++ break; ++ case PD_VOP: ++ mem_st = PD_VOP_MEM_ST; ++ break; ++ case PD_VO0: ++ mem_st = PD_VO0_MEM_ST; ++ break; ++ case PD_VO1: ++ mem_st = PD_VO1_MEM_ST; ++ break; ++ case PD_AUDIO: ++ mem_st = PD_AUDIO_MEM_ST; ++ break; ++ case PD_PHP: ++ mem_st = PD_PHP_MEM_ST; ++ break; ++ case PD_GMAC: ++ mem_st = PD_GMAC_MEM_ST; ++ break; ++ case PD_PCIE: ++ mem_st = PD_PCIE_MEM_ST; ++ break; ++ case PD_NVM0: ++ mem_st = PD_NVM0_MEM_ST; ++ break; ++ case PD_SDIO: ++ mem_st = PD_SDIO_MEM_ST; ++ break; ++ case PD_USB: ++ mem_st = PD_USB_MEM_ST; ++ break; ++ case PD_SDMMC: ++ mem_st = PD_SDMMC_MEM_ST; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ *pd_mem_st = mem_st; ++ ++ return 0; ++} ++ ++static int pmu_power_domain_reset_mem(uint32_t pd, uint32_t pd_mem_st) ++{ ++ uint32_t loop = 0; ++ int ret = 0; ++ ++ while (pmu_power_domain_chain_st(pd_mem_st) != pmu_pd_on) { ++ udelay(1); ++ loop++; ++ if (loop >= PD_CTR_LOOP) { ++ WARN("%s: %d chain up time out\n", __func__, pd); ++ ret = -EINVAL; ++ goto error; ++ } ++ } ++ ++ udelay(60); ++ ++ mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), ++ BITS_WITH_WMASK(pmu_pd_off, 0x1, pd % 16)); ++ dsb(); ++ ++ loop = 0; ++ while (pmu_power_domain_mem_st(pd_mem_st) != pmu_pd_off) { ++ udelay(1); ++ loop++; ++ if (loop >= PD_CTR_LOOP) { ++ WARN("%s: %d mem down time out\n", __func__, pd); ++ ret = -EINVAL; ++ goto error; ++ } ++ } ++ ++ mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), ++ BITS_WITH_WMASK(pmu_pd_on, 0x1, pd % 16)); ++ dsb(); ++ ++ loop = 0; ++ while (pmu_power_domain_mem_st(pd_mem_st) != pmu_pd_on) { ++ udelay(1); ++ loop++; ++ if (loop >= PD_CTR_LOOP) { ++ WARN("%s: %d mem up time out\n", __func__, pd); ++ ret = -EINVAL; ++ goto error; ++ } ++ } ++ ++ return 0; ++ ++error: ++ return ret; ++} ++ ++static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) ++{ ++ uint32_t loop = 0; ++ uint32_t is_mem_on = pmu_pd_off; ++ uint32_t pd_mem_st; ++ int ret = 0; ++ ++ if (pd_state == pmu_pd_on) { ++ ret = pmu_power_domain_pd_to_mem_st(pd, &pd_mem_st); ++ if (ret == 0) { ++ is_mem_on = pmu_power_domain_mem_st(pd_mem_st); ++ if (is_mem_on == pmu_pd_on) ++ WARN("%s: %d mem is up\n", __func__, pd); ++ } ++ } ++ ++ mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(pd / 16), ++ BITS_WITH_WMASK(pd_state, 0x1, pd % 16)); ++ dsb(); ++ ++ if (is_mem_on == pmu_pd_on) { ++ ret = pmu_power_domain_reset_mem(pd, pd_mem_st); ++ if (ret != 0) ++ goto out; ++ WARN("%s: %d mem reset ok\n", __func__, pd); ++ } ++ ++ while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { ++ udelay(1); ++ loop++; ++ } ++ ++ if (pmu_power_domain_st(pd) != pd_state) { ++ WARN("%s: %d, %d, (0x%x, 0x%x) error!\n", __func__, pd, pd_state, ++ mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)), ++ mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4))); ++ ret = -EINVAL; ++ } ++ ++out: ++ return ret; ++} ++ ++static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) ++{ ++ uint32_t state; ++ ++ if (pmu_power_domain_st(pd_id) == pd_state) ++ goto out; ++ ++ if (pd_state == pmu_pd_on) ++ pmu_power_domain_ctr(pd_id, pd_state); ++ ++ state = (pd_state == pmu_pd_off) ? bus_idle : bus_active; ++ ++ switch (pd_id) { ++ case PD_GPU: ++ pmu_bus_idle_req(BUS_ID_GPU, state); ++ break; ++ case PD_NPUTOP: ++ pmu_bus_idle_req(BUS_ID_NPUTOP, state); ++ break; ++ case PD_NPU1: ++ pmu_bus_idle_req(BUS_ID_NPU1, state); ++ break; ++ case PD_NPU2: ++ pmu_bus_idle_req(BUS_ID_NPU2, state); ++ break; ++ case PD_VENC0: ++ pmu_bus_idle_req(BUS_ID_RKVENC0, state); ++ break; ++ case PD_VENC1: ++ pmu_bus_idle_req(BUS_ID_RKVENC1, state); ++ break; ++ case PD_RKVDEC0: ++ pmu_bus_idle_req(BUS_ID_RKVDEC0, state); ++ break; ++ case PD_RKVDEC1: ++ pmu_bus_idle_req(BUS_ID_RKVDEC1, state); ++ break; ++ case PD_VDPU: ++ pmu_bus_idle_req(BUS_ID_VDPU, state); ++ break; ++ case PD_AV1: ++ pmu_bus_idle_req(BUS_ID_AV1, state); ++ break; ++ case PD_VI: ++ pmu_bus_idle_req(BUS_ID_VI, state); ++ break; ++ case PD_ISP1: ++ pmu_bus_idle_req(BUS_ID_ISP, state); ++ break; ++ case PD_RGA31: ++ pmu_bus_idle_req(BUS_ID_RGA31, state); ++ break; ++ case PD_VOP: ++ pmu_bus_idle_req(BUS_ID_VOP_CHANNEL, state); ++ pmu_bus_idle_req(BUS_ID_VOP, state); ++ break; ++ case PD_VO0: ++ pmu_bus_idle_req(BUS_ID_VO0, state); ++ break; ++ case PD_VO1: ++ pmu_bus_idle_req(BUS_ID_VO1, state); ++ break; ++ case PD_AUDIO: ++ pmu_bus_idle_req(BUS_ID_AUDIO, state); ++ break; ++ case PD_PHP: ++ pmu_bus_idle_req(BUS_ID_PHP, state); ++ break; ++ case PD_NVM: ++ pmu_bus_idle_req(BUS_ID_NVM, state); ++ break; ++ case PD_SDIO: ++ pmu_bus_idle_req(BUS_ID_SDIO, state); ++ break; ++ case PD_USB: ++ pmu_bus_idle_req(BUS_ID_USB, state); ++ break; ++ case PD_SECURE: ++ pmu_bus_idle_req(BUS_ID_SECURE, state); ++ break; ++ default: ++ break; ++ } ++ ++ if (pd_state == pmu_pd_off) ++ pmu_power_domain_ctr(pd_id, pd_state); ++ ++out: ++ return 0; ++} ++ ++static void pmu_power_domains_suspend(void) ++{ ++ ddr_data.qch_pwr_st = ++ mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & PMU2_QCH_PWR_MSK; ++ ddr_data.pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)); ++ ddr_data.bus_idle_st0 = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(0)); ++ ++ qos_save(); ++ ++ if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) ++ pd_php_save(); ++ ++ if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) ++ pd_crypto_save(); ++ ++ pmu_qch_pwr_ctlr(0x20, 1); ++ pmu_qch_pwr_ctlr(0x40, 1); ++ pmu_qch_pwr_ctlr(0x1, 1); ++ pmu_qch_pwr_ctlr(0x2, 1); ++ pmu_qch_pwr_ctlr(0x4, 1); ++ pmu_qch_pwr_ctlr(0x8, 1); ++ pmu_qch_pwr_ctlr(0x10, 1); ++ ++ pmu_bus_idle_req(BUS_ID_VO1USBTOP, bus_idle); ++ pmu_bus_idle_req(BUS_ID_SECURE_VO1USB_CHANNEL, bus_idle); ++ ++ pmu_bus_idle_req(BUS_ID_USB, bus_idle); ++ ++ pmu_set_power_domain(PD_GPU, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_NPU1, pmu_pd_off); ++ pmu_set_power_domain(PD_NPU2, pmu_pd_off); ++ pmu_set_power_domain(PD_NPUTOP, pmu_pd_off); ++ pmu_set_power_domain(PD_NPU, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_RKVDEC1, pmu_pd_off); ++ pmu_set_power_domain(PD_RKVDEC0, pmu_pd_off); ++ pmu_set_power_domain(PD_VENC1, pmu_pd_off); ++ pmu_set_power_domain(PD_VENC0, pmu_pd_off); ++ pmu_set_power_domain(PD_VCODEC, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_RGA30, pmu_pd_off); ++ pmu_set_power_domain(PD_AV1, pmu_pd_off); ++ pmu_set_power_domain(PD_VDPU, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_VO0, pmu_pd_off); ++ pmu_set_power_domain(PD_VO1, pmu_pd_off); ++ pmu_set_power_domain(PD_VOP, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_FEC, pmu_pd_off); ++ pmu_set_power_domain(PD_ISP1, pmu_pd_off); ++ pmu_set_power_domain(PD_VI, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_RGA31, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_AUDIO, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_GMAC, pmu_pd_off); ++ pmu_set_power_domain(PD_PCIE, pmu_pd_off); ++ pmu_set_power_domain(PD_PHP, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_SDIO, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_NVM0, pmu_pd_off); ++ pmu_set_power_domain(PD_NVM, pmu_pd_off); ++ ++ pmu_set_power_domain(PD_SDMMC, pmu_pd_off); ++ pmu_set_power_domain(PD_CRYPTO, pmu_pd_off); ++} ++ ++static void pmu_power_domains_resume(void) ++{ ++ int i; ++ ++ pmu_set_power_domain(PD_CRYPTO, !!(ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO))); ++ pmu_set_power_domain(PD_SDMMC, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDMMC))); ++ ++ pmu_set_power_domain(PD_NVM, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM))); ++ pmu_set_power_domain(PD_NVM0, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM0))); ++ ++ pmu_set_power_domain(PD_SDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDIO))); ++ ++ pmu_set_power_domain(PD_PHP, !!(ddr_data.pmu_pd_st0 & BIT(PD_PHP))); ++ pmu_set_power_domain(PD_PCIE, !!(ddr_data.pmu_pd_st0 & BIT(PD_PCIE))); ++ pmu_set_power_domain(PD_GMAC, !!(ddr_data.pmu_pd_st0 & BIT(PD_GMAC))); ++ ++ pmu_set_power_domain(PD_AUDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_AUDIO))); ++ ++ pmu_set_power_domain(PD_USB, !!(ddr_data.pmu_pd_st0 & BIT(PD_USB))); ++ ++ pmu_set_power_domain(PD_RGA31, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA31))); ++ ++ pmu_set_power_domain(PD_VI, !!(ddr_data.pmu_pd_st0 & BIT(PD_VI))); ++ pmu_set_power_domain(PD_ISP1, !!(ddr_data.pmu_pd_st0 & BIT(PD_ISP1))); ++ pmu_set_power_domain(PD_FEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_FEC))); ++ ++ pmu_set_power_domain(PD_VOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_VOP))); ++ ++ pmu_set_power_domain(PD_VO1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO1))); ++ ++ pmu_set_power_domain(PD_VO0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO0))); ++ ++ pmu_set_power_domain(PD_VDPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_VDPU))); ++ pmu_set_power_domain(PD_AV1, !!(ddr_data.pmu_pd_st0 & BIT(PD_AV1))); ++ pmu_set_power_domain(PD_RGA30, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA30))); ++ ++ pmu_set_power_domain(PD_VCODEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_VCODEC))); ++ pmu_set_power_domain(PD_VENC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC0))); ++ pmu_set_power_domain(PD_VENC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC1))); ++ pmu_set_power_domain(PD_RKVDEC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC0))); ++ pmu_set_power_domain(PD_RKVDEC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC1))); ++ ++ pmu_set_power_domain(PD_NPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU))); ++ pmu_set_power_domain(PD_NPUTOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPUTOP))); ++ pmu_set_power_domain(PD_NPU2, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU2))); ++ pmu_set_power_domain(PD_NPU1, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU1))); ++ ++ pmu_set_power_domain(PD_GPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_GPU))); ++ ++ for (i = 0; i < 32; i++) ++ pmu_bus_idle_req(i, !!(ddr_data.bus_idle_st0 & BIT(i))); ++ ++ pmu_qch_pwr_ctlr(0x10, !!(ddr_data.qch_pwr_st & 0x10)); ++ pmu_qch_pwr_ctlr(0x8, !!(ddr_data.qch_pwr_st & 0x8)); ++ pmu_qch_pwr_ctlr(0x4, !!(ddr_data.qch_pwr_st & 0x4)); ++ pmu_qch_pwr_ctlr(0x2, !!(ddr_data.qch_pwr_st & 0x2)); ++ pmu_qch_pwr_ctlr(0x1, !!(ddr_data.qch_pwr_st & 0x1)); ++ pmu_qch_pwr_ctlr(0x40, !!(ddr_data.qch_pwr_st & 0x40)); ++ pmu_qch_pwr_ctlr(0x20, !!(ddr_data.qch_pwr_st & 0x20)); ++ ++ if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) ++ pd_crypto_restore(); ++ ++ if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) ++ pd_php_restore(); ++ ++ qos_restore(); ++} ++ ++static int cpus_power_domain_on(uint32_t cpu_id) ++{ ++ mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), ++ BITS_WITH_WMASK(0, 0x1, core_pm_en)); ++ mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), ++ BITS_WITH_WMASK(1, 0x1, core_pm_sft_wakeup_en)); ++ dsb(); ++ ++ return 0; ++} ++ ++static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) ++{ ++ uint32_t apm_value = BIT(core_pm_en); ++ ++ if (pd_cfg == core_pwr_wfi_int) ++ apm_value |= BIT(core_pm_int_wakeup_en); ++ ++ mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), ++ BITS_WITH_WMASK(apm_value, 0x3, 0)); ++ dsb(); ++ ++ return 0; ++} ++ ++static inline void cpus_pd_req_enter_wfi(void) ++{ ++ /* CORTEX_A55_CPUACTLR_EL1 */ ++ __asm__ volatile ("msr DBGPRCR_EL1, xzr\n" ++ "mrs x0, S3_0_C15_C2_7\n" ++ "orr x0, x0, #0x1\n" ++ "msr S3_0_C15_C2_7, x0\n" ++ "wfi_loop:\n" ++ "isb\n" ++ "wfi\n" ++ "b wfi_loop\n"); ++} ++ ++static void nonboot_cpus_off(void) ++{ ++ uint32_t boot_cpu, cpu, tmp; ++ uint32_t exp_st; ++ uint32_t bcore0_rst_msk = 0, bcore1_rst_msk = 0; ++ int wait_cnt; ++ ++ bcore0_rst_msk = CRU_BIGCPU02_RST_MSK | CRU_BIGCPU13_RST_MSK; ++ bcore1_rst_msk = CRU_BIGCPU02_RST_MSK | CRU_BIGCPU13_RST_MSK; ++ ++ mmio_write_32(BIGCORE0CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore0_rst_msk, 0)); ++ mmio_write_32(BIGCORE1CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore1_rst_msk, 0)); ++ ++ wait_cnt = NONBOOT_CPUS_OFF_LOOP; ++ exp_st = SYS_GRF_BIG_CPUS_WFE; ++ do { ++ wait_cnt--; ++ tmp = mmio_read_32(SYSGRF_BASE + SYS_GRF_SOC_STATUS(3)); ++ tmp &= SYS_GRF_BIG_CPUS_WFE; ++ } while (tmp != exp_st && wait_cnt); ++ ++ boot_cpu = plat_my_core_pos(); ++ ++ /* turn off noboot cpus */ ++ for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { ++ if (cpu == boot_cpu) ++ continue; ++ cpus_power_domain_off(cpu, core_pwr_wfi); ++ } ++ ++ mmio_write_32(SRAM_BASE + 0x08, (uintptr_t)&cpus_pd_req_enter_wfi); ++ mmio_write_32(SRAM_BASE + 0x04, 0xdeadbeaf); ++ ++ dsb(); ++ isb(); ++ ++ sev(); ++ ++ wait_cnt = NONBOOT_CPUS_OFF_LOOP; ++ do { ++ wait_cnt--; ++ tmp = mmio_read_32(PMU_BASE + PMU2_CLUSTER_ST); ++ tmp &= CLUSTER_STS_NONBOOT_CPUS_DWN; ++ } while (tmp != CLUSTER_STS_NONBOOT_CPUS_DWN && wait_cnt); ++ ++ if (tmp != CLUSTER_STS_NONBOOT_CPUS_DWN) ++ ERROR("nonboot cpus status(%x) error!\n", tmp); ++} ++ ++int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, ++ uint64_t entrypoint) ++{ ++ uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); ++ ++ assert(cpu_id < PLATFORM_CORE_COUNT); ++ assert(cpuson_flags[cpu_id] == 0); ++ cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; ++ cpuson_entry_point[cpu_id] = entrypoint; ++ dsb(); ++ ++ flush_dcache_range((uintptr_t)cpuson_flags, sizeof(cpuson_flags)); ++ flush_dcache_range((uintptr_t)cpuson_entry_point, ++ sizeof(cpuson_entry_point)); ++ dsb(); ++ isb(); ++ ++ cpus_power_domain_on(cpu_id); ++ ++ return PSCI_E_SUCCESS; ++} ++ ++int rockchip_soc_cores_pwr_dm_on_finish(void) ++{ ++ uint32_t cpu_id = plat_my_core_pos(); ++ ++ mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), ++ BITS_WITH_WMASK(0, 0xf, 0)); ++ ++ return PSCI_E_SUCCESS; ++} ++ ++int rockchip_soc_cores_pwr_dm_off(void) ++{ ++ uint32_t cpu_id = plat_my_core_pos(); ++ ++ cpus_power_domain_off(cpu_id, core_pwr_wfi); ++ ++ return PSCI_E_SUCCESS; ++} ++ ++int rockchip_soc_cores_pwr_dm_suspend(void) ++{ ++ uint32_t cpu_id = plat_my_core_pos(); ++ ++ assert(cpu_id < PLATFORM_CORE_COUNT); ++ ++ cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; ++ cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); ++ dsb(); ++ flush_dcache_range((uintptr_t)cpuson_flags, sizeof(cpuson_flags)); ++ flush_dcache_range((uintptr_t)cpuson_entry_point, ++ sizeof(cpuson_entry_point)); ++ dsb(); ++ isb(); ++ ++ cpus_power_domain_off(cpu_id, core_pwr_wfi_int); ++ ++ __asm__ volatile ("msr DBGPRCR_EL1, xzr\n" ++ "mrs x0, S3_0_C15_C2_7\n" ++ "orr x0, x0, #0x1\n" ++ "msr S3_0_C15_C2_7, x0\n"); ++ ++ return PSCI_E_SUCCESS; ++} ++ ++int rockchip_soc_cores_pwr_dm_resume(void) ++{ ++ uint32_t cpu_id = plat_my_core_pos(); ++ ++ mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), ++ BITS_WITH_WMASK(0, 0x3, 0)); ++ ++ dsb(); ++ ++ return PSCI_E_SUCCESS; ++} ++ ++static void ddr_sleep_config(void) ++{ ++ int i; ++ ++ if (pmu_power_domain_st(PD_DDR01) == 0) { ++ ddr_data.ddrgrf_chn_con0[0] = ++ mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0)); ++ ddr_data.ddrgrf_chn_con0[1] = ++ mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0)); ++ ddr_data.ddrgrf_chn_con1[0] = ++ mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1)); ++ ddr_data.ddrgrf_chn_con1[1] = ++ mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1)); ++ ddr_data.ddrgrf_chn_con2[0] = ++ mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2)); ++ ddr_data.ddrgrf_chn_con2[1] = ++ mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2)); ++ ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 0x20002000); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 0x20002000); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 0x08000000); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 0x08000000); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0), 0x00200020); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0), 0x00200020); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1), 0x00400040); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1), 0x00400040); ++ } ++ ++ if (pmu_power_domain_st(PD_DDR23) == 0) { ++ ddr_data.ddrgrf_chn_con0[2] = ++ mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0)); ++ ddr_data.ddrgrf_chn_con0[3] = ++ mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0)); ++ ddr_data.ddrgrf_chn_con1[2] = ++ mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1)); ++ ddr_data.ddrgrf_chn_con1[3] = ++ mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1)); ++ ddr_data.ddrgrf_chn_con2[2] = ++ mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2)); ++ ddr_data.ddrgrf_chn_con2[3] = ++ mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2)); ++ ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 0x20002000); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 0x20002000); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 0x08000000); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 0x08000000); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0), 0x00200020); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0), 0x00200020); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1), 0x00400040); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1), 0x00400040); ++ } ++ ++ for (i = 0; i < DDR_CHN_CNT; i++) { ++ ddr_data.pmu1_ddr_pwr_sft_con[i] = ++ mmio_read_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i)); ++ mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), 0x0fff0900); ++ } ++} ++ ++static void ddr_sleep_config_restore(void) ++{ ++ int i; ++ ++ for (i = 0; i < DDR_CHN_CNT; i++) { ++ mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), ++ 0x0fff0000 | ddr_data.pmu1_ddr_pwr_sft_con[i]); ++ } ++ ++ if (pmu_power_domain_st(PD_DDR01) == 0) { ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1), ++ 0x00400000 | ddr_data.ddrgrf_chn_con1[0]); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1), ++ 0x00400000 | ddr_data.ddrgrf_chn_con1[1]); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0), ++ 0x00200000 | ddr_data.ddrgrf_chn_con0[0]); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0), ++ 0x00200000 | ddr_data.ddrgrf_chn_con0[1]); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), ++ 0x28000000 | ddr_data.ddrgrf_chn_con2[0]); ++ mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), ++ 0x28000000 | ddr_data.ddrgrf_chn_con2[1]); ++ } ++ ++ if (pmu_power_domain_st(PD_DDR23) == 0) { ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1), ++ 0x00400000 | ddr_data.ddrgrf_chn_con1[2]); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1), ++ 0x00400000 | ddr_data.ddrgrf_chn_con1[3]); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0), ++ 0x00200000 | ddr_data.ddrgrf_chn_con0[2]); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0), ++ 0x00200000 | ddr_data.ddrgrf_chn_con0[3]); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), ++ 0x28000000 | ddr_data.ddrgrf_chn_con2[2]); ++ mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), ++ 0x28000000 | ddr_data.ddrgrf_chn_con2[3]); ++ } ++} ++ ++static void pmu_sleep_config(void) ++{ ++ uint32_t pmu1_pwr_con, pmu1_wkup_int_con, pmu1_cru_pwr_con; ++ uint32_t pmu1_ddr_pwr_con, pmu1_pll_pd_con[2] = {0}; ++ uint32_t pmu2_dsu_pwr_con, pmu2_core_pwr_con, pmu2_clst_idle_con; ++ uint32_t pmu2_bus_idle_con[3] = {0}, pmu2_pwr_gate_con[3] = {0}; ++ uint32_t pmu2_vol_gate_con[3] = {0}, pmu2_qch_pwr_con = 0; ++ int i; ++ ++ ddr_data.pmu1grf_soc_con7 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(7)); ++ ddr_data.pmu1grf_soc_con8 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(8)); ++ ddr_data.pmu1grf_soc_con9 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(9)); ++ ddr_data.pmu1sgrf_soc_con14 = mmio_read_32(PMU1SGRF_BASE + PMU1_SGRF_SOC_CON(14)); ++ ddr_data.pmu0sgrf_soc_con1 = mmio_read_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1)); ++ ddr_data.pmu0grf_soc_con1 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(1)); ++ ++ ddr_data.pmu2_vol_gate_con[0] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(0)); ++ ddr_data.pmu2_vol_gate_con[1] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(1)); ++ ddr_data.pmu2_vol_gate_con[2] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(2)); ++ ++ ddr_data.pmu2_submem_gate_sft_con0 = ++ mmio_read_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0)); ++ ++ /* save pmic_sleep iomux gpio0_a4 */ ++ ddr_data.gpio0a_iomux_l = mmio_read_32(PMU0IOC_BASE + 0); ++ ddr_data.gpio0a_iomux_h = mmio_read_32(PMU0IOC_BASE + 4); ++ ddr_data.pmu0grf_soc_con3 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3)); ++ ++ /* PMU1 repair disable */ ++ mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(0), 0x00010000); ++ ++ /* set pmic_sleep iomux */ ++ mmio_write_32(PMU0IOC_BASE + 0, ++ BITS_WITH_WMASK(1, 0xf, 8) | ++ BITS_WITH_WMASK(1, 0xfu, 12)); ++ ++ /* set tsadc_shut_m0 pin iomux to gpio */ ++ mmio_write_32(PMU0IOC_BASE + 0, ++ BITS_WITH_WMASK(0, 0xf, 4)); ++ ++ /* set spi2_cs0/1 pin iomux to gpio */ ++ mmio_write_32(PMU0IOC_BASE + 8, ++ BITS_WITH_WMASK(0, 0xff, 0)); ++ ++ /* sleep 1~2 src select */ ++ mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), ++ BITS_WITH_WMASK(0x8, 0xf, 0) | ++ BITS_WITH_WMASK(0x8, 0xf, 4) | ++ BITS_WITH_WMASK(0x0, 0x3, 8)); ++ ++ pmu1_wkup_int_con = BIT(WAKEUP_GPIO0_INT_EN) | ++ BIT(WAKEUP_CPU0_INT_EN); ++ ++ pmu1_pwr_con = BIT(powermode_en); ++ ++ pmu1_cru_pwr_con = ++ BIT(alive_osc_mode_en) | ++ BIT(power_off_en) | ++ BIT(pd_clk_src_gate_en); ++ ++ pmu1_ddr_pwr_con = 0; ++ ++ pmu2_dsu_pwr_con = ++ BIT(DSU_PWRDN_EN) | ++ BIT(DSU_PWROFF_EN); ++ ++ pmu2_core_pwr_con = BIT(CORE_PWRDN_EN); ++ ++ pmu2_clst_idle_con = ++ BIT(IDLE_REQ_BIGCORE0_EN) | ++ BIT(IDLE_REQ_BIGCORE1_EN) | ++ BIT(IDLE_REQ_DSU_EN) | ++ BIT(IDLE_REQ_LITDSU_EN) | ++ BIT(IDLE_REQ_ADB400_CORE_QCH_EN); ++ ++ pmu1_pll_pd_con[0] = ++ BIT(B0PLL_PD_EN) | ++ BIT(B1PLL_PD_EN) | ++ BIT(LPLL_PD_EN) | ++ BIT(V0PLL_PD_EN) | ++ BIT(AUPLL_PD_EN) | ++ BIT(GPLL_PD_EN) | ++ BIT(CPLL_PD_EN) | ++ BIT(NPLL_PD_EN); ++ ++ pmu1_pll_pd_con[1] = ++ BIT(PPLL_PD_EN) | ++ BIT(SPLL_PD_EN); ++ ++ pmu2_bus_idle_con[0] = 0; ++ ++ pmu2_bus_idle_con[1] = ++ BIT(BUS_ID_SECURE - 16) | ++ BIT(BUS_ID_SECURE_CENTER_CHANNEL - 16) | ++ BIT(BUS_ID_CENTER_CHANNEL - 16); ++ ++ pmu2_bus_idle_con[2] = ++ BIT(BUS_ID_MSCH - 32) | ++ BIT(BUS_ID_BUS - 32) | ++ BIT(BUS_ID_TOP - 32); ++ ++ pmu2_pwr_gate_con[0] = 0; ++ pmu2_pwr_gate_con[1] = BIT(PD_SECURE - 16); ++ pmu2_pwr_gate_con[2] = 0; ++ ++ pmu2_qch_pwr_con = 0; ++ ++ pmu2_vol_gate_con[0] = 0x7; ++ pmu2_vol_gate_con[2] = 0; ++ ++ mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(0), 0x00030000); ++ mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(1), 0x00030000); ++ mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), ++ WITH_16BITS_WMSK(pmu2_core_pwr_con)); ++ mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), ++ WITH_16BITS_WMSK(pmu2_core_pwr_con)); ++ mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, ++ WITH_16BITS_WMSK(pmu2_clst_idle_con)); ++ mmio_write_32(PMU_BASE + PMU2_DSU_AUTO_PWR_CON, 0x00030000); ++ mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, ++ WITH_16BITS_WMSK(pmu2_dsu_pwr_con)); ++ ++ mmio_write_32(PMU_BASE + PMU1_OSC_STABLE_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU1_STABLE_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU1_WAKEUP_RST_CLR_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU1_PLL_LOCK_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU1_PWM_SWITCH_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU2_CORE0_STABLE_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU2_CORE0_PWRUP_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU2_CORE0_PWRDN_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU2_CORE1_STABLE_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU2_CORE1_PWRUP_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU2_CORE1_PWRDN_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU2_DSU_STABLE_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU2_DSU_PWRUP_CNT_THRESH, 24000); ++ mmio_write_32(PMU_BASE + PMU2_DSU_PWRDN_CNT_THRESH, 24000); ++ ++ /* Config pmu power mode and pmu wakeup source */ ++ mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, ++ BITS_WITH_WMASK(1, 0x1, 0)); ++ ++ /* pmu1_pwr_con */ ++ mmio_write_32(PMU_BASE + PMU1_PWR_CON, ++ WITH_16BITS_WMSK(pmu1_pwr_con)); ++ ++ /* cru_pwr_con */ ++ mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON, ++ WITH_16BITS_WMSK(pmu1_cru_pwr_con)); ++ ++ /* wakeup source */ ++ mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, pmu1_wkup_int_con); ++ ++ /* ddr pwr con */ ++ for (i = 0; i < DDR_CHN_CNT; i++) { ++ mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(i), ++ WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); ++ pmu2_bus_idle_con[1] |= ++ BIT(BUS_ID_MSCH0 - 16 + i); ++ } ++ ++ /* pll_pd */ ++ mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), ++ WITH_16BITS_WMSK(pmu1_pll_pd_con[0])); ++ mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(1), ++ WITH_16BITS_WMSK(pmu1_pll_pd_con[1])); ++ ++ /* bypass cpu1~7*/ ++ mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0x00ff00fe); ++ ++ /* bus idle */ ++ mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), ++ WITH_16BITS_WMSK(pmu2_bus_idle_con[0])); ++ mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), ++ WITH_16BITS_WMSK(pmu2_bus_idle_con[1])); ++ mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), ++ WITH_16BITS_WMSK(pmu2_bus_idle_con[2])); ++ mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), ++ 0xf000f000); ++ /* power gate */ ++ mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), ++ WITH_16BITS_WMSK(pmu2_pwr_gate_con[0])); ++ mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), ++ WITH_16BITS_WMSK(pmu2_pwr_gate_con[1])); ++ mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(2), ++ WITH_16BITS_WMSK(pmu2_pwr_gate_con[2])); ++ /* vol gate */ ++ mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), ++ BITS_WITH_WMASK(pmu2_vol_gate_con[0], 0x7, 0)); ++ mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), 0); ++ mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), ++ BITS_WITH_WMASK(pmu2_vol_gate_con[2], 0x3, 0)); ++ /* qch */ ++ mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_CON, ++ BITS_WITH_WMASK(pmu2_qch_pwr_con, 0x7f, 0)); ++ ++ mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), ++ 0x000f000f); ++} ++ ++static void pmu_sleep_restore(void) ++{ ++ mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(7), ++ WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con7)); ++ mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(8), ++ WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con8)); ++ mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(9), ++ WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con9)); ++ mmio_write_32(PMU1SGRF_BASE + PMU1_SGRF_SOC_CON(14), ++ WITH_16BITS_WMSK(ddr_data.pmu1sgrf_soc_con14)); ++ ++ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1), ++ WITH_16BITS_WMSK(ddr_data.pmu0sgrf_soc_con1)); ++ mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(1), ++ WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con1)); ++ ++ mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), 0xffff0000); ++ mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), 0xffff0000); ++ mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 0xffff0000); ++ mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, 0xffff0000); ++ mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0xffff0000); ++ ++ /* Must clear PMU1_WAKEUP_INT_CON because the wakeup source ++ * in PMU1_WAKEUP_INT_CON will wakeup cpus in cpu_auto_pd state. ++ */ ++ mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, 0); ++ mmio_write_32(PMU_BASE + PMU1_PWR_CON, 0xffff0000); ++ mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 0x00010000); ++ mmio_write_32(PMU_BASE + PMU0_WAKEUP_INT_CON, 0x00010000); ++ mmio_write_32(PMU_BASE + PMU0_PWR_CON, 0xffff0000); ++ ++ mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), ++ WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[0])); ++ mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), ++ WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[1])); ++ mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), ++ WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[2])); ++ ++ mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), ++ WITH_16BITS_WMSK(ddr_data.pmu2_submem_gate_sft_con0)); ++ ++ mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), ++ WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con3)); ++ mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(2), ++ WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con2)); ++ ++ mmio_write_32(PMU0IOC_BASE + 0x4, ++ WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h)); ++ mmio_write_32(PMU0IOC_BASE + 0, ++ WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l)); ++} ++ ++static void soc_sleep_config(void) ++{ ++ ddr_data.gpio0b_iomux_l = mmio_read_32(PMU0IOC_BASE + 0x8); ++ ++ pmu_sleep_config(); ++ ddr_sleep_config(); ++} ++ ++static void soc_sleep_restore(void) ++{ ++ ddr_sleep_config_restore(); ++ pmu_sleep_restore(); ++ ++ mmio_write_32(PMU0IOC_BASE + 0x8, WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l)); ++} ++ ++static void pm_pll_suspend(void) ++{ ++ ddr_data.cru_mode_con = mmio_read_32(CRU_BASE + 0x280); ++ ddr_data.busscru_mode_con = mmio_read_32(BUSSCRU_BASE + 0x280); ++ ddr_data.pmu2_bisr_con0 = mmio_read_32(PMU_BASE + PMU2_BISR_CON(0)); ++ ddr_data.cpll_con0 = mmio_read_32(CRU_BASE + CRU_PLLS_CON(2, 0)); ++ ddr_data.pmu1cru_clksel_con1 = mmio_read_32(PMU1CRU_BASE + CRU_CLKSEL_CON(1)); ++ ++ /* disable bisr_init */ ++ mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), BITS_WITH_WMASK(0, 0x1, 0)); ++ /* cpll bypass */ ++ mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), BITS_WITH_WMASK(1u, 1u, 15)); ++} ++ ++static void pm_pll_restore(void) ++{ ++ pm_pll_wait_lock(CRU_BASE + CRU_PLLS_CON(2, 0)); ++ ++ mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); ++ mmio_write_32(BUSSCRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.busscru_mode_con)); ++ mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), WITH_16BITS_WMSK(ddr_data.cpll_con0)); ++ dsb(); ++ isb(); ++ mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), WITH_16BITS_WMSK(ddr_data.pmu2_bisr_con0)); ++} ++ ++int rockchip_soc_sys_pwr_dm_suspend(void) ++{ ++ clk_gate_con_save(); ++ clk_gate_con_disable(); ++ ++ psram_sleep_cfg->pm_flag &= ~PM_WARM_BOOT_BIT; ++ ++ pmu_power_domains_suspend(); ++ soc_sleep_config(); ++ dsu_core_save(); ++ pm_pll_suspend(); ++ ++ return 0; ++} ++ ++int rockchip_soc_sys_pwr_dm_resume(void) ++{ ++ pm_pll_restore(); ++ dsu_core_restore(); ++ soc_sleep_restore(); ++ pmu_power_domains_resume(); ++ plat_rockchip_gic_cpuif_enable(); ++ ++ psram_sleep_cfg->pm_flag |= PM_WARM_BOOT_BIT; ++ ++ clk_gate_con_restore(); ++ ++ return 0; ++} ++ ++void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(const ++ psci_power_state_t *target_state) ++{ ++ psci_power_down_wfi(); ++} ++ ++void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void) ++{ ++ cpus_pd_req_enter_wfi(); ++ psci_power_down_wfi(); ++} ++ ++void __dead2 rockchip_soc_soft_reset(void) ++{ ++ /* pll slow mode */ ++ mmio_write_32(CRU_BASE + 0x280, 0x03ff0000); ++ mmio_write_32(BIGCORE0CRU_BASE + 0x280, 0x00030000); ++ mmio_write_32(BIGCORE0CRU_BASE + 0x300, 0x60000000); ++ mmio_write_32(BIGCORE0CRU_BASE + 0x304, 0x00600000); ++ mmio_write_32(BIGCORE1CRU_BASE + 0x280, 0x00030000); ++ mmio_write_32(BIGCORE1CRU_BASE + 0x300, 0x60000000); ++ mmio_write_32(BIGCORE1CRU_BASE + 0x304, 0x00600000); ++ mmio_write_32(DSUCRU_BASE + 0x280, 0x00030000); ++ mmio_write_32(DSUCRU_BASE + 0x318, 0x30600000); ++ mmio_write_32(DSUCRU_BASE + 0x31c, 0x30600000); ++ mmio_write_32(DSUCRU_BASE + 0x304, 0x00010000); ++ mmio_write_32(BUSSCRU_BASE + 0x280, 0x0003000); ++ dsb(); ++ isb(); ++ ++ mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); ++ ++ /* ++ * Maybe the HW needs some times to reset the system, ++ * so we do not hope the core to execute valid codes. ++ */ ++ psci_power_down_wfi(); ++} ++ ++void __dead2 rockchip_soc_system_off(void) ++{ ++ /* set pmic_sleep pin(gpio0_a2) to gpio mode */ ++ mmio_write_32(PMU0IOC_BASE + 0, BITS_WITH_WMASK(0, 0xf, 8)); ++ ++ /* config output */ ++ mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DDR_L, ++ BITS_WITH_WMASK(1, 0x1, 2)); ++ ++ /* config output high level */ ++ mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DR_L, ++ BITS_WITH_WMASK(1, 0x1, 2)); ++ dsb(); ++ ++ /* ++ * Maybe the HW needs some times to reset the system, ++ * so we do not hope the core to execute valid codes. ++ */ ++ psci_power_down_wfi(); ++} ++ ++static void rockchip_pmu_pd_init(void) ++{ ++ mmio_write_32(PMU_BASE + PMU2_BISR_CON(1), 0xffffffff); ++ mmio_write_32(PMU_BASE + PMU2_BISR_CON(2), 0xffffffff); ++ mmio_write_32(PMU_BASE + PMU2_BISR_CON(3), 0xffffffff); ++ ++ pmu_set_power_domain(PD_PHP, pmu_pd_on); ++ pmu_set_power_domain(PD_PCIE, pmu_pd_on); ++ pmu_set_power_domain(PD_GMAC, pmu_pd_on); ++ pmu_set_power_domain(PD_SECURE, pmu_pd_on); ++ pmu_set_power_domain(PD_VOP, pmu_pd_on); ++ pmu_set_power_domain(PD_VO0, pmu_pd_on); ++ pmu_set_power_domain(PD_VO1, pmu_pd_on); ++} ++ ++#define PLL_LOCKED_TIMEOUT 600000U ++ ++void pm_pll_wait_lock(uint32_t pll_base) ++{ ++ int delay = PLL_LOCKED_TIMEOUT; ++ ++ if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0) ++ return; ++ ++ while (delay-- >= 0) { ++ if (mmio_read_32(pll_base + CRU_PLL_CON(6)) & ++ CRU_PLLCON6_LOCK_STATUS) ++ break; ++ udelay(1); ++ } ++ ++ if (delay <= 0) ++ ERROR("Can't wait pll(0x%x) lock\n", pll_base); ++} ++ ++void rockchip_plat_mmu_el3(void) ++{ ++ /* Nothing todo */ ++} ++ ++void plat_rockchip_pmu_init(void) ++{ ++ int cpu; ++ ++ for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) ++ cpuson_flags[cpu] = 0; ++ ++ psram_sleep_cfg->sp = PSRAM_SP_TOP; ++ psram_sleep_cfg->ddr_func = (uint64_t)ddr_resume; ++ psram_sleep_cfg->ddr_data = 0; ++ psram_sleep_cfg->ddr_flag = 0; ++ psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; ++ psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT; ++ ++ nonboot_cpus_off(); ++ ++ /* ++ * When perform idle operation, corresponding clock can be ++ * opened or gated automatically. ++ */ ++ mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(0), 0xffffffff); ++ mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(1), 0xffffffff); ++ mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(2), 0x00070007); ++ ++ rockchip_pmu_pd_init(); ++ ++ /* grf_con_pmic_sleep_sel ++ * pmic sleep function selection ++ * 1'b0: From reset pulse generator, can reset external PMIC ++ * 1'b1: From pmu block, only support sleep function for external PMIC ++ */ ++ mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 0x03ff0000); ++ ++ /* pmusram remap to 0xffff0000 */ ++ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001); ++ ++ pm_reg_rgns_init(); ++} +diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.h b/plat/rockchip/rk3588/drivers/pmu/pmu.h +new file mode 100644 +index 0000000..7d8288c +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/pmu/pmu.h +@@ -0,0 +1,589 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef __PMU_H__ ++#define __PMU_H__ ++ ++#include ++ ++#define PMU0_PWR_CON 0x0000 ++#define PMU0_WAKEUP_INT_CON 0x0008 ++#define PMU0_WAKEUP_INT_ST 0x000c ++#define PMU0_PMIC_STABLE_CNT_THRES 0x0010 ++#define PMU0_WAKEUP_RST_CLR_CNT_THRES 0x0014 ++#define PMU0_OSC_STABLE_CNT_THRES 0x0018 ++#define PMU0_PWR_CHAIN_STABLE_CON 0x001c ++#define PMU0_DDR_RET_CON(i) (0x0020 + (i) * 4) ++#define PMU0_INFO_TX_CON 0x0030 ++ ++#define PMU1_VERSION_ID 0x4000 ++#define PMU1_PWR_CON 0x4004 ++#define PMU1_PWR_FSM 0x4008 ++#define PMU1_INT_MASK_CON 0x400c ++#define PMU1_WAKEUP_INT_CON 0x4010 ++#define PMU1_WAKEUP_INT_ST 0x4014 ++#define PMU1_WAKEUP_EDGE_CON 0x4018 ++#define PMU1_WAKEUP_EDGE_ST 0x401c ++#define PMU1_DDR_PWR_CON(i) (0x4020 + (i) * 4) ++#define PMU1_DDR_PWR_SFTCON(i) (0x4030 + (i) * 4) ++#define PMU1_DDR_PWR_FSM 0x4040 ++#define PMU1_DDR_PWR_ST 0x4044 ++#define PMU1_CRU_PWR_CON 0x4050 ++#define PMU1_CRU_PWR_SFTCON 0x4054 ++#define PMU1_CRU_PWR_FSM 0x4058 ++#define PMU1_PLLPD_CON(i) (0x4060 + (i) * 4) ++#define PMU1_PLLPD_SFTCON(i) (0x4068 + (i) * 4) ++#define PMU1_STABLE_CNT_THRESH 0x4080 ++#define PMU1_OSC_STABLE_CNT_THRESH 0x4084 ++#define PMU1_WAKEUP_RST_CLR_CNT_THRESH 0x4088 ++#define PMU1_PLL_LOCK_CNT_THRESH 0x408c ++#define PMU1_WAKEUP_TIMEOUT_THRESH 0x4094 ++#define PMU1_PWM_SWITCH_CNT_THRESH 0x4098 ++#define PMU1_SYS_REG(i) (0x4100 + (i) * 4) ++ ++#define PMU2_PWR_CON1 0x8000 ++#define PMU2_DSU_PWR_CON 0x8004 ++#define PMU2_DSU_PWR_SFTCON 0x8008 ++#define PMU2_DSU_AUTO_PWR_CON 0x800c ++#define PMU2_CPU_AUTO_PWR_CON(i) (0x8010 + (i) * 4) ++#define PMU2_CPU_PWR_SFTCON(i) (0x8030 + (i) * 4) ++#define PMU2_CORE_PWR_CON(i) (0x8050 + (i) * 4) ++#define PMU2_CORE_PWR_SFTCON(i) (0x8058 + (i) * 4) ++#define PMU2_CORE_AUTO_PWR_CON(i) (0x8060 + (i) * 4) ++#define PMU2_CLUSTER_NOC_AUTO_CON 0x8068 ++#define PMU2_CLUSTER_DBG_PWR_CON 0x806c ++#define PMU2_CLUSTER_IDLE_CON 0x8070 ++#define PMU2_CLUSTER_IDLE_SFTCON 0x8074 ++#define PMU2_CLUSTER_IDLE_ACK 0x8078 ++#define PMU2_CLUSTER_IDLE_ST 0x807c ++#define PMU2_CLUSTER_ST 0x8080 ++#define PMU2_SCU_PWR_FSM_STATUS(i) (0x8084 + (i) * 4) ++#define PMU2_CORE_PCHANNEL_STATUS(i) (0x808c + (i) * 4) ++#define PMU2_CPU_PWR_CHAIN_STABLE_CON 0x8098 ++#define PMU2_CLUSTER_MEMPWR_GATE_SFTCON 0x809c ++#define PMU2_DSU_STABLE_CNT_THRESH 0x80b0 ++#define PMU2_DSU_PWRUP_CNT_THRESH 0x80b4 ++#define PMU2_DSU_PWRDN_CNT_THRESH 0x80b8 ++#define PMU2_CORE0_STABLE_CNT_THRESH 0x80bc ++#define PMU2_CORE0_PWRUP_CNT_THRESH 0x80c0 ++#define PMU2_CORE0_PWRDN_CNT_THRESH 0x80c4 ++#define PMU2_CORE1_STABLE_CNT_THRESH 0x80c8 ++#define PMU2_CORE1_PWRUP_CNT_THRESH 0x80cc ++#define PMU2_CORE1_PWRDN_CNT_THRESH 0x80d0 ++#define PMU2_DBG_RST_CNT_THRESH(i) (0x80d4 + (i) * 4) ++#define PMU2_BUS_IDLE_CON(i) (0x8100 + (i) * 4) ++#define PMU2_BUS_IDLE_SFTCON(i) (0x810c + (i) * 4) ++#define PMU2_BUS_IDLE_ACK(i) (0x8118 + (i) * 4) ++#define PMU2_BUS_IDLE_ST(i) (0x8120 + (i) * 4) ++#define PMU2_BIU_AUTO_CON(i) (0x8128 + (i) * 4) ++#define PMU2_PWR_GATE_CON(i) (0x8140 + (i) * 4) ++#define PMU2_PWR_GATE_SFTCON(i) (0x814c + (i) * 4) ++#define PMU2_VOL_GATE_CON(i) (0x8158 + (i) * 4) ++#define PMU2_PWR_UP_CHAIN_STABLE_CON(i) (0x8164 + (i) * 4) ++#define PMU2_PWR_DWN_CHAIN_STABLE_CON(i)(0x8170 + (i) * 4) ++#define PMU2_PWR_STABLE_CHAIN_CNT_THRES 0x817c ++#define PMU2_PWR_GATE_ST(i) (0x8180 + (i) * 4) ++#define PMU2_PWR_GATE_FSM 0x8188 ++#define PMU2_VOL_GATE_FAST_CON 0x818c ++#define PMU2_GPU_PWRUP_CNT 0x8190 ++#define PMU2_GPU_PWRDN_CNT 0x8194 ++#define PMU2_NPU_PWRUP_CNT 0x8198 ++#define PMU2_NPU_PWRDN_CNT 0x819c ++#define PMU2_MEMPWR_GATE_SFTCON(i) (0x81a0 + (i) * 4) ++#define PMU2_MEMPWR_MD_GATE_SFTCON(i) (0x81b0 + (i) * 4) ++#define PMU2_MEMPWR_MD_GATE_STATUS 0x81bc ++#define PMU2_SUBMEM_PWR_ACK_BYPASS(i) (0x81c0 + (i) * 4) ++#define PMU2_QCHANNEL_PWR_CON 0x81d0 ++#define PMU2_QCHANNEL_PWR_SFTCON 0x81d4 ++#define PMU2_QCHANNEL_STATUS 0x81d8 ++#define PMU2_DEBUG_INFO_SEL 0x81e0 ++#define PMU2_VOP_SUBPD_STATE 0x81e4 ++#define PMU2_PWR_CHAIN0_ST(i) (0x81e8 + (i) * 4) ++#define PMU2_PWR_CHAIN1_ST(i) (0x81f0 + (i) * 4) ++#define PMU2_PWR_MEM_ST(i) (0x81f8 + (i) * 4) ++#define PMU2_BISR_CON(i) (0x8200 + (i) * 4) ++#define PMU2_BISR_STATUS(i) (0x8280 + (i) * 4) ++ ++#define PMU2_QCH_PWR_MSK 0x7f ++ ++#define PD_CTR_LOOP 500 ++#define PD_CHECK_LOOP 500 ++#define WFEI_CHECK_LOOP 500 ++#define BUS_IDLE_LOOP 1000 ++#define QCH_PWR_LOOP 5000 ++ ++/* PMU1SCRU */ ++#define PMU1SCRU_GATE_CON(i) (0x800 + (i) * 4) ++ ++/* PMU_GRF */ ++#define PMU0_GRF_SOC_CON(i) ((i) * 4) ++#define PMU0_GRF_OS_REGS(i) (0x80 + ((i) - 8) * 4) ++#define PMU1_GRF_SOC_CON(i) ((i) * 4) ++#define PMU0_GRF_IO_RET_CON(i) (0x20 + (i) * 4) ++ ++/* PMU_SGRF */ ++#define PMU0_SGRF_SOC_CON(i) ((i) * 4) ++#define PMU1_SGRF_SOC_CON(i) ((i) * 4) ++ ++/* sys grf */ ++#define GRF_CPU_STATUS0 0x0420 ++ ++#define CORES_PM_DISABLE 0x0 ++#define PD_CHECK_LOOP 500 ++#define WFEI_CHECK_LOOP 500 ++ ++/* The ways of cores power domain contorlling */ ++enum cores_pm_ctr_mode { ++ core_pwr_pd = 0, ++ core_pwr_wfi = 1, ++ core_pwr_wfi_int = 2 ++}; ++ ++/* PMU0_PWR_CON */ ++enum pmu0_pwr_con { ++ pmu0_powermode_en = 0, ++ pmu0_pmu1_pwr_bypass = 1, ++ pmu0_pmu1_bus_bypass = 2, ++ pmu0_wkup_bypass = 3, ++ pmu0_pmic_bypass = 4, ++ pmu0_reset_bypass = 5, ++ pmu0_freq_sw_bypass = 6, ++ pmu0_osc_dis_bypass = 7, ++ pmu0_pmu1_pwr_gt_en = 8, ++ pmu0_pmu1_pwr_gt_sft_en = 9, ++ pmu0_pmu1_mem_gt_sft_en = 10, ++ pmu0_pmu1_bus_idle_en = 11, ++ pmu0_pmu1_bus_idle_sft_en = 12, ++ pmu0_pmu1_biu_auto_en = 13, ++ pmu0_pwr_off_io_en = 14, ++}; ++ ++/* PMU1_PWR_CON */ ++enum pmu1_pwr_con { ++ powermode_en = 0, ++ dsu_bypass = 1, ++ bus_bypass = 4, ++ ddr_bypass = 5, ++ pwrdn_bypass = 6, ++ cru_bypass = 7, ++ qch_bypass = 8, ++ core_bypass = 9, ++ cpu_sleep_wfi_dis = 12, ++}; ++ ++/* PMU1_DDR_PWR_CON */ ++enum pmu1_ddr_pwr_con { ++ ddr_sref_en = 0, ++ ddr_sref_a_en = 1, ++ ddrio_ret_en = 2, ++ ddrio_ret_exit_en = 5, ++ ddrio_rstiov_en = 6, ++ ddrio_rstiov_exit_en = 7, ++ ddr_gating_a_en = 8, ++ ddr_gating_c_en = 9, ++ ddr_gating_p_en = 10, ++}; ++ ++/* PMU_CRU_PWR_CON */ ++enum pmu1_cru_pwr_con { ++ alive_32k_en = 0, ++ osc_dis_en = 1, ++ wakeup_rst_en = 2, ++ input_clamp_en = 3, ++ alive_osc_mode_en = 4, ++ power_off_en = 5, ++ pwm_switch_en = 6, ++ pwm_gpio_ioe_en = 7, ++ pwm_switch_io = 8, ++ pd_clk_src_gate_en = 9, ++}; ++ ++/* PMU_PLLPD_CON */ ++enum pmu1_pllpd_con { ++ B0PLL_PD_EN, ++ B1PLL_PD_EN, ++ LPLL_PD_EN, ++ D0APLL_PD_EN, ++ D0BPLL_PD_EN, ++ D1APLL_PD_EN, ++ D1BPLL_PD_EN, ++ D2APLL_PD_EN, ++ D2BPLL_PD_EN, ++ D3APLL_PD_EN, ++ D3BPLL_PD_EN, ++ V0PLL_PD_EN, ++ AUPLL_PD_EN, ++ GPLL_PD_EN, ++ CPLL_PD_EN, ++ NPLL_PD_EN, ++ PPLL_PD_EN = 0, ++ SPLL_PD_EN = 1, ++}; ++ ++enum pmu1_wakeup_int { ++ WAKEUP_CPU0_INT_EN, ++ WAKEUP_CPU1_INT_EN, ++ WAKEUP_CPU2_INT_EN, ++ WAKEUP_CPU3_INT_EN, ++ WAKEUP_CPU4_INT_EN, ++ WAKEUP_CPU5_INT_EN, ++ WAKEUP_CPU6_INT_EN, ++ WAKEUP_CPU7_INT_EN, ++ WAKEUP_GPIO0_INT_EN, ++ WAKEUP_SDMMC_EN, ++ WAKEUP_SDIO_EN, ++ WAKEUP_USBDEV_EN, ++ WAKEUP_UART0_EN, ++ WAKEUP_VAD_EN, ++ WAKEUP_TIMER_EN, ++ WAKEUP_SOC_INT_EN, ++ WAKEUP_TIMEROUT_EN, ++ WAKEUP_PMUMCU_CEC_EN = 20, ++}; ++ ++enum pmu2_dsu_auto_pwr_con { ++ dsu_pm_en = 0, ++ dsu_pm_int_wakeup_en = 1, ++ dsu_pm_sft_wakeup_en = 3, ++}; ++ ++enum pmu2_cpu_auto_pwr_con { ++ cpu_pm_en = 0, ++ cpu_pm_int_wakeup_en = 1, ++ cpu_pm_sft_wakeup_en = 3, ++}; ++ ++enum pmu2_core_auto_pwr_con { ++ core_pm_en = 0, ++ core_pm_int_wakeup_en = 1, ++ core_pm_int_wakeup_glb_msk = 2, ++ core_pm_sft_wakeup_en = 3, ++}; ++ ++enum pmu2_dsu_power_con { ++ DSU_PWRDN_EN, ++ DSU_PWROFF_EN, ++ BIT_FULL_EN, ++ DSU_RET_EN, ++ CLUSTER_CLK_SRC_GT_EN, ++}; ++ ++enum pmu2_core_power_con { ++ CORE_PWRDN_EN, ++ CORE_PWROFF_EN, ++ CORE_CPU_PWRDN_EN, ++ CORE_PWR_CNT_EN, ++}; ++ ++enum pmu2_cluster_idle_con { ++ IDLE_REQ_BIGCORE0_EN = 0, ++ IDLE_REQ_BIGCORE1_EN = 2, ++ IDLE_REQ_DSU_EN = 4, ++ IDLE_REQ_LITDSU_EN = 5, ++ IDLE_REQ_ADB400_CORE_QCH_EN = 6, ++}; ++ ++enum qos_id { ++ QOS_ISP0_MWO = 0, ++ QOS_ISP0_MRO = 1, ++ QOS_ISP1_MWO = 2, ++ QOS_ISP1_MRO = 3, ++ QOS_VICAP_M0 = 4, ++ QOS_VICAP_M1 = 5, ++ QOS_FISHEYE0 = 6, ++ QOS_FISHEYE1 = 7, ++ QOS_VOP_M0 = 8, ++ QOS_VOP_M1 = 9, ++ QOS_RKVDEC0 = 10, ++ QOS_RKVDEC1 = 11, ++ QOS_AV1 = 12, ++ QOS_RKVENC0_M0RO = 13, ++ QOS_RKVENC0_M1RO = 14, ++ QOS_RKVENC0_M2WO = 15, ++ QOS_RKVENC1_M0RO = 16, ++ QOS_RKVENC1_M1RO = 17, ++ QOS_RKVENC1_M2WO = 18, ++ QOS_DSU_M0 = 19, ++ QOS_DSU_M1 = 20, ++ QOS_DSU_MP = 21, ++ QOS_DEBUG = 22, ++ QOS_GPU_M0 = 23, ++ QOS_GPU_M1 = 24, ++ QOS_GPU_M2 = 25, ++ QOS_GPU_M3 = 26, ++ QOS_NPU1 = 27, ++ QOS_NPU0_MRO = 28, ++ QOS_NPU2 = 29, ++ QOS_NPU0_MWR = 30, ++ QOS_MCU_NPU = 31, ++ QOS_JPEG_DEC = 32, ++ QOS_JPEG_ENC0 = 33, ++ QOS_JPEG_ENC1 = 34, ++ QOS_JPEG_ENC2 = 35, ++ QOS_JPEG_ENC3 = 36, ++ QOS_RGA2_MRO = 37, ++ QOS_RGA2_MWO = 38, ++ QOS_RGA3_0 = 39, ++ QOS_RGA3_1 = 40, ++ QOS_VDPU = 41, ++ QOS_IEP = 42, ++ QOS_HDCP0 = 43, ++ QOS_HDCP1 = 44, ++ QOS_HDMIRX = 45, ++ QOS_GIC600_M0 = 46, ++ QOS_GIC600_M1 = 47, ++ QOS_MMU600PCIE_TCU = 48, ++ QOS_MMU600PHP_TBU = 49, ++ QOS_MMU600PHP_TCU = 50, ++ QOS_USB3_0 = 51, ++ QOS_USB3_1 = 52, ++ QOS_USBHOST_0 = 53, ++ QOS_USBHOST_1 = 54, ++ QOS_EMMC = 55, ++ QOS_FSPI = 56, ++ QOS_SDIO = 57, ++ QOS_DECOM = 58, ++ QOS_DMAC0 = 59, ++ QOS_DMAC1 = 60, ++ QOS_DMAC2 = 61, ++ QOS_GIC600M = 62, ++ QOS_DMA2DDR = 63, ++ QOS_MCU_DDR = 64, ++ QOS_VAD = 65, ++ QOS_MCU_PMU = 66, ++ QOS_CRYPTOS = 67, ++ QOS_CRYPTONS = 68, ++ QOS_DCF = 69, ++ QOS_SDMMC = 70, ++}; ++ ++enum pmu2_pdid { ++ PD_GPU = 0, ++ PD_NPU = 1, ++ PD_VCODEC = 2, ++ PD_NPUTOP = 3, ++ PD_NPU1 = 4, ++ PD_NPU2 = 5, ++ PD_VENC0 = 6, ++ PD_VENC1 = 7, ++ PD_RKVDEC0 = 8, ++ PD_RKVDEC1 = 9, ++ PD_VDPU = 10, ++ PD_RGA30 = 11, ++ PD_AV1 = 12, ++ PD_VI = 13, ++ PD_FEC = 14, ++ PD_ISP1 = 15, ++ PD_RGA31 = 16, ++ PD_VOP = 17, ++ PD_VO0 = 18, ++ PD_VO1 = 19, ++ PD_AUDIO = 20, ++ PD_PHP = 21, ++ PD_GMAC = 22, ++ PD_PCIE = 23, ++ PD_NVM = 24, ++ PD_NVM0 = 25, ++ PD_SDIO = 26, ++ PD_USB = 27, ++ PD_SECURE = 28, ++ PD_SDMMC = 29, ++ PD_CRYPTO = 30, ++ PD_CENTER = 31, ++ PD_DDR01 = 32, ++ PD_DDR23 = 33, ++}; ++ ++enum pmu2_pd_repair_id { ++ PD_RPR_PMU = 0, ++ PD_RPR_GPU = 1, ++ PD_RPR_NPUTOP = 2, ++ PD_RPR_NPU1 = 3, ++ PD_RPR_NPU2 = 4, ++ PD_RPR_VENC0 = 5, ++ PD_RPR_VENC1 = 6, ++ PD_RPR_RKVDEC0 = 7, ++ PD_RPR_RKVDEC1 = 8, ++ PD_RPR_VDPU = 9, ++ PD_RPR_RGA30 = 10, ++ PD_RPR_AV1 = 11, ++ PD_RPR_VI = 12, ++ PD_RPR_FEC = 13, ++ PD_RPR_ISP1 = 14, ++ PD_RPR_RGA31 = 15, ++ PD_RPR_VOP = 16, ++ PD_RPR_VO0 = 17, ++ PD_RPR_VO1 = 18, ++ PD_RPR_AUDIO = 19, ++ PD_RPR_PHP = 20, ++ PD_RPR_GMAC = 21, ++ PD_RPR_PCIE = 22, ++ PD_RPR_NVM0 = 23, ++ PD_RPR_SDIO = 24, ++ PD_RPR_USB = 25, ++ PD_RPR_SDMMC = 26, ++ PD_RPR_CRYPTO = 27, ++ PD_RPR_CENTER = 28, ++ PD_RPR_DDR01 = 29, ++ PD_RPR_DDR23 = 30, ++ PD_RPR_BUS = 31, ++}; ++ ++enum pmu2_bus_id { ++ BUS_ID_GPU = 0, ++ BUS_ID_NPUTOP = 1, ++ BUS_ID_NPU1 = 2, ++ BUS_ID_NPU2 = 3, ++ BUS_ID_RKVENC0 = 4, ++ BUS_ID_RKVENC1 = 5, ++ BUS_ID_RKVDEC0 = 6, ++ BUS_ID_RKVDEC1 = 7, ++ BUS_ID_VDPU = 8, ++ BUS_ID_AV1 = 9, ++ BUS_ID_VI = 10, ++ BUS_ID_ISP = 11, ++ BUS_ID_RGA31 = 12, ++ BUS_ID_VOP = 13, ++ BUS_ID_VOP_CHANNEL = 14, ++ BUS_ID_VO0 = 15, ++ BUS_ID_VO1 = 16, ++ BUS_ID_AUDIO = 17, ++ BUS_ID_NVM = 18, ++ BUS_ID_SDIO = 19, ++ BUS_ID_USB = 20, ++ BUS_ID_PHP = 21, ++ BUS_ID_VO1USBTOP = 22, ++ BUS_ID_SECURE = 23, ++ BUS_ID_SECURE_CENTER_CHANNEL = 24, ++ BUS_ID_SECURE_VO1USB_CHANNEL = 25, ++ BUS_ID_CENTER = 26, ++ BUS_ID_CENTER_CHANNEL = 27, ++ BUS_ID_MSCH0 = 28, ++ BUS_ID_MSCH1 = 29, ++ BUS_ID_MSCH2 = 30, ++ BUS_ID_MSCH3 = 31, ++ BUS_ID_MSCH = 32, ++ BUS_ID_BUS = 33, ++ BUS_ID_TOP = 34, ++}; ++ ++enum pmu2_mem_st { ++ PD_NPU_TOP_MEM_ST = 11, ++ PD_NPU1_MEM_ST = 12, ++ PD_NPU2_MEM_ST = 13, ++ PD_VENC0_MEM_ST = 14, ++ PD_VENC1_MEM_ST = 15, ++ PD_RKVDEC0_MEM_ST = 16, ++ PD_RKVDEC1_MEM_ST = 17, ++ PD_RGA30_MEM_ST = 19, ++ PD_AV1_MEM_ST = 20, ++ PD_VI_MEM_ST = 21, ++ PD_FEC_MEM_ST = 22, ++ PD_ISP1_MEM_ST = 23, ++ PD_RGA31_MEM_ST = 24, ++ PD_VOP_MEM_ST = 25, ++ PD_VO0_MEM_ST = 26, ++ PD_VO1_MEM_ST = 27, ++ PD_AUDIO_MEM_ST = 28, ++ PD_PHP_MEM_ST = 29, ++ PD_GMAC_MEM_ST = 30, ++ PD_PCIE_MEM_ST = 31, ++ PD_NVM0_MEM_ST = 33, ++ PD_SDIO_MEM_ST = 34, ++ PD_USB_MEM_ST = 35, ++ PD_SDMMC_MEM_ST = 37, ++}; ++ ++enum pmu2_qid { ++ QID_PHPMMU_TBU = 0, ++ QID_PHPMMU_TCU = 1, ++ QID_PCIEMMU_TBU0 = 2, ++ QID_PCIEMU_TCU = 3, ++ QID_PHP_GICITS = 4, ++ QID_BUS_GICITS0 = 5, ++ QID_BUS_GICITS1 = 6, ++}; ++ ++/* PMU_DSU_PWR_CON */ ++enum pmu_dsu_pwr_con { ++ DSU_PWRDN_ENA = 2, ++ DSU_PWROFF_ENA, ++ DSU_RET_ENA = 6, ++ CLUSTER_CLK_SRC_GATE_ENA, ++ DSU_PWR_CON_END ++}; ++ ++enum cpu_power_state { ++ CPU_POWER_ON, ++ CPU_POWER_OFF, ++ CPU_EMULATION_OFF, ++ CPU_RETENTION, ++ CPU_DEBUG ++}; ++ ++enum dsu_power_state { ++ DSU_POWER_ON, ++ CLUSTER_TRANSFER_IDLE, ++ DSU_POWER_DOWN, ++ DSU_OFF, ++ DSU_WAKEUP, ++ DSU_POWER_UP, ++ CLUSTER_TRANSFER_RESUME, ++ DSU_FUNCTION_RETENTION ++}; ++ ++/* PMU2_CLUSTER_STS 0x8080 */ ++enum pmu2_cluster_sts_bits { ++ pd_cpu0_dwn = 0, ++ pd_cpu1_dwn, ++ pd_cpu2_dwn, ++ pd_cpu3_dwn, ++ pd_cpu4_dwn, ++ pd_cpu5_dwn, ++ pd_cpu6_dwn, ++ pd_cpu7_dwn, ++ pd_core0_dwn, ++ pd_core1_dwn ++}; ++ ++#define CLUSTER_STS_NONBOOT_CPUS_DWN 0xfe ++ ++enum cpu_off_trigger { ++ CPU_OFF_TRIGGER_WFE = 0, ++ CPU_OFF_TRIGGER_REQ_EML, ++ CPU_OFF_TRIGGER_REQ_WFI, ++ CPU_OFF_TRIGGER_REQ_WFI_NBT_CPU, ++ CPU_OFF_TRIGGER_REQ_WFI_NBT_CPU_SRAM ++}; ++ ++/***************************************************************************** ++ * power domain on or off ++ *****************************************************************************/ ++enum pmu_pd_state { ++ pmu_pd_on = 0, ++ pmu_pd_off = 1 ++}; ++ ++enum bus_state { ++ bus_active, ++ bus_idle, ++}; ++ ++#define RK_CPU_STATUS_OFF 0 ++#define RK_CPU_STATUS_ON 1 ++#define RK_CPU_STATUS_BUSY -1 ++ ++#define PD_CTR_LOOP 500 ++#define MAX_WAIT_COUNT 500 ++ ++#define pmu_bus_idle_st(id) \ ++ (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST((id) / 32)) & BIT((id) % 32))) ++ ++#define pmu_bus_idle_ack(id) \ ++ (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ACK((id) / 32)) & BIT((id) % 32))) ++ ++void pm_pll_wait_lock(uint32_t pll_base); ++#endif /* __PMU_H__ */ +diff --git a/plat/rockchip/rk3588/drivers/scmi/plat_scmi_def.h b/plat/rockchip/rk3588/drivers/scmi/plat_scmi_def.h +new file mode 100644 +index 0000000..0b9ca72 +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/scmi/plat_scmi_def.h +@@ -0,0 +1,17 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef PLAT_SCMI_DEF_H ++#define PLAT_SCMI_DEF_H ++ ++#include ++ ++#define SMT_BUFFER_BASE SCMI_SHARE_MEM_BASE ++#define SMT_BUFFER0_BASE SMT_BUFFER_BASE ++ ++void rockchip_init_scmi_server(void); ++ ++#endif /* PLAT_SCMI_DEF_H */ +diff --git a/plat/rockchip/rk3588/drivers/scmi/rk3588_clk.c b/plat/rockchip/rk3588/drivers/scmi/rk3588_clk.c +new file mode 100644 +index 0000000..ab3af5f +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/scmi/rk3588_clk.c +@@ -0,0 +1,2463 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include "rk3588_clk.h" ++#include ++#include ++#include ++ ++enum pll_type_sel { ++ PLL_SEL_AUTO, /* all plls (normal pll or pvtpll) */ ++ PLL_SEL_PVT, ++ PLL_SEL_NOR, ++ PLL_SEL_AUTO_NOR /* all normal plls (apll/gpll/npll) */ ++}; ++ ++#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) ++ ++#define RK3588_CPUL_PVTPLL_CON0_L 0x40 ++#define RK3588_CPUL_PVTPLL_CON0_H 0x44 ++#define RK3588_CPUL_PVTPLL_CON1 0x48 ++#define RK3588_CPUL_PVTPLL_CON2 0x4c ++#define RK3588_CPUB_PVTPLL_CON0_L 0x00 ++#define RK3588_CPUB_PVTPLL_CON0_H 0x04 ++#define RK3588_CPUB_PVTPLL_CON1 0x08 ++#define RK3588_CPUB_PVTPLL_CON2 0x0c ++#define RK3588_DSU_PVTPLL_CON0_L 0x60 ++#define RK3588_DSU_PVTPLL_CON0_H 0x64 ++#define RK3588_DSU_PVTPLL_CON1 0x70 ++#define RK3588_DSU_PVTPLL_CON2 0x74 ++#define RK3588_GPU_PVTPLL_CON0_L 0x00 ++#define RK3588_GPU_PVTPLL_CON0_H 0x04 ++#define RK3588_GPU_PVTPLL_CON1 0x08 ++#define RK3588_GPU_PVTPLL_CON2 0x0c ++#define RK3588_NPU_PVTPLL_CON0_L 0x0c ++#define RK3588_NPU_PVTPLL_CON0_H 0x10 ++#define RK3588_NPU_PVTPLL_CON1 0x14 ++#define RK3588_NPU_PVTPLL_CON2 0x18 ++#define RK3588_PVTPLL_MAX_LENGTH 0x3f ++ ++#define GPLL_RATE 1188000000 ++#define CPLL_RATE 1500000000 ++#define SPLL_RATE 702000000 ++#define AUPLL_RATE 786431952 ++#define NPLL_RATE 850000000 ++ ++#define MAX_RATE_TABLE 16 ++ ++#define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift) ++#define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift) ++#define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift) ++#define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift) ++#define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift) ++#define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift) ++ ++#define CPU_PLL_PATH_SLOWMODE BITS_WITH_WMASK(0U, 0x3U, 0) ++#define CPU_PLL_PATH_NORMAL BITS_WITH_WMASK(1U, 0x3U, 0) ++#define CPU_PLL_PATH_DEEP_SLOW BITS_WITH_WMASK(2U, 0x3U, 0) ++ ++#define CRU_PLL_POWER_DOWN BIT_WITH_WMSK(13) ++#define CRU_PLL_POWER_UP WMSK_BIT(13) ++ ++/* core_i: from gpll or apll */ ++#define CLK_CORE_I_SEL_APLL WMSK_BIT(6) ++#define CLK_CORE_I_SEL_GPLL BIT_WITH_WMSK(6) ++ ++/* clk_core: ++ * from normal pll(core_i: gpll or apll) path or direct pass from apll ++ */ ++ ++/* cpul clk path */ ++#define CPUL_CLK_PATH_NOR_XIN BITS_WITH_WMASK(0U, 0x3U, 14) ++#define CPUL_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(1U, 0x3U, 14) ++#define CPUL_CLK_PATH_NOR_LPLL BITS_WITH_WMASK(2U, 0x3U, 14) ++ ++#define CPUL_CLK_PATH_LPLL (BITS_WITH_WMASK(0U, 0x3U, 5) | \ ++ BITS_WITH_WMASK(0U, 0x3U, 12)) ++#define CPUL_CLK_PATH_DIR_LPLL (BITS_WITH_WMASK(0x1, 0x3U, 5) | \ ++ BITS_WITH_WMASK(1U, 0x3U, 12)) ++#define CPUL_CLK_PATH_PVTPLL (BITS_WITH_WMASK(0x2, 0x3U, 5) | \ ++ BITS_WITH_WMASK(2U, 0x3U, 12)) ++ ++#define CPUL_PVTPLL_PATH_DEEP_SLOW BITS_WITH_WMASK(0U, 0x1U, 14) ++#define CPUL_PVTPLL_PATH_PVTPLL BITS_WITH_WMASK(1U, 0x1U, 14) ++ ++/* cpub01 clk path */ ++#define CPUB01_CLK_PATH_NOR_XIN BITS_WITH_WMASK(0U, 0x3U, 6) ++#define CPUB01_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(1U, 0x3U, 6) ++#define CPUB01_CLK_PATH_NOR_B0PLL BITS_WITH_WMASK(2U, 0x3U, 6) ++ ++#define CPUB01_CLK_PATH_B0PLL BITS_WITH_WMASK(0U, 0x3U, 13) ++#define CPUB01_CLK_PATH_DIR_B0PLL BITS_WITH_WMASK(1U, 0x3U, 13) ++#define CPUB01_CLK_PATH_B0_PVTPLL BITS_WITH_WMASK(2U, 0x3U, 13) ++ ++#define CPUB01_CLK_PATH_B1PLL BITS_WITH_WMASK(0U, 0x3U, 5) ++#define CPUB01_CLK_PATH_DIR_B1PLL BITS_WITH_WMASK(1U, 0x3U, 5) ++#define CPUB01_CLK_PATH_B1_PVTPLL BITS_WITH_WMASK(2U, 0x3U, 5) ++ ++#define CPUB01_PVTPLL_PATH_DEEP_SLOW BITS_WITH_WMASK(0U, 0x1U, 2) ++#define CPUB01_PVTPLL_PATH_PVTPLL BITS_WITH_WMASK(1U, 0x1U, 2) ++ ++#define CPUB_PCLK_PATH_100M BITS_WITH_WMASK(0U, 0x3U, 0) ++#define CPUB_PCLK_PATH_50M BITS_WITH_WMASK(1U, 0x3U, 0) ++#define CPUB_PCLK_PATH_24M BITS_WITH_WMASK(2U, 0x3U, 0) ++ ++/* dsu clk path */ ++#define SCLK_DSU_PATH_NOR_B0PLL BITS_WITH_WMASK(0U, 0x3U, 12) ++#define SCLK_DSU_PATH_NOR_B1PLL BITS_WITH_WMASK(1U, 0x3U, 12) ++#define SCLK_DSU_PATH_NOR_LPLL BITS_WITH_WMASK(2U, 0x3U, 12) ++#define SCLK_DSU_PATH_NOR_GPLL BITS_WITH_WMASK(3U, 0x3U, 12) ++ ++#define DSU_PVTPLL_PATH_DEEP_SLOW BITS_WITH_WMASK(0U, 0x1U, 15) ++#define DSU_PVTPLL_PATH_PVTPLL BITS_WITH_WMASK(1U, 0x1U, 15) ++ ++#define SCLK_DSU_PATH_NOR_PLL WMSK_BIT(0) ++#define SCLK_DSU_PATH_PVTPLL BIT_WITH_WMSK(0) ++ ++/* npu clk path */ ++#define NPU_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(0U, 0x7U, 7) ++#define NPU_CLK_PATH_NOR_CPLL BITS_WITH_WMASK(1U, 0x7U, 7) ++#define NPU_CLK_PATH_NOR_AUPLL BITS_WITH_WMASK(2U, 0x7U, 7) ++#define NPU_CLK_PATH_NOR_NPLL BITS_WITH_WMASK(3U, 0x7U, 7) ++#define NPU_CLK_PATH_NOR_SPLL BITS_WITH_WMASK(4U, 0x7U, 7) ++ ++#define NPU_CLK_PATH_NOR_PLL WMSK_BIT(0) ++#define NPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(0) ++ ++/* gpu clk path */ ++#define GPU_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(0U, 0x7U, 5) ++#define GPU_CLK_PATH_NOR_CPLL BITS_WITH_WMASK(1U, 0x7U, 5) ++#define GPU_CLK_PATH_NOR_AUPLL BITS_WITH_WMASK(2U, 0x7U, 5) ++#define GPU_CLK_PATH_NOR_NPLL BITS_WITH_WMASK(3U, 0x7U, 5) ++#define GPU_CLK_PATH_NOR_SPLL BITS_WITH_WMASK(4U, 0x7U, 5) ++#define GPU_CLK_PATH_NOR_PLL WMSK_BIT(14) ++#define GPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(14) ++ ++#define PVTPLL_NEED(type, length) (((type) == PLL_SEL_PVT || \ ++ (type) == PLL_SEL_AUTO) && \ ++ (length)) ++ ++struct pvtpll_table { ++ unsigned int rate; ++ uint32_t length; ++ uint32_t ring_sel; ++}; ++ ++struct sys_clk_info_t { ++ struct pvtpll_table *cpul_table; ++ struct pvtpll_table *cpub01_table; ++ struct pvtpll_table *cpub23_table; ++ struct pvtpll_table *gpu_table; ++ struct pvtpll_table *npu_table; ++ unsigned int cpul_rate_count; ++ unsigned int cpub01_rate_count; ++ unsigned int cpub23_rate_count; ++ unsigned int gpu_rate_count; ++ unsigned int npu_rate_count; ++ unsigned long cpul_rate; ++ unsigned long dsu_rate; ++ unsigned long cpub01_rate; ++ unsigned long cpub23_rate; ++ unsigned long gpu_rate; ++ unsigned long npu_rate; ++}; ++ ++#define RK3588_SCMI_CLOCK(_id, _name, _data, _table, _cnt, _is_s) \ ++{ \ ++ .id = _id, \ ++ .name = _name, \ ++ .clk_ops = _data, \ ++ .rate_table = _table, \ ++ .rate_cnt = _cnt, \ ++ .is_security = _is_s, \ ++} ++ ++#define ROCKCHIP_PVTPLL(_rate, _sel, _len) \ ++{ \ ++ .rate = _rate##U, \ ++ .ring_sel = _sel, \ ++ .length = _len, \ ++} ++ ++static struct pvtpll_table rk3588_cpul_pvtpll_table[] = { ++ /* rate_hz, ring_sel, length */ ++ ROCKCHIP_PVTPLL(1800000000, 1, 15), ++ ROCKCHIP_PVTPLL(1704000000, 1, 15), ++ ROCKCHIP_PVTPLL(1608000000, 1, 15), ++ ROCKCHIP_PVTPLL(1416000000, 1, 15), ++ ROCKCHIP_PVTPLL(1200000000, 1, 17), ++ ROCKCHIP_PVTPLL(1008000000, 1, 22), ++ ROCKCHIP_PVTPLL(816000000, 1, 32), ++ ROCKCHIP_PVTPLL(600000000, 0, 0), ++ ROCKCHIP_PVTPLL(408000000, 0, 0), ++ { /* sentinel */ }, ++}; ++ ++static struct pvtpll_table rk3588_cpub0_pvtpll_table[] = { ++ /* rate_hz, ring_sel, length */ ++ ROCKCHIP_PVTPLL(2400000000, 1, 11), ++ ROCKCHIP_PVTPLL(2352000000, 1, 11), ++ ROCKCHIP_PVTPLL(2304000000, 1, 11), ++ ROCKCHIP_PVTPLL(2256000000, 1, 11), ++ ROCKCHIP_PVTPLL(2208000000, 1, 11), ++ ROCKCHIP_PVTPLL(2112000000, 1, 11), ++ ROCKCHIP_PVTPLL(2016000000, 1, 11), ++ ROCKCHIP_PVTPLL(1800000000, 1, 11), ++ ROCKCHIP_PVTPLL(1608000000, 1, 11), ++ ROCKCHIP_PVTPLL(1416000000, 1, 13), ++ ROCKCHIP_PVTPLL(1200000000, 1, 17), ++ ROCKCHIP_PVTPLL(1008000000, 1, 23), ++ ROCKCHIP_PVTPLL(816000000, 1, 33), ++ ROCKCHIP_PVTPLL(600000000, 0, 0), ++ ROCKCHIP_PVTPLL(408000000, 0, 0), ++ { /* sentinel */ }, ++}; ++ ++static struct ++pvtpll_table rk3588_cpub1_pvtpll_table[ARRAY_SIZE(rk3588_cpub0_pvtpll_table)] = { 0 }; ++ ++static struct pvtpll_table rk3588_gpu_pvtpll_table[] = { ++ /* rate_hz, ring_sel, length */ ++ ROCKCHIP_PVTPLL(1000000000, 1, 12), ++ ROCKCHIP_PVTPLL(900000000, 1, 12), ++ ROCKCHIP_PVTPLL(800000000, 1, 12), ++ ROCKCHIP_PVTPLL(700000000, 1, 13), ++ ROCKCHIP_PVTPLL(600000000, 1, 17), ++ ROCKCHIP_PVTPLL(500000000, 1, 25), ++ ROCKCHIP_PVTPLL(400000000, 1, 38), ++ ROCKCHIP_PVTPLL(300000000, 1, 55), ++ ROCKCHIP_PVTPLL(200000000, 0, 0), ++ { /* sentinel */ }, ++}; ++ ++static struct pvtpll_table rk3588_npu_pvtpll_table[] = { ++ /* rate_hz, ring_sel, length */ ++ ROCKCHIP_PVTPLL(1000000000, 1, 12), ++ ROCKCHIP_PVTPLL(900000000, 1, 12), ++ ROCKCHIP_PVTPLL(800000000, 1, 12), ++ ROCKCHIP_PVTPLL(700000000, 1, 13), ++ ROCKCHIP_PVTPLL(600000000, 1, 17), ++ ROCKCHIP_PVTPLL(500000000, 1, 25), ++ ROCKCHIP_PVTPLL(400000000, 1, 38), ++ ROCKCHIP_PVTPLL(300000000, 1, 55), ++ ROCKCHIP_PVTPLL(200000000, 0, 0), ++ { /* sentinel */ }, ++}; ++ ++static unsigned long rk3588_cpul_rates[] = { ++ 408000000, 600000000, 816000000, 1008000000, ++ 1200000000, 1416000000, 1608000000, 1800000063, ++}; ++ ++static unsigned long rk3588_cpub_rates[] = { ++ 408000000, 816000000, 1008000000, 1200000000, ++ 1416000000, 1608000000, 1800000000, 2016000000, ++ 2208000000, 2304000000, 2400000063 ++}; ++ ++static unsigned long rk3588_gpu_rates[] = { ++ 200000000, 300000000, 400000000, 500000000, ++ 600000000, 700000000, 800000000, 900000000, ++ 1000000063 ++}; ++ ++static unsigned long rk3588_sbus_rates[] = { ++ 24000000, 50000000, 100000000, 150000000, 200000000, ++ 250000000, 350000000, 700000000 ++}; ++ ++static unsigned long rk3588_sdmmc_rates[] = { ++ 400000, 24000000, 50000000, 100000000, 150000000, 200000000, ++ 300000000, 400000000, 600000000, 700000000 ++}; ++ ++static struct sys_clk_info_t sys_clk_info; ++static int clk_scmi_dsu_set_rate(rk_scmi_clock_t *clock, unsigned long rate); ++ ++static struct pvtpll_table *rkclk_get_pvtpll_config(struct pvtpll_table *table, ++ unsigned int count, ++ unsigned int freq_hz) ++{ ++ int i; ++ ++ for (i = 0; i < count; i++) { ++ if (freq_hz == table[i].rate) ++ return &table[i]; ++ } ++ return NULL; ++} ++ ++static int clk_cpul_set_rate(unsigned long rate, enum pll_type_sel type) ++{ ++ struct pvtpll_table *pvtpll; ++ int div; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpul_table, ++ sys_clk_info.cpul_rate_count, rate); ++ if (pvtpll == NULL) ++ return SCMI_INVALID_PARAMETERS; ++ ++ /* set lpll */ ++ if (PVTPLL_NEED(type, pvtpll->length) != 0) { ++ /* set clock gating interval */ ++ mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON2, ++ 0x00040000); ++ /* set ring sel */ ++ mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L, ++ 0x07000000 | (pvtpll->ring_sel << 8)); ++ /* set length */ ++ mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_H, ++ 0x003f0000 | pvtpll->length); ++ /* set cal cnt = 24, T = 1us */ ++ mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON1, ++ 0x18); ++ /* enable pvtpll */ ++ mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L, ++ 0x00020002); ++ /* start monitor */ ++ mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L, ++ 0x00010001); ++ /* set corel mux pvtpll */ ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), ++ CPUL_PVTPLL_PATH_PVTPLL); ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6), ++ CPUL_CLK_PATH_PVTPLL); ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), ++ CPUL_CLK_PATH_PVTPLL); ++ return 0; ++ } ++ ++ /* set clk corel div */ ++ div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6), ++ CLKDIV_5BITS_SHF(div, 0) | CLKDIV_5BITS_SHF(div, 7)); ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), ++ CLKDIV_5BITS_SHF(div, 0) | CLKDIV_5BITS_SHF(div, 7)); ++ /* set corel mux gpll */ ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5), ++ CPUL_CLK_PATH_NOR_GPLL); ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6), ++ CPUL_CLK_PATH_LPLL); ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), ++ CPUL_CLK_PATH_LPLL); ++ ++ return 0; ++} ++ ++static int clk_scmi_cpul_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int ret; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ ret = clk_cpul_set_rate(rate, PLL_SEL_AUTO); ++ if (ret == 0) { ++ sys_clk_info.cpul_rate = rate; ++ ret = clk_scmi_dsu_set_rate(clock, rate); ++ } ++ ++ return ret; ++} ++ ++static unsigned long rk3588_lpll_get_rate(void) ++{ ++ unsigned int m, p, s, k; ++ uint64_t rate64 = 24000000, postdiv; ++ int mode; ++ ++ mode = (mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(5)) >> 14) & ++ 0x3; ++ ++ if (mode == 0) ++ return rate64; ++ ++ m = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(16)) >> ++ CRU_PLLCON0_M_SHIFT) & ++ CRU_PLLCON0_M_MASK; ++ p = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >> ++ CRU_PLLCON1_P_SHIFT) & ++ CRU_PLLCON1_P_MASK; ++ s = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >> ++ CRU_PLLCON1_S_SHIFT) & ++ CRU_PLLCON1_S_MASK; ++ k = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(18)) >> ++ CRU_PLLCON2_K_SHIFT) & ++ CRU_PLLCON2_K_MASK; ++ ++ rate64 *= m; ++ rate64 = rate64 / p; ++ ++ if (k != 0) { ++ /* fractional mode */ ++ uint64_t frac_rate64 = 24000000 * k; ++ ++ postdiv = p * 65535; ++ frac_rate64 = frac_rate64 / postdiv; ++ rate64 += frac_rate64; ++ } ++ rate64 = rate64 >> s; ++ ++ return (unsigned long)rate64; ++} ++ ++static unsigned long clk_scmi_cpul_get_rate(rk_scmi_clock_t *clock) ++{ ++ int src, div; ++ ++ src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(6)) & 0x0060; ++ src = src >> 5; ++ if (src == 2) { ++ return sys_clk_info.cpul_rate; ++ } else { ++ src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(5)) & 0xc000; ++ src = src >> 14; ++ div = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(6)) & 0x1f; ++ switch (src) { ++ case 0: ++ return 24000000; ++ case 1: ++ /* Make the return rate is equal to the set rate */ ++ if (sys_clk_info.cpul_rate) ++ return sys_clk_info.cpul_rate; ++ else ++ return GPLL_RATE / (div + 1); ++ case 2: ++ return rk3588_lpll_get_rate(); ++ default: ++ return 0; ++ } ++ } ++} ++ ++static int clk_scmi_cpul_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static void clk_scmi_b0pll_disable(void) ++{ ++ static bool is_b0pll_disabled; ++ ++ if (is_b0pll_disabled != 0) ++ return; ++ ++ /* set coreb01 mux gpll */ ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), ++ CPUB01_CLK_PATH_NOR_GPLL); ++ /* pll enter slow mode */ ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE); ++ /* set pll power down */ ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1), CRU_PLL_POWER_DOWN); ++ ++ is_b0pll_disabled = true; ++} ++ ++static int clk_cpub01_set_rate(unsigned long rate, enum pll_type_sel type) ++{ ++ struct pvtpll_table *pvtpll; ++ int div; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpub01_table, ++ sys_clk_info.cpub01_rate_count, rate); ++ if (pvtpll == NULL) ++ return SCMI_INVALID_PARAMETERS; ++ ++ /* set b0pll */ ++ if (PVTPLL_NEED(type, pvtpll->length)) { ++ /* set clock gating interval */ ++ mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON2, ++ 0x00040000); ++ /* set ring sel */ ++ mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, ++ 0x07000000 | (pvtpll->ring_sel << 8)); ++ /* set length */ ++ mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_H, ++ 0x003f0000 | pvtpll->length); ++ /* set cal cnt = 24, T = 1us */ ++ mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON1, ++ 0x18); ++ /* enable pvtpll */ ++ mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, ++ 0x00020002); ++ /* start monitor */ ++ mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, ++ 0x00010001); ++ /* set core mux pvtpll */ ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), ++ CPUB01_PVTPLL_PATH_PVTPLL); ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), ++ CPUB01_CLK_PATH_B0_PVTPLL); ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1), ++ CPUB01_CLK_PATH_B1_PVTPLL); ++ goto out; ++ } ++ ++ /* set clk coreb01 div */ ++ div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), ++ CLKDIV_5BITS_SHF(div, 8)); ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1), ++ CLKDIV_5BITS_SHF(div, 0)); ++ /* set coreb01 mux gpll */ ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), ++ CPUB01_CLK_PATH_NOR_GPLL); ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), ++ CPUB01_CLK_PATH_B0PLL); ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1), ++ CPUB01_CLK_PATH_B1PLL); ++ ++out: ++ clk_scmi_b0pll_disable(); ++ ++ return 0; ++} ++ ++static int clk_scmi_cpub01_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int ret; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ ret = clk_cpub01_set_rate(rate, PLL_SEL_AUTO); ++ if (ret == 0) ++ sys_clk_info.cpub01_rate = rate; ++ ++ return ret; ++} ++ ++static unsigned long rk3588_b0pll_get_rate(void) ++{ ++ unsigned int m, p, s, k; ++ uint64_t rate64 = 24000000, postdiv; ++ int mode; ++ ++ mode = (mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0)) >> 6) & ++ 0x3; ++ ++ if (mode == 0) ++ return rate64; ++ ++ m = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(0)) >> ++ CRU_PLLCON0_M_SHIFT) & ++ CRU_PLLCON0_M_MASK; ++ p = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1)) >> ++ CRU_PLLCON1_P_SHIFT) & ++ CRU_PLLCON1_P_MASK; ++ s = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1)) >> ++ CRU_PLLCON1_S_SHIFT) & ++ CRU_PLLCON1_S_MASK; ++ k = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(2)) >> ++ CRU_PLLCON2_K_SHIFT) & ++ CRU_PLLCON2_K_MASK; ++ ++ rate64 *= m; ++ rate64 = rate64 / p; ++ ++ if (k != 0) { ++ /* fractional mode */ ++ uint64_t frac_rate64 = 24000000 * k; ++ ++ postdiv = p * 65535; ++ frac_rate64 = frac_rate64 / postdiv; ++ rate64 += frac_rate64; ++ } ++ rate64 = rate64 >> s; ++ ++ return (unsigned long)rate64; ++} ++ ++static unsigned long clk_scmi_cpub01_get_rate(rk_scmi_clock_t *clock) ++{ ++ int value, src, div; ++ ++ value = mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0)); ++ src = (value & 0x6000) >> 13; ++ if (src == 2) { ++ return sys_clk_info.cpub01_rate; ++ } else { ++ src = (value & 0x00c0) >> 6; ++ div = (value & 0x1f00) >> 8; ++ switch (src) { ++ case 0: ++ return 24000000; ++ case 1: ++ /* Make the return rate is equal to the set rate */ ++ if (sys_clk_info.cpub01_rate) ++ return sys_clk_info.cpub01_rate; ++ else ++ return GPLL_RATE / (div + 1); ++ case 2: ++ return rk3588_b0pll_get_rate(); ++ default: ++ return 0; ++ } ++ } ++} ++ ++static int clk_scmi_cpub01_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static void clk_scmi_b1pll_disable(void) ++{ ++ static bool is_b1pll_disabled; ++ ++ if (is_b1pll_disabled != 0) ++ return; ++ ++ /* set coreb23 mux gpll */ ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), ++ CPUB01_CLK_PATH_NOR_GPLL); ++ /* pll enter slow mode */ ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE); ++ /* set pll power down */ ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9), CRU_PLL_POWER_DOWN); ++ ++ is_b1pll_disabled = true; ++} ++ ++static int clk_cpub23_set_rate(unsigned long rate, enum pll_type_sel type) ++{ ++ struct pvtpll_table *pvtpll; ++ int div; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpub23_table, ++ sys_clk_info.cpub23_rate_count, rate); ++ if (pvtpll == NULL) ++ return SCMI_INVALID_PARAMETERS; ++ ++ /* set b1pll */ ++ if (PVTPLL_NEED(type, pvtpll->length)) { ++ /* set clock gating interval */ ++ mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON2, ++ 0x00040000); ++ /* set ring sel */ ++ mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, ++ 0x07000000 | (pvtpll->ring_sel << 8)); ++ /* set length */ ++ mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_H, ++ 0x003f0000 | pvtpll->length); ++ /* set cal cnt = 24, T = 1us */ ++ mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON1, ++ 0x18); ++ /* enable pvtpll */ ++ mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, ++ 0x00020002); ++ /* start monitor */ ++ mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, ++ 0x00010001); ++ /* set core mux pvtpll */ ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), ++ CPUB01_PVTPLL_PATH_PVTPLL); ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), ++ CPUB01_CLK_PATH_B0_PVTPLL); ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1), ++ CPUB01_CLK_PATH_B1_PVTPLL); ++ goto out; ++ } ++ ++ /* set clk coreb23 div */ ++ div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), ++ CLKDIV_5BITS_SHF(div, 8)); ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1), ++ CLKDIV_5BITS_SHF(div, 0)); ++ /* set coreb23 mux gpll */ ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), ++ CPUB01_CLK_PATH_NOR_GPLL); ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), ++ CPUB01_CLK_PATH_B0PLL); ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1), ++ CPUB01_CLK_PATH_B1PLL); ++ ++out: ++ clk_scmi_b1pll_disable(); ++ ++ return 0; ++} ++ ++static int clk_scmi_cpub23_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int ret; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ ret = clk_cpub23_set_rate(rate, PLL_SEL_AUTO); ++ if (ret == 0) ++ sys_clk_info.cpub23_rate = rate; ++ ++ return ret; ++} ++ ++static unsigned long rk3588_b1pll_get_rate(void) ++{ ++ unsigned int m, p, s, k; ++ uint64_t rate64 = 24000000, postdiv; ++ int mode; ++ ++ mode = (mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0)) >> 6) & ++ 0x3; ++ ++ if (mode == 0) ++ return rate64; ++ ++ m = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(8)) >> ++ CRU_PLLCON0_M_SHIFT) & ++ CRU_PLLCON0_M_MASK; ++ p = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9)) >> ++ CRU_PLLCON1_P_SHIFT) & ++ CRU_PLLCON1_P_MASK; ++ s = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9)) >> ++ CRU_PLLCON1_S_SHIFT) & ++ CRU_PLLCON1_S_MASK; ++ k = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(10)) >> ++ CRU_PLLCON2_K_SHIFT) & ++ CRU_PLLCON2_K_MASK; ++ ++ rate64 *= m; ++ rate64 = rate64 / p; ++ ++ if (k != 0) { ++ /* fractional mode */ ++ uint64_t frac_rate64 = 24000000 * k; ++ ++ postdiv = p * 65535; ++ frac_rate64 = frac_rate64 / postdiv; ++ rate64 += frac_rate64; ++ } ++ rate64 = rate64 >> s; ++ ++ return (unsigned long)rate64; ++} ++ ++static unsigned long clk_scmi_cpub23_get_rate(rk_scmi_clock_t *clock) ++{ ++ int value, src, div; ++ ++ value = mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0)); ++ src = (value & 0x6000) >> 13; ++ if (src == 2) { ++ return sys_clk_info.cpub23_rate; ++ } else { ++ src = (value & 0x00c0) >> 6; ++ div = (value & 0x1f00) >> 8; ++ switch (src) { ++ case 0: ++ return 24000000; ++ case 1: ++ /* Make the return rate is equal to the set rate */ ++ if (sys_clk_info.cpub23_rate) ++ return sys_clk_info.cpub23_rate; ++ else ++ return GPLL_RATE / (div + 1); ++ case 2: ++ return rk3588_b1pll_get_rate(); ++ default: ++ return 0; ++ } ++ } ++} ++ ++static int clk_scmi_cpub23_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_dsu_get_rate(rk_scmi_clock_t *clock) ++{ ++ int src, div; ++ ++ src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(1)) & 0x1; ++ if (src != 0) { ++ return sys_clk_info.dsu_rate; ++ } else { ++ src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(0)) & 0x3000; ++ src = src >> 12; ++ div = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(0)) & 0xf80; ++ div = div >> 7; ++ switch (src) { ++ case 0: ++ return rk3588_b0pll_get_rate() / (div + 1); ++ case 1: ++ return rk3588_b1pll_get_rate() / (div + 1); ++ case 2: ++ return rk3588_lpll_get_rate() / (div + 1); ++ case 3: ++ return GPLL_RATE / (div + 1); ++ default: ++ return 0; ++ } ++ } ++} ++ ++static void clk_scmi_lpll_disable(void) ++{ ++ static bool is_lpll_disabled; ++ ++ if (is_lpll_disabled) ++ return; ++ ++ /* set corel mux gpll */ ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5), ++ CPUL_CLK_PATH_NOR_GPLL); ++ /* set dsu mux gpll */ ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0), ++ SCLK_DSU_PATH_NOR_GPLL); ++ /* pll enter slow mode */ ++ mmio_write_32(DSUCRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE); ++ /* set pll power down */ ++ mmio_write_32(DSUCRU_BASE + CRU_PLL_CON(17), CRU_PLL_POWER_DOWN); ++ ++ is_lpll_disabled = true; ++} ++ ++static int clk_dsu_set_rate(unsigned long rate, enum pll_type_sel type) ++{ ++ struct pvtpll_table *pvtpll; ++ int div; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpul_table, ++ sys_clk_info.cpul_rate_count, rate); ++ if (pvtpll == NULL) ++ return SCMI_INVALID_PARAMETERS; ++ ++ /* set pvtpll */ ++ if (PVTPLL_NEED(type, pvtpll->length)) { ++ /* set clock gating interval */ ++ mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON2, ++ 0x00040000); ++ /* set ring sel */ ++ mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L, ++ 0x07000000 | (pvtpll->ring_sel << 8)); ++ /* set length */ ++ mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_H, ++ 0x003f0000 | pvtpll->length); ++ /* set cal cnt = 24, T = 1us */ ++ mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON1, ++ 0x18); ++ /* enable pvtpll */ ++ mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L, ++ 0x00020002); ++ /* start monitor */ ++ mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L, ++ 0x00010001); ++ /* set dsu mux pvtpll */ ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), ++ DSU_PVTPLL_PATH_PVTPLL); ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(1), ++ SCLK_DSU_PATH_PVTPLL); ++ goto out; ++ } ++ /* set dsu div */ ++ div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0), ++ CLKDIV_5BITS_SHF(div, 7)); ++ /* set dsu mux gpll */ ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0), ++ SCLK_DSU_PATH_NOR_GPLL); ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(1), ++ SCLK_DSU_PATH_NOR_PLL); ++ ++out: ++ clk_scmi_lpll_disable(); ++ ++ return 0; ++} ++ ++static int clk_scmi_dsu_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int ret; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ ret = clk_dsu_set_rate(rate, PLL_SEL_AUTO); ++ ++ if (ret == 0) ++ sys_clk_info.dsu_rate = rate; ++ return ret; ++} ++ ++static int clk_scmi_dsu_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_gpu_get_rate(rk_scmi_clock_t *clock) ++{ ++ int div, src; ++ ++ if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x4000) != 0) { ++ return sys_clk_info.gpu_rate; ++ } else { ++ div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x1f; ++ src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x00e0; ++ src = src >> 5; ++ switch (src) { ++ case 0: ++ /* Make the return rate is equal to the set rate */ ++ if (sys_clk_info.gpu_rate) ++ return sys_clk_info.gpu_rate; ++ else ++ return GPLL_RATE / (div + 1); ++ case 1: ++ return CPLL_RATE / (div + 1); ++ case 2: ++ return AUPLL_RATE / (div + 1); ++ case 3: ++ return NPLL_RATE / (div + 1); ++ case 4: ++ return SPLL_RATE / (div + 1); ++ default: ++ return 0; ++ } ++ } ++} ++ ++static int clk_gpu_set_rate(unsigned long rate, enum pll_type_sel type) ++{ ++ struct pvtpll_table *pvtpll; ++ int div; ++ ++ pvtpll = rkclk_get_pvtpll_config(sys_clk_info.gpu_table, ++ sys_clk_info.gpu_rate_count, rate); ++ if (pvtpll == NULL) ++ return SCMI_INVALID_PARAMETERS; ++ ++ if (PVTPLL_NEED(type, pvtpll->length)) { ++ /* set clock gating interval */ ++ mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON2, ++ 0x00040000); ++ /* set ring sel */ ++ mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_L, ++ 0x07000000 | (pvtpll->ring_sel << 8)); ++ /* set length */ ++ mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_H, ++ 0x003f0000 | pvtpll->length); ++ /* set cal cnt = 24, T = 1us */ ++ mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON1, ++ 0x18); ++ /* enable pvtpll */ ++ mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_L, ++ 0x00020002); ++ /* start monitor */ ++ mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_L, ++ 0x00010001); ++ /* set gpu mux pvtpll */ ++ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), ++ GPU_CLK_PATH_PVTPLL); ++ return 0; ++ } ++ ++ /* set gpu div */ ++ div = DIV_ROUND_UP(GPLL_RATE, rate); ++ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), ++ CLKDIV_5BITS_SHF(div - 1, 0)); ++ /* set gpu mux gpll */ ++ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), ++ GPU_CLK_PATH_NOR_GPLL); ++ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), ++ GPU_CLK_PATH_NOR_PLL); ++ ++ return 0; ++} ++ ++static int clk_scmi_gpu_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int ret; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ ret = clk_gpu_set_rate(rate, PLL_SEL_AUTO); ++ if (ret == 0) ++ sys_clk_info.gpu_rate = rate; ++ ++ return ret; ++} ++ ++static int clk_scmi_gpu_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_npu_get_rate(rk_scmi_clock_t *clock) ++{ ++ int div, src; ++ ++ if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(74)) & 0x1) != 0) { ++ return sys_clk_info.npu_rate; ++ } else { ++ div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(73)) & 0x007c; ++ div = div >> 2; ++ src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(73)) & 0x0380; ++ src = src >> 7; ++ switch (src) { ++ case 0: ++ /* Make the return rate is equal to the set rate */ ++ if (sys_clk_info.npu_rate != 0) ++ return sys_clk_info.npu_rate; ++ else ++ return GPLL_RATE / (div + 1); ++ case 1: ++ return CPLL_RATE / (div + 1); ++ case 2: ++ return AUPLL_RATE / (div + 1); ++ case 3: ++ return NPLL_RATE / (div + 1); ++ case 4: ++ return SPLL_RATE / (div + 1); ++ default: ++ return 0; ++ } ++ } ++} ++ ++static int clk_npu_set_rate(unsigned long rate, enum pll_type_sel type) ++{ ++ struct pvtpll_table *pvtpll; ++ int div; ++ ++ pvtpll = rkclk_get_pvtpll_config(sys_clk_info.npu_table, ++ sys_clk_info.npu_rate_count, rate); ++ if (pvtpll == NULL) ++ return SCMI_INVALID_PARAMETERS; ++ ++ if (PVTPLL_NEED(type, pvtpll->length)) { ++ /* set clock gating interval */ ++ mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON2, ++ 0x00040000); ++ /* set ring sel */ ++ mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_L, ++ 0x07000000 | (pvtpll->ring_sel << 8)); ++ /* set length */ ++ mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_H, ++ 0x003f0000 | pvtpll->length); ++ /* set cal cnt = 24, T = 1us */ ++ mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON1, ++ 0x18); ++ /* enable pvtpll */ ++ mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_L, ++ 0x00020002); ++ /* start monitor */ ++ mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_L, ++ 0x00010001); ++ /* set npu mux pvtpll */ ++ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(74), ++ NPU_CLK_PATH_PVTPLL); ++ return 0; ++ } ++ ++ /* set npu div */ ++ div = DIV_ROUND_UP(GPLL_RATE, rate); ++ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(73), ++ CLKDIV_5BITS_SHF(div - 1, 2)); ++ /* set npu mux gpll */ ++ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(73), ++ NPU_CLK_PATH_NOR_GPLL); ++ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(74), ++ NPU_CLK_PATH_NOR_PLL); ++ ++ return 0; ++} ++ ++static int clk_scmi_npu_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int ret; ++ ++ if (rate == 0) ++ return SCMI_INVALID_PARAMETERS; ++ ++ ret = clk_npu_set_rate(rate, PLL_SEL_AUTO); ++ if (ret == 0) ++ sys_clk_info.npu_rate = rate; ++ ++ return ret; ++} ++ ++static int clk_scmi_npu_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_sbus_get_rate(rk_scmi_clock_t *clock) ++{ ++ int div; ++ ++ if ((mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)) & 0x0800) != 0) { ++ div = mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)); ++ div = (div & 0x03e0) >> 5; ++ return SPLL_RATE / (div + 1); ++ } else { ++ return OSC_HZ; ++ } ++} ++ ++static int clk_scmi_sbus_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int div; ++ ++ if (rate == OSC_HZ) { ++ mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), ++ WMSK_BIT(11)); ++ return 0; ++ } ++ ++ div = DIV_ROUND_UP(SPLL_RATE, rate); ++ mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), ++ CLKDIV_5BITS_SHF(div - 1, 5)); ++ mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), ++ BIT_WITH_WMSK(11) | WMSK_BIT(10)); ++ return 0; ++} ++ ++static int clk_scmi_sbus_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_pclk_sbus_get_rate(rk_scmi_clock_t *clock) ++{ ++ int div; ++ ++ div = mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)); ++ div = div & 0x001f; ++ return SPLL_RATE / (div + 1); ++ ++} ++ ++static int clk_scmi_pclk_sbus_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int div; ++ ++ div = DIV_ROUND_UP(SPLL_RATE, rate); ++ mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), ++ CLKDIV_5BITS_SHF(div - 1, 0)); ++ return 0; ++} ++ ++static int clk_scmi_pclk_sbus_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_cclk_sdmmc_get_rate(rk_scmi_clock_t *clock) ++{ ++ int div; ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x3000; ++ src = src >> 12; ++ div = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x0fc0; ++ div = div >> 6; ++ if (src == 1) { ++ return SPLL_RATE / (div + 1); ++ } else if (src == 2) { ++ return OSC_HZ / (div + 1); ++ } else { ++ return GPLL_RATE / (div + 1); ++ } ++} ++ ++static int clk_scmi_cclk_sdmmc_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int div; ++ ++ if ((OSC_HZ % rate) == 0) { ++ div = DIV_ROUND_UP(OSC_HZ, rate); ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), ++ CLKDIV_6BITS_SHF(div - 1, 6) | ++ BITS_WITH_WMASK(2U, 0x3U, 12)); ++ } else if ((SPLL_RATE % rate) == 0) { ++ div = DIV_ROUND_UP(SPLL_RATE, rate); ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), ++ CLKDIV_6BITS_SHF(div - 1, 6) | ++ BITS_WITH_WMASK(1U, 0x3U, 12)); ++ } else { ++ div = DIV_ROUND_UP(GPLL_RATE, rate); ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), ++ CLKDIV_6BITS_SHF(div - 1, 6) | ++ BITS_WITH_WMASK(0U, 0x3U, 12)); ++ } ++ ++ return 0; ++} ++ ++static int clk_scmi_cclk_sdmmc_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), ++ BITS_WITH_WMASK(!status, 0x1U, 4)); ++ return 0; ++} ++ ++static unsigned long clk_scmi_dclk_sdmmc_get_rate(rk_scmi_clock_t *clock) ++{ ++ int div; ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x0020; ++ div = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x001f; ++ if (src != 0) { ++ return SPLL_RATE / (div + 1); ++ } else { ++ return GPLL_RATE / (div + 1); ++ } ++} ++ ++static int clk_scmi_dclk_sdmmc_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ int div; ++ ++ if ((SPLL_RATE % rate) == 0) { ++ div = DIV_ROUND_UP(SPLL_RATE, rate); ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), ++ CLKDIV_5BITS_SHF(div - 1, 0) | ++ BITS_WITH_WMASK(1U, 0x1U, 5)); ++ } else { ++ div = DIV_ROUND_UP(GPLL_RATE, rate); ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), ++ CLKDIV_5BITS_SHF(div - 1, 0) | ++ BITS_WITH_WMASK(0U, 0x1U, 5)); ++ } ++ return 0; ++} ++ ++static int clk_scmi_dclk_sdmmc_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), ++ BITS_WITH_WMASK(!status, 0x1U, 1)); ++ return 0; ++} ++ ++static unsigned long clk_scmi_aclk_secure_ns_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0003; ++ switch (src) { ++ case 0: ++ return 350 * MHz; ++ case 1: ++ return 200 * MHz; ++ case 2: ++ return 100 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_aclk_secure_ns_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 350 * MHz) ++ src = 0; ++ else if (rate >= 200 * MHz) ++ src = 1; ++ else if (rate >= 100 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), ++ BITS_WITH_WMASK(src, 0x3U, 0)); ++ ++ return 0; ++} ++ ++static int clk_scmi_aclk_secure_ns_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_hclk_secure_ns_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x000c; ++ src = src >> 2; ++ switch (src) { ++ case 0: ++ return 150 * MHz; ++ case 1: ++ return 100 * MHz; ++ case 2: ++ return 50 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_hclk_secure_ns_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 150 * MHz) ++ src = 0; ++ else if (rate >= 100 * MHz) ++ src = 1; ++ else if (rate >= 50 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), ++ BITS_WITH_WMASK(src, 0x3U, 2)); ++ return 0; ++} ++ ++static int clk_scmi_hclk_secure_ns_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_tclk_wdt_get_rate(rk_scmi_clock_t *clock) ++{ ++ return OSC_HZ; ++} ++ ++static int clk_scmi_tclk_wdt_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2), ++ BITS_WITH_WMASK(!status, 0x1U, 0)); ++ return 0; ++} ++ ++static unsigned long clk_scmi_keyladder_core_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x00c0; ++ src = src >> 6; ++ switch (src) { ++ case 0: ++ return 350 * MHz; ++ case 1: ++ return 233 * MHz; ++ case 2: ++ return 116 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_keyladder_core_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 350 * MHz) ++ src = 0; ++ else if (rate >= 233 * MHz) ++ src = 1; ++ else if (rate >= 116 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), ++ BITS_WITH_WMASK(src, 0x3U, 6)); ++ return 0; ++} ++ ++static int clk_scmi_keyladder_core_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 9)); ++ return 0; ++} ++ ++static unsigned long clk_scmi_keyladder_rng_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x0300; ++ src = src >> 8; ++ switch (src) { ++ case 0: ++ return 175 * MHz; ++ case 1: ++ return 116 * MHz; ++ case 2: ++ return 58 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_keyladder_rng_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 175 * MHz) ++ src = 0; ++ else if (rate >= 116 * MHz) ++ src = 1; ++ else if (rate >= 58 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), ++ BITS_WITH_WMASK(src, 0x3U, 8)); ++ return 0; ++} ++ ++static int clk_scmi_keyladder_rng_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 10)); ++ return 0; ++} ++ ++static unsigned long clk_scmi_aclk_secure_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0030; ++ src = src >> 4; ++ switch (src) { ++ case 0: ++ return 350 * MHz; ++ case 1: ++ return 233 * MHz; ++ case 2: ++ return 116 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_aclk_secure_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 350 * MHz) ++ src = 0; ++ else if (rate >= 233 * MHz) ++ src = 1; ++ else if (rate >= 116 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), ++ BITS_WITH_WMASK(src, 0x3U, 4)); ++ return 0; ++} ++ ++static int clk_scmi_aclk_secure_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_hclk_secure_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x00c0; ++ src = src >> 6; ++ switch (src) { ++ case 0: ++ return 175 * MHz; ++ case 1: ++ return 116 * MHz; ++ case 2: ++ return 58 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_hclk_secure_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 175 * MHz) ++ src = 0; ++ else if (rate >= 116 * MHz) ++ src = 1; ++ else if (rate >= 58 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), ++ BITS_WITH_WMASK(src, 0x3U, 6)); ++ return 0; ++} ++ ++static int clk_scmi_hclk_secure_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_pclk_secure_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0300; ++ src = src >> 8; ++ switch (src) { ++ case 0: ++ return 116 * MHz; ++ case 1: ++ return 58 * MHz; ++ case 2: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_pclk_secure_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 116 * MHz) ++ src = 0; ++ else if (rate >= 58 * MHz) ++ src = 1; ++ else ++ src = 2; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), ++ BITS_WITH_WMASK(src, 0x3U, 8)); ++ return 0; ++} ++ ++static int clk_scmi_pclk_secure_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_crypto_rng_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0xc000; ++ src = src >> 14; ++ switch (src) { ++ case 0: ++ return 175 * MHz; ++ case 1: ++ return 116 * MHz; ++ case 2: ++ return 58 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_crypto_rng_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 175 * MHz) ++ src = 0; ++ else if (rate >= 116 * MHz) ++ src = 1; ++ else if (rate >= 58 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), ++ BITS_WITH_WMASK(src, 0x3U, 14)); ++ return 0; ++} ++ ++static int clk_scmi_crypto_rng_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 1)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_crypto_core_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0c00; ++ src = src >> 10; ++ switch (src) { ++ case 0: ++ return 350 * MHz; ++ case 1: ++ return 233 * MHz; ++ case 2: ++ return 116 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_crypto_core_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 350 * MHz) ++ src = 0; ++ else if (rate >= 233 * MHz) ++ src = 1; ++ else if (rate >= 116 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), ++ BITS_WITH_WMASK(src, 0x3U, 10)); ++ return 0; ++} ++ ++static int clk_scmi_crypto_core_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(0), ++ BITS_WITH_WMASK(!status, 0x1U, 15)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_crypto_pka_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x3000; ++ src = src >> 12; ++ switch (src) { ++ case 0: ++ return 350 * MHz; ++ case 1: ++ return 233 * MHz; ++ case 2: ++ return 116 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_crypto_pka_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 350 * MHz) ++ src = 0; ++ else if (rate >= 233 * MHz) ++ src = 1; ++ else if (rate >= 116 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), ++ BITS_WITH_WMASK(src, 0x3U, 12)); ++ return 0; ++} ++ ++static int clk_scmi_crypto_pka_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 0)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_spll_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(BUSSCRU_BASE + CRU_MODE_CON0) & 0x3; ++ switch (src) { ++ case 0: ++ return OSC_HZ; ++ case 1: ++ return 702 * MHz; ++ case 2: ++ return 32768; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_spll_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 700 * MHz) ++ src = 1; ++ else ++ src = 0; ++ ++ mmio_write_32(BUSSCRU_BASE + CRU_MODE_CON0, ++ BITS_WITH_WMASK(0, 0x3U, 0)); ++ mmio_write_32(BUSSCRU_BASE + CRU_PLL_CON(137), ++ BITS_WITH_WMASK(2, 0x7U, 6)); ++ ++ mmio_write_32(BUSSCRU_BASE + CRU_MODE_CON0, ++ BITS_WITH_WMASK(src, 0x3U, 0)); ++ return 0; ++} ++ ++static int clk_scmi_spll_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ return 0; ++} ++ ++static unsigned long clk_scmi_hclk_sd_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_hclk_secure_ns_get_rate(clock); ++} ++ ++static int clk_scmi_hclk_sd_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), ++ BITS_WITH_WMASK(!status, 0x1U, 2)); ++ return 0; ++} ++ ++static unsigned long clk_scmi_crypto_rng_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x0030; ++ src = src >> 4; ++ switch (src) { ++ case 0: ++ return 175 * MHz; ++ case 1: ++ return 116 * MHz; ++ case 2: ++ return 58 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_crypto_rng_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 175 * MHz) ++ src = 0; ++ else if (rate >= 116 * MHz) ++ src = 1; ++ else if (rate >= 58 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), ++ BITS_WITH_WMASK(src, 0x3U, 4)); ++ return 0; ++} ++ ++static int clk_scmi_crypto_rng_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 6)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_crypto_core_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x3; ++ src = src >> 0; ++ switch (src) { ++ case 0: ++ return 350 * MHz; ++ case 1: ++ return 233 * MHz; ++ case 2: ++ return 116 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_crypto_core_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 350 * MHz) ++ src = 0; ++ else if (rate >= 233 * MHz) ++ src = 1; ++ else if (rate >= 116 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), ++ BITS_WITH_WMASK(src, 0x3U, 0)); ++ return 0; ++} ++ ++static int clk_scmi_crypto_core_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 4)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_crypto_pka_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ uint32_t src; ++ ++ src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x000c; ++ src = src >> 2; ++ switch (src) { ++ case 0: ++ return 350 * MHz; ++ case 1: ++ return 233 * MHz; ++ case 2: ++ return 116 * MHz; ++ case 3: ++ return OSC_HZ; ++ default: ++ return 0; ++ } ++} ++ ++static int clk_scmi_crypto_pka_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ uint32_t src; ++ ++ if (rate >= 350 * MHz) ++ src = 0; ++ else if (rate >= 233 * MHz) ++ src = 1; ++ else if (rate >= 116 * MHz) ++ src = 2; ++ else ++ src = 3; ++ ++ mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), ++ BITS_WITH_WMASK(src, 0x3U, 2)); ++ return 0; ++} ++ ++static int clk_scmi_crypto_pka_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 5)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_a_crypto_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_aclk_secure_s_get_rate(clock); ++} ++ ++static int clk_scmi_a_crypto_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ return clk_scmi_aclk_secure_s_set_rate(clock, rate); ++} ++ ++static int clk_scmi_a_crypto_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 7)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_h_crypto_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_hclk_secure_s_get_rate(clock); ++} ++ ++static int clk_scmi_h_crypto_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ return clk_scmi_hclk_secure_s_set_rate(clock, rate); ++} ++ ++static int clk_scmi_h_crypto_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 8)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_p_crypto_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_pclk_secure_s_get_rate(clock); ++} ++ ++static int clk_scmi_p_crypto_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ return clk_scmi_pclk_secure_s_set_rate(clock, rate); ++} ++ ++static int clk_scmi_p_crypto_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2), ++ BITS_WITH_WMASK(!status, 0x1U, 13)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_a_keylad_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_aclk_secure_s_get_rate(clock); ++} ++ ++static int clk_scmi_a_keylad_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ return clk_scmi_aclk_secure_s_set_rate(clock, rate); ++} ++ ++static int clk_scmi_a_keylad_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 11)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_h_keylad_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_hclk_secure_s_get_rate(clock); ++} ++ ++static int clk_scmi_h_keylad_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ return clk_scmi_hclk_secure_s_set_rate(clock, rate); ++} ++ ++static int clk_scmi_h_keylad_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 12)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_p_keylad_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_pclk_secure_s_get_rate(clock); ++} ++ ++static int clk_scmi_p_keylad_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ return clk_scmi_pclk_secure_s_set_rate(clock, rate); ++} ++ ++static int clk_scmi_p_keylad_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2), ++ BITS_WITH_WMASK(!status, 0x1U, 14)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_trng_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_hclk_secure_s_get_rate(clock); ++} ++ ++static int clk_scmi_trng_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ return clk_scmi_hclk_secure_s_set_rate(clock, rate); ++} ++ ++static int clk_scmi_trng_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), ++ BITS_WITH_WMASK(!status, 0x1U, 6)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_h_trng_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_hclk_secure_s_get_rate(clock); ++} ++ ++static int clk_scmi_h_trng_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ return clk_scmi_hclk_secure_s_set_rate(clock, rate); ++} ++ ++static int clk_scmi_h_trng_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2), ++ BITS_WITH_WMASK(!status, 0x1U, 15)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_p_otpc_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return clk_scmi_pclk_secure_s_get_rate(clock); ++} ++ ++static int clk_scmi_p_otpc_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) ++{ ++ return clk_scmi_pclk_secure_s_set_rate(clock, rate); ++} ++ ++static int clk_scmi_p_otpc_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 13)); ++ ++ return 0; ++} ++ ++static unsigned long clk_scmi_otpc_s_get_rate(rk_scmi_clock_t *clock) ++{ ++ return OSC_HZ; ++} ++ ++static int clk_scmi_otpc_s_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), ++ BITS_WITH_WMASK(!status, 0x1U, 14)); ++ return 0; ++} ++ ++static unsigned long clk_scmi_otp_phy_get_rate(rk_scmi_clock_t *clock) ++{ ++ return OSC_HZ; ++} ++ ++static int clk_scmi_otp_phy_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), ++ BITS_WITH_WMASK(!status, 0x1U, 13)); ++ return 0; ++} ++ ++static unsigned long clk_scmi_otpc_rd_get_rate(rk_scmi_clock_t *clock) ++{ ++ return OSC_HZ; ++} ++ ++static int clk_scmi_otpc_rd_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), ++ BITS_WITH_WMASK(!status, 0x1U, 12)); ++ return 0; ++} ++ ++static unsigned long clk_scmi_otpc_arb_get_rate(rk_scmi_clock_t *clock) ++{ ++ return OSC_HZ; ++} ++ ++static int clk_scmi_otpc_arb_set_status(rk_scmi_clock_t *clock, bool status) ++{ ++ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), ++ BITS_WITH_WMASK(!status, 0x1U, 11)); ++ return 0; ++} ++ ++static const struct rk_clk_ops clk_scmi_cpul_ops = { ++ .get_rate = clk_scmi_cpul_get_rate, ++ .set_rate = clk_scmi_cpul_set_rate, ++ .set_status = clk_scmi_cpul_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_dsu_ops = { ++ .get_rate = clk_scmi_dsu_get_rate, ++ .set_rate = clk_scmi_dsu_set_rate, ++ .set_status = clk_scmi_dsu_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_cpub01_ops = { ++ .get_rate = clk_scmi_cpub01_get_rate, ++ .set_rate = clk_scmi_cpub01_set_rate, ++ .set_status = clk_scmi_cpub01_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_cpub23_ops = { ++ .get_rate = clk_scmi_cpub23_get_rate, ++ .set_rate = clk_scmi_cpub23_set_rate, ++ .set_status = clk_scmi_cpub23_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_gpu_ops = { ++ .get_rate = clk_scmi_gpu_get_rate, ++ .set_rate = clk_scmi_gpu_set_rate, ++ .set_status = clk_scmi_gpu_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_npu_ops = { ++ .get_rate = clk_scmi_npu_get_rate, ++ .set_rate = clk_scmi_npu_set_rate, ++ .set_status = clk_scmi_npu_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_sbus_ops = { ++ .get_rate = clk_scmi_sbus_get_rate, ++ .set_rate = clk_scmi_sbus_set_rate, ++ .set_status = clk_scmi_sbus_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_pclk_sbus_ops = { ++ .get_rate = clk_scmi_pclk_sbus_get_rate, ++ .set_rate = clk_scmi_pclk_sbus_set_rate, ++ .set_status = clk_scmi_pclk_sbus_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_cclk_sdmmc_ops = { ++ .get_rate = clk_scmi_cclk_sdmmc_get_rate, ++ .set_rate = clk_scmi_cclk_sdmmc_set_rate, ++ .set_status = clk_scmi_cclk_sdmmc_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_dclk_sdmmc_ops = { ++ .get_rate = clk_scmi_dclk_sdmmc_get_rate, ++ .set_rate = clk_scmi_dclk_sdmmc_set_rate, ++ .set_status = clk_scmi_dclk_sdmmc_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_aclk_secure_ns_ops = { ++ .get_rate = clk_scmi_aclk_secure_ns_get_rate, ++ .set_rate = clk_scmi_aclk_secure_ns_set_rate, ++ .set_status = clk_scmi_aclk_secure_ns_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_hclk_secure_ns_ops = { ++ .get_rate = clk_scmi_hclk_secure_ns_get_rate, ++ .set_rate = clk_scmi_hclk_secure_ns_set_rate, ++ .set_status = clk_scmi_hclk_secure_ns_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_tclk_wdt_ops = { ++ .get_rate = clk_scmi_tclk_wdt_get_rate, ++ .set_status = clk_scmi_tclk_wdt_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_keyladder_core_ops = { ++ .get_rate = clk_scmi_keyladder_core_get_rate, ++ .set_rate = clk_scmi_keyladder_core_set_rate, ++ .set_status = clk_scmi_keyladder_core_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_keyladder_rng_ops = { ++ .get_rate = clk_scmi_keyladder_rng_get_rate, ++ .set_rate = clk_scmi_keyladder_rng_set_rate, ++ .set_status = clk_scmi_keyladder_rng_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_aclk_secure_s_ops = { ++ .get_rate = clk_scmi_aclk_secure_s_get_rate, ++ .set_rate = clk_scmi_aclk_secure_s_set_rate, ++ .set_status = clk_scmi_aclk_secure_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_hclk_secure_s_ops = { ++ .get_rate = clk_scmi_hclk_secure_s_get_rate, ++ .set_rate = clk_scmi_hclk_secure_s_set_rate, ++ .set_status = clk_scmi_hclk_secure_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_pclk_secure_s_ops = { ++ .get_rate = clk_scmi_pclk_secure_s_get_rate, ++ .set_rate = clk_scmi_pclk_secure_s_set_rate, ++ .set_status = clk_scmi_pclk_secure_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_crypto_rng_ops = { ++ .get_rate = clk_scmi_crypto_rng_get_rate, ++ .set_rate = clk_scmi_crypto_rng_set_rate, ++ .set_status = clk_scmi_crypto_rng_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_crypto_core_ops = { ++ .get_rate = clk_scmi_crypto_core_get_rate, ++ .set_rate = clk_scmi_crypto_core_set_rate, ++ .set_status = clk_scmi_crypto_core_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_crypto_pka_ops = { ++ .get_rate = clk_scmi_crypto_pka_get_rate, ++ .set_rate = clk_scmi_crypto_pka_set_rate, ++ .set_status = clk_scmi_crypto_pka_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_spll_ops = { ++ .get_rate = clk_scmi_spll_get_rate, ++ .set_rate = clk_scmi_spll_set_rate, ++ .set_status = clk_scmi_spll_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_hclk_sd_ops = { ++ .get_rate = clk_scmi_hclk_sd_get_rate, ++ .set_status = clk_scmi_hclk_sd_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_crypto_rng_s_ops = { ++ .get_rate = clk_scmi_crypto_rng_s_get_rate, ++ .set_rate = clk_scmi_crypto_rng_s_set_rate, ++ .set_status = clk_scmi_crypto_rng_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_crypto_core_s_ops = { ++ .get_rate = clk_scmi_crypto_core_s_get_rate, ++ .set_rate = clk_scmi_crypto_core_s_set_rate, ++ .set_status = clk_scmi_crypto_core_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_crypto_pka_s_ops = { ++ .get_rate = clk_scmi_crypto_pka_s_get_rate, ++ .set_rate = clk_scmi_crypto_pka_s_set_rate, ++ .set_status = clk_scmi_crypto_pka_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_a_crypto_s_ops = { ++ .get_rate = clk_scmi_a_crypto_s_get_rate, ++ .set_rate = clk_scmi_a_crypto_s_set_rate, ++ .set_status = clk_scmi_a_crypto_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_h_crypto_s_ops = { ++ .get_rate = clk_scmi_h_crypto_s_get_rate, ++ .set_rate = clk_scmi_h_crypto_s_set_rate, ++ .set_status = clk_scmi_h_crypto_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_p_crypto_s_ops = { ++ .get_rate = clk_scmi_p_crypto_s_get_rate, ++ .set_rate = clk_scmi_p_crypto_s_set_rate, ++ .set_status = clk_scmi_p_crypto_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_a_keylad_s_ops = { ++ .get_rate = clk_scmi_a_keylad_s_get_rate, ++ .set_rate = clk_scmi_a_keylad_s_set_rate, ++ .set_status = clk_scmi_a_keylad_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_h_keylad_s_ops = { ++ .get_rate = clk_scmi_h_keylad_s_get_rate, ++ .set_rate = clk_scmi_h_keylad_s_set_rate, ++ .set_status = clk_scmi_h_keylad_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_p_keylad_s_ops = { ++ .get_rate = clk_scmi_p_keylad_s_get_rate, ++ .set_rate = clk_scmi_p_keylad_s_set_rate, ++ .set_status = clk_scmi_p_keylad_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_trng_s_ops = { ++ .get_rate = clk_scmi_trng_s_get_rate, ++ .set_rate = clk_scmi_trng_s_set_rate, ++ .set_status = clk_scmi_trng_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_h_trng_s_ops = { ++ .get_rate = clk_scmi_h_trng_s_get_rate, ++ .set_rate = clk_scmi_h_trng_s_set_rate, ++ .set_status = clk_scmi_h_trng_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_p_otpc_s_ops = { ++ .get_rate = clk_scmi_p_otpc_s_get_rate, ++ .set_rate = clk_scmi_p_otpc_s_set_rate, ++ .set_status = clk_scmi_p_otpc_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_otpc_s_ops = { ++ .get_rate = clk_scmi_otpc_s_get_rate, ++ .set_status = clk_scmi_otpc_s_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_otp_phy_ops = { ++ .get_rate = clk_scmi_otp_phy_get_rate, ++ .set_status = clk_scmi_otp_phy_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_otpc_rd_ops = { ++ .get_rate = clk_scmi_otpc_rd_get_rate, ++ .set_status = clk_scmi_otpc_rd_set_status, ++}; ++ ++static const struct rk_clk_ops clk_scmi_otpc_arb_ops = { ++ .get_rate = clk_scmi_otpc_arb_get_rate, ++ .set_status = clk_scmi_otpc_arb_set_status, ++}; ++ ++rk_scmi_clock_t clock_table[] = { ++ RK3588_SCMI_CLOCK(SCMI_CLK_CPUL, "scmi_clk_cpul", &clk_scmi_cpul_ops, rk3588_cpul_rates, ARRAY_SIZE(rk3588_cpul_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_CLK_DSU, "scmi_clk_dsu", &clk_scmi_dsu_ops, rk3588_cpul_rates, ARRAY_SIZE(rk3588_cpul_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_CLK_CPUB01, "scmi_clk_cpub01", &clk_scmi_cpub01_ops, rk3588_cpub_rates, ARRAY_SIZE(rk3588_cpub_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_CLK_CPUB23, "scmi_clk_cpub23", &clk_scmi_cpub23_ops, rk3588_cpub_rates, ARRAY_SIZE(rk3588_cpub_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_CLK_DDR, "scmi_clk_ddr", NULL, NULL, 0, false), ++ RK3588_SCMI_CLOCK(SCMI_CLK_GPU, "scmi_clk_gpu", &clk_scmi_gpu_ops, rk3588_gpu_rates, ARRAY_SIZE(rk3588_gpu_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_CLK_NPU, "scmi_clk_npu", &clk_scmi_npu_ops, rk3588_gpu_rates, ARRAY_SIZE(rk3588_gpu_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_CLK_SBUS, "scmi_clk_sbus", &clk_scmi_sbus_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_PCLK_SBUS, "scmi_pclk_sbus", &clk_scmi_pclk_sbus_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_CCLK_SD, "scmi_cclk_sd", &clk_scmi_cclk_sdmmc_ops, rk3588_sdmmc_rates, ARRAY_SIZE(rk3588_sdmmc_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_DCLK_SD, "scmi_dclk_sd", &clk_scmi_dclk_sdmmc_ops, rk3588_sdmmc_rates, ARRAY_SIZE(rk3588_sdmmc_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_ACLK_SECURE_NS, "scmi_aclk_se_ns", &clk_scmi_aclk_secure_ns_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_HCLK_SECURE_NS, "scmi_hclk_se_ns", &clk_scmi_hclk_secure_ns_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_TCLK_WDT, "scmi_tclk_wdt", &clk_scmi_tclk_wdt_ops, NULL, 0, false), ++ RK3588_SCMI_CLOCK(SCMI_KEYLADDER_CORE, "scmi_keylad_c", &clk_scmi_keyladder_core_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_KEYLADDER_RNG, "scmi_keylad_r", &clk_scmi_keyladder_rng_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_ACLK_SECURE_S, "scmi_aclk_se_s", &clk_scmi_aclk_secure_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_HCLK_SECURE_S, "scmi_hclk_se_s", &clk_scmi_hclk_secure_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_PCLK_SECURE_S, "scmi_pclk_se_s", &clk_scmi_pclk_secure_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_CRYPTO_RNG, "scmi_crypto_r", &clk_scmi_crypto_rng_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_CRYPTO_CORE, "scmi_crypto_c", &clk_scmi_crypto_core_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_CRYPTO_PKA, "scmi_crypto_p", &clk_scmi_crypto_pka_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_SPLL, "scmi_spll", &clk_scmi_spll_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), ++ RK3588_SCMI_CLOCK(SCMI_HCLK_SD, "scmi_hclk_sd", &clk_scmi_hclk_sd_ops, NULL, 0, false), ++ RK3588_SCMI_CLOCK(SCMI_CRYPTO_RNG_S, "scmi_crypto_r_s", &clk_scmi_crypto_rng_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_CRYPTO_CORE_S, "scmi_crypto_c_s", &clk_scmi_crypto_core_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_CRYPTO_PKA_S, "scmi_crypto_p_s", &clk_scmi_crypto_pka_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_A_CRYPTO_S, "scmi_a_crypto_s", &clk_scmi_a_crypto_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_H_CRYPTO_S, "scmi_h_crypto_s", &clk_scmi_h_crypto_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_P_CRYPTO_S, "scmi_p_crypto_s", &clk_scmi_p_crypto_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_A_KEYLADDER_S, "scmi_a_keylad_s", &clk_scmi_a_keylad_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_H_KEYLADDER_S, "scmi_h_keylad_s", &clk_scmi_h_keylad_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_P_KEYLADDER_S, "scmi_p_keylad_s", &clk_scmi_p_keylad_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_TRNG_S, "scmi_trng_s", &clk_scmi_trng_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_H_TRNG_S, "scmi_h_trng_s", &clk_scmi_h_trng_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_P_OTPC_S, "scmi_p_otpc_s", &clk_scmi_p_otpc_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), ++ RK3588_SCMI_CLOCK(SCMI_OTPC_S, "scmi_otpc_s", &clk_scmi_otpc_s_ops, NULL, 0, true), ++ RK3588_SCMI_CLOCK(SCMI_OTP_PHY, "scmi_otp_phy", &clk_scmi_otp_phy_ops, NULL, 0, false), ++ RK3588_SCMI_CLOCK(SCMI_OTPC_AUTO_RD, "scmi_otpc_rd", &clk_scmi_otpc_rd_ops, NULL, 0, false), ++ RK3588_SCMI_CLOCK(SCMI_OTPC_ARB, "scmi_otpc_arb", &clk_scmi_otpc_arb_ops, NULL, 0, false), ++}; ++ ++size_t rockchip_scmi_clock_count(unsigned int agent_id __unused) ++{ ++ return ARRAY_SIZE(clock_table); ++} ++ ++rk_scmi_clock_t *rockchip_scmi_get_clock(uint32_t agent_id __unused, ++ uint32_t clock_id) ++{ ++ rk_scmi_clock_t *table = NULL; ++ ++ if (clock_id < ARRAY_SIZE(clock_table)) ++ table = &clock_table[clock_id]; ++ ++ if (table && !table->is_security) ++ return table; ++ else ++ return NULL; ++} ++ ++void pvtplls_suspend(void) ++{ ++ clk_cpul_set_rate(408000000, PLL_SEL_NOR); ++ clk_dsu_set_rate(408000000, PLL_SEL_NOR); ++ clk_cpub01_set_rate(408000000, PLL_SEL_NOR); ++ clk_cpub23_set_rate(408000000, PLL_SEL_NOR); ++} ++ ++void pvtplls_resume(void) ++{ ++ clk_cpul_set_rate(sys_clk_info.cpul_rate, PLL_SEL_AUTO); ++ clk_dsu_set_rate(sys_clk_info.dsu_rate, PLL_SEL_AUTO); ++ clk_cpub01_set_rate(sys_clk_info.cpub01_rate, PLL_SEL_AUTO); ++ clk_cpub23_set_rate(sys_clk_info.cpub23_rate, PLL_SEL_AUTO); ++} ++ ++void sys_reset_pvtplls_prepare(void) ++{ ++ clk_gpu_set_rate(100000000, PLL_SEL_NOR); ++ clk_npu_set_rate(100000000, PLL_SEL_NOR); ++ clk_cpul_set_rate(408000000, PLL_SEL_NOR); ++ clk_cpub01_set_rate(408000000, PLL_SEL_NOR); ++ clk_cpub23_set_rate(408000000, PLL_SEL_NOR); ++ clk_dsu_set_rate(408000000, PLL_SEL_NOR); ++} ++ ++void rockchip_clock_init(void) ++{ ++ /* set gpll src div to 0 for cpul */ ++ mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5), CLKDIV_5BITS_SHF(0U, 9)); ++ /* set gpll src div to 0 for cpub01 */ ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), ++ CLKDIV_5BITS_SHF(0U, 1)); ++ /* set gpll src div to 0 for cpu23 */ ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), ++ CLKDIV_5BITS_SHF(0U, 1)); ++ ++ mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), ++ CPUB_PCLK_PATH_50M); ++ mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), ++ CPUB_PCLK_PATH_50M); ++ ++ mmio_write_32(DSUCRU_BASE + DSUCRU_CLKSEL_CON(4), ++ CLKDIV_5BITS_SHF(5U, 0)); ++ mmio_write_32(DSUCRU_BASE + DSUCRU_CLKSEL_CON(4), ++ BITS_WITH_WMASK(PCLK_DSU_ROOT_SEL_GPLL, ++ PCLK_DSU_ROOT_SEL_MASK, ++ PCLK_DSU_ROOT_SEL_SHIFT)); ++ ++ sys_clk_info.cpul_table = rk3588_cpul_pvtpll_table; ++ sys_clk_info.cpul_rate_count = ARRAY_SIZE(rk3588_cpul_pvtpll_table); ++ sys_clk_info.cpub01_table = rk3588_cpub0_pvtpll_table; ++ sys_clk_info.cpub01_rate_count = ARRAY_SIZE(rk3588_cpub0_pvtpll_table); ++ sys_clk_info.cpub23_table = rk3588_cpub1_pvtpll_table; ++ sys_clk_info.cpub23_rate_count = ARRAY_SIZE(rk3588_cpub1_pvtpll_table); ++ memcpy(sys_clk_info.cpub23_table, sys_clk_info.cpub01_table, ++ sys_clk_info.cpub01_rate_count * sizeof(*sys_clk_info.cpub01_table)); ++ sys_clk_info.gpu_table = rk3588_gpu_pvtpll_table; ++ sys_clk_info.gpu_rate_count = ARRAY_SIZE(rk3588_gpu_pvtpll_table); ++ sys_clk_info.npu_table = rk3588_npu_pvtpll_table; ++ sys_clk_info.npu_rate_count = ARRAY_SIZE(rk3588_npu_pvtpll_table); ++} +diff --git a/plat/rockchip/rk3588/drivers/scmi/rk3588_clk.h b/plat/rockchip/rk3588/drivers/scmi/rk3588_clk.h +new file mode 100644 +index 0000000..66fddaa +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/scmi/rk3588_clk.h +@@ -0,0 +1,104 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef __CLOCK_H__ ++#define __CLOCK_H__ ++ ++/* scmi-clocks indices */ ++ ++#define SCMI_CLK_CPUL 0 ++#define SCMI_CLK_DSU 1 ++#define SCMI_CLK_CPUB01 2 ++#define SCMI_CLK_CPUB23 3 ++#define SCMI_CLK_DDR 4 ++#define SCMI_CLK_GPU 5 ++#define SCMI_CLK_NPU 6 ++#define SCMI_CLK_SBUS 7 ++#define SCMI_PCLK_SBUS 8 ++#define SCMI_CCLK_SD 9 ++#define SCMI_DCLK_SD 10 ++#define SCMI_ACLK_SECURE_NS 11 ++#define SCMI_HCLK_SECURE_NS 12 ++#define SCMI_TCLK_WDT 13 ++#define SCMI_KEYLADDER_CORE 14 ++#define SCMI_KEYLADDER_RNG 15 ++#define SCMI_ACLK_SECURE_S 16 ++#define SCMI_HCLK_SECURE_S 17 ++#define SCMI_PCLK_SECURE_S 18 ++#define SCMI_CRYPTO_RNG 19 ++#define SCMI_CRYPTO_CORE 20 ++#define SCMI_CRYPTO_PKA 21 ++#define SCMI_SPLL 22 ++#define SCMI_HCLK_SD 23 ++#define SCMI_CRYPTO_RNG_S 24 ++#define SCMI_CRYPTO_CORE_S 25 ++#define SCMI_CRYPTO_PKA_S 26 ++#define SCMI_A_CRYPTO_S 27 ++#define SCMI_H_CRYPTO_S 28 ++#define SCMI_P_CRYPTO_S 29 ++#define SCMI_A_KEYLADDER_S 30 ++#define SCMI_H_KEYLADDER_S 31 ++#define SCMI_P_KEYLADDER_S 32 ++#define SCMI_TRNG_S 33 ++#define SCMI_H_TRNG_S 34 ++#define SCMI_P_OTPC_S 35 ++#define SCMI_OTPC_S 36 ++#define SCMI_OTP_PHY 37 ++#define SCMI_OTPC_AUTO_RD 38 ++#define SCMI_OTPC_ARB 39 ++ ++/******** DSUCRU **************************************/ ++#define DSUCRU_CLKSEL_CON(n) (0x0300 + (n) * 4) ++ ++/********Name=DSUCRU_CLKSEL_CON04,Offset=0x310********/ ++#define PCLK_DSU_ROOT_SEL_SHIFT 5 ++#define PCLK_DSU_ROOT_SEL_MASK 0x3 ++#define PCLK_DSU_ROOT_SEL_GPLL 0x3 ++ ++/********Name=SECURE_SOFTRST_CON00,Offset=0xA00********/ ++#define SRST_A_SECURE_NS_BIU 10 ++#define SRST_H_SECURE_NS_BIU 11 ++#define SRST_A_SECURE_S_BIU 12 ++#define SRST_H_SECURE_S_BIU 13 ++#define SRST_P_SECURE_S_BIU 14 ++#define SRST_CRYPTO_CORE 15 ++/********Name=SECURE_SOFTRST_CON01,Offset=0xA04********/ ++#define SRST_CRYPTO_PKA 16 ++#define SRST_CRYPTO_RNG 17 ++#define SRST_A_CRYPTO 18 ++#define SRST_H_CRYPTO 19 ++#define SRST_KEYLADDER_CORE 25 ++#define SRST_KEYLADDER_RNG 26 ++#define SRST_A_KEYLADDER 27 ++#define SRST_H_KEYLADDER 28 ++#define SRST_P_OTPC_S 29 ++#define SRST_OTPC_S 30 ++#define SRST_WDT_S 31 ++/********Name=SECURE_SOFTRST_CON02,Offset=0xA08********/ ++#define SRST_T_WDT_S 32 ++#define SRST_H_BOOTROM 33 ++#define SRST_A_DCF 34 ++#define SRST_P_DCF 35 ++#define SRST_H_BOOTROM_NS 37 ++#define SRST_P_KEYLADDER 46 ++#define SRST_H_TRNG_S 47 ++/********Name=SECURE_SOFTRST_CON03,Offset=0xA0C********/ ++#define SRST_H_TRNG_NS 48 ++#define SRST_D_SDMMC_BUFFER 49 ++#define SRST_H_SDMMC 50 ++#define SRST_H_SDMMC_BUFFER 51 ++#define SRST_SDMMC 52 ++#define SRST_P_TRNG_CHK 53 ++#define SRST_TRNG_S 54 ++ ++#define SRST_INVALID 55 ++ ++void pvtplls_suspend(void); ++void pvtplls_resume(void); ++ ++void rockchip_clock_init(void); ++ ++#endif +diff --git a/plat/rockchip/rk3588/drivers/scmi/rk3588_rstd.c b/plat/rockchip/rk3588/drivers/scmi/rk3588_rstd.c +new file mode 100644 +index 0000000..f1f26d3 +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/scmi/rk3588_rstd.c +@@ -0,0 +1,97 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "rk3588_clk.h" ++#include ++#include ++ ++#define DEFAULT_RESET_DOM_ATTRIBUTE 0 ++ ++#define RK3588_SCMI_RESET(_id, _name, _attribute, _ops) \ ++{ \ ++ .id = _id, \ ++ .name = _name, \ ++ .attribute = _attribute, \ ++ .rstd_ops = _ops, \ ++} ++ ++static int rk3588_reset_explicit(rk_scmi_rstd_t *reset_domain, ++ bool assert_not_deassert) ++{ ++ int bank = reset_domain->id / 16; ++ int offset = reset_domain->id % 16; ++ ++ mmio_write_32(SCRU_BASE + CRU_SOFTRST_CON(bank), ++ BITS_WITH_WMASK(assert_not_deassert, 0x1U, offset)); ++ return SCMI_SUCCESS; ++} ++ ++static struct rk_scmi_rstd_ops rk3588_reset_domain_ops = { ++ .reset_explicit = rk3588_reset_explicit, ++}; ++ ++static rk_scmi_rstd_t rk3588_reset_domain_table[] = { ++ RK3588_SCMI_RESET(SRST_CRYPTO_CORE, "scmi_sr_cy_core", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_CRYPTO_PKA, "scmi_sr_cy_pka", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_CRYPTO_RNG, "scmi_sr_cy_rng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_A_CRYPTO, "scmi_sr_a_cy", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_H_CRYPTO, "scmi_sr_h_cy", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_KEYLADDER_CORE, "scmi_sr_k_core", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_KEYLADDER_RNG, "scmi_sr_k_rng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_P_OTPC_S, "scmi_sr_p_otp", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_OTPC_S, "scmi_sr_otp", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_WDT_S, "scmi_sr_wdt", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_T_WDT_S, "scmi_sr_t_wdt", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_H_BOOTROM, "scmi_sr_h_boot", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_P_KEYLADDER, "scmi_sr_p_ky", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_H_TRNG_S, "scmi_sr_h_trng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_H_TRNG_NS, "scmi_sr_t_trng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_D_SDMMC_BUFFER, "scmi_sr_d_sd", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_H_SDMMC, "scmi_sr_h_sd", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_H_SDMMC_BUFFER, "scmi_sr_h_sd_b", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_SDMMC, "scmi_sr_sd", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_P_TRNG_CHK, "scmi_sr_p_trng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_TRNG_S, "scmi_sr_trng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), ++ RK3588_SCMI_RESET(SRST_INVALID, "scmi_sr_invalid", DEFAULT_RESET_DOM_ATTRIBUTE, NULL), ++}; ++ ++static rk_scmi_rstd_t * ++rockchip_get_reset_domain_table(int id) ++{ ++ rk_scmi_rstd_t *reset = rk3588_reset_domain_table; ++ int i = 0, cnt = ARRAY_SIZE(rk3588_reset_domain_table); ++ ++ for (i = 0; i < cnt; i++) { ++ if (reset->id == id) ++ return &rk3588_reset_domain_table[i]; ++ reset++; ++ } ++ ++ return &rk3588_reset_domain_table[cnt - 1]; ++} ++ ++rk_scmi_rstd_t *rockchip_scmi_get_rstd(unsigned int agent_id, ++ unsigned int scmi_id) ++ ++{ ++ return rockchip_get_reset_domain_table(scmi_id); ++} ++ ++size_t rockchip_scmi_rstd_count(unsigned int agent_id) ++{ ++ return SRST_TRNG_S; ++} ++ +diff --git a/plat/rockchip/rk3588/drivers/secure/secure.c b/plat/rockchip/rk3588/drivers/secure/secure.c +new file mode 100644 +index 0000000..fc9f211 +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/secure/secure.c +@@ -0,0 +1,188 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++static void secure_fw_master_init(void) ++{ ++ uint32_t i; ++ ++ /* ddr_mcu can access all ddr-regions */ ++ mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(1), 0x0000ffff); ++ /* dcf/crypto_s can access all ddr-regions */ ++ mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(14), 0x00000000); ++ /* dsu_mp_sec can access all ddr-regions. ++ * DSU access memory [f000_0000~ff00_0000] through MP in firewall_ddr. ++ */ ++ mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(36), 0xffff0000); ++ ++ /* all other ns-master can't access all ddr-regions */ ++ for (i = 0; i < FIREWALL_DDR_MST_CNT; i++) { ++ if (i == 1 || i == 14 || i == 36) ++ continue; ++ ++ mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(i), 0xffffffff); ++ } ++ ++ /* mcu_pmu can access all sram-regions */ ++ mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(19), 0x000000ff); ++ /* dsu mp-sec can access all sram-regions */ ++ mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(38), 0x000000ff); ++ /* nsp_dsu2main_sec can access all sram-regions */ ++ mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(41), 0x00000000); ++ ++ /* all ns-master can't access all sram-regions */ ++ for (i = 0; i < FIREWALL_SYSMEM_MST_CNT; i++) { ++ if (i == 19 || i == 38 || i == 41) ++ continue; ++ ++ mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(i), ++ 0x00ff00ff); ++ } ++ ++ /* dsu-ns can't access all ddr-regions, dsu-s can access all ddr-regions */ ++ mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(0), 0xffffffff); ++ mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(1), 0x00000000); ++ dsb(); ++ isb(); ++} ++ ++/* unit: Mb */ ++static void dsu_fw_rgn_config(uint64_t base_mb, uint64_t top_mb, int rgn_id) ++{ ++ int i; ++ ++ if (rgn_id >= FIREWALL_DSU_RGN_CNT || rgn_id < 0) { ++ ERROR("%s regions-id:%d is invalid!\n", __func__, rgn_id); ++ panic(); ++ } ++ ++ mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(rgn_id), ++ RG_MAP_SECURE(top_mb, base_mb)); ++ ++ for (i = 0; i < DDR_CHN_CNT; i++) ++ mmio_setbits_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i), ++ BIT(rgn_id)); ++} ++ ++/* unit: Mb */ ++static void ddr_fw_rgn_config(uint64_t base_mb, uint64_t top_mb, int rgn_id) ++{ ++ if (rgn_id >= FIREWALL_DDR_RGN_CNT || rgn_id < 0) { ++ ERROR("%s regions-id:%d is invalid!\n", __func__, rgn_id); ++ panic(); ++ } ++ ++ mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_RGN(rgn_id), ++ RG_MAP_SECURE(top_mb, base_mb)); ++ ++ /* enable region */ ++ mmio_setbits_32(FIREWALL_DDR_BASE + FIREWALL_DDR_CON, ++ BIT(rgn_id)); ++} ++ ++/* Unit: Kb */ ++static void sram_fw_rgn_config(uint64_t base_kb, uint64_t top_kb, int rgn_id) ++{ ++ if (rgn_id >= FIREWALL_SYSMEM_RGN_CNT || rgn_id < 0) { ++ ERROR("%s regions-id:%d is invalid!\n", __func__, rgn_id); ++ panic(); ++ } ++ ++ mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_RGN(rgn_id), ++ RG_MAP_SRAM_SECURE(top_kb, base_kb)); ++ ++ /* enable region */ ++ mmio_setbits_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_CON, BIT(rgn_id)); ++} ++ ++static void secure_region_init(void) ++{ ++ uint32_t i; ++ ++ /* disable all region first except region0 */ ++ mmio_clrbits_32(FIREWALL_DDR_BASE + FIREWALL_DDR_CON, 0xfffe); ++ for (i = 0; i < FIREWALL_DSU_CON_CNT; i++) ++ mmio_clrbits_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i), 0xfffe); ++ mmio_clrbits_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_CON, 0xfe); ++ ++ secure_fw_master_init(); ++ ++ /* Use FW_DDR_RGN0_REG to config 0~1M space to secure */ ++ dsu_fw_rgn_config(0, 1, 0); ++ ddr_fw_rgn_config(0, 1, 0); ++ ++ /* Use FIREWALL_SYSMEM_RGN0 to config SRAM_ENTRY code(0~4k of sram) to secure */ ++ sram_fw_rgn_config(0, 4, 0); ++ /* For 0xffff0000~0xffffffff, use FIREWALL_SYSMEM_RGN7 to config ++ * 960~1024k of sram to secure. ++ */ ++ sram_fw_rgn_config(960, 1024, 7); ++} ++ ++void secure_timer_init(void) ++{ ++ /* gpu's cntvalue comes from stimer1 channel_5 */ ++ mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, ++ TIMER_DIS); ++ ++ mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT0, 0xffffffff); ++ mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT1, 0xffffffff); ++ ++ /* auto reload & enable the timer */ ++ mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, ++ TIMER_EN | TIMER_FMODE); ++} ++ ++void sgrf_init(void) ++{ ++ uint32_t i; ++ ++ secure_region_init(); ++ ++ /* config master ddr_mcu_prot|dcf_wr|dcf_rd as secure */ ++ mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(14), 0x001f0011); ++ mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(15), 0xffffffff); ++ mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(16), 0x03ff03ff); ++ ++ /* config slave mailbox_mcu_ddr as secure */ ++ mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(4), 0xffff2000); ++ /* config slave int256mux4_mcu_ddr|int256mux4_mcu_pmu as secure */ ++ mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(5), 0xffff0060); ++ /* config slave ddrgrf*|dma2ddr|ddrphy*_cru|umctl* as secure */ ++ mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(24), 0xffff0fbf); ++ /* config slave ddrphy*|ddr_stanby*|ddr_mcu_timer|ddr_mcu_wdt as secure */ ++ mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(25), 0xffff03ff); ++ ++ /* config all other slave as ns */ ++ for (i = 0; i < SGRF_FIREWALL_CON_CNT; i++) { ++ if (i == 4 || i == 5 || i == 24 || i == 25) ++ continue; ++ ++ mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(i), 0xffff0000); ++ } ++ ++ /* config vad_hprot non-secure, pmu_mcu_hprot as secure */ ++ mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(0), 0x00180010); ++ /* config pmu1, pmu0, pmu_sram as secure */ ++ mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(1), 0xefbe6020); ++ /* config remap_pmu_mem, h_pmu_mem as secure */ ++ mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(2), 0x01f900c0); ++ ++ /* disable dp encryption */ ++ mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(13), 0x00180018); ++ ++ /* select grf config for pcie ats */ ++ mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(17), 0x11111111); ++ mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(18), 0x11111111); ++ mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(19), 0x00110011); ++} +diff --git a/plat/rockchip/rk3588/drivers/secure/secure.h b/plat/rockchip/rk3588/drivers/secure/secure.h +new file mode 100644 +index 0000000..d9c234f +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/secure/secure.h +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef SECURE_H ++#define SECURE_H ++ ++/* DSUSGRF */ ++#define DSU_SGRF_SOC_CON(i) ((i) * 4) ++#define DSUSGRF_SOC_CON(i) ((i) * 4) ++#define DSUSGRF_SOC_CON_CNT 13 ++#define DSUSGRF_DDR_HASH_CON(i) (0x240 + (i) * 4) ++#define DSUSGRF_DDR_HASH_CON_CNT 8 ++ ++/* PMUSGRF */ ++#define PMU1SGRF_SOC_CON(n) ((n) * 4) ++ ++/* SGRF */ ++#define SGRF_SOC_CON(i) ((i) * 4) ++#define SGRF_FIREWALL_CON(i) (0x240 + (i) * 4) ++#define SGRF_FIREWALL_CON_CNT 32 ++ ++/* ddr firewall */ ++#define FIREWALL_DDR_RGN(i) ((i) * 0x4) ++#define FIREWALL_DDR_RGN_CNT 16 ++#define FIREWALL_DDR_MST(i) (0x40 + (i) * 0x4) ++#define FIREWALL_DDR_MST_CNT 42 ++#define FIREWALL_DDR_CON 0xf0 ++ ++#define FIREWALL_SYSMEM_RGN(i) ((i) * 0x4) ++#define FIREWALL_SYSMEM_RGN_CNT 8 ++#define FIREWALL_SYSMEM_MST(i) (0x40 + (i) * 0x4) ++#define FIREWALL_SYSMEM_MST_CNT 43 ++#define FIREWALL_SYSMEM_CON 0xf0 ++ ++#define FIREWALL_DSU_RGN(i) ((i) * 0x4) ++#define FIREWALL_DSU_RGN_CNT 16 ++#define FIREWALL_DSU_MST(i) (0x40 + (i) * 0x4) ++#define FIREWALL_DSU_MST_CNT 2 ++#define FIREWALL_DSU_CON(i) (0xf0 + (i) * 4) ++#define FIREWALL_DSU_CON_CNT 4 ++ ++#define PLAT_MAX_DDR_CAPACITY_MB 0x8000 /* for 32Gb */ ++#define RG_MAP_SECURE(top, base) \ ++ (((((top) - 1) & 0x7fff) << 16) | ((base) & 0x7fff)) ++#define RG_MAP_SRAM_SECURE(top_kb, base_kb) \ ++ (((((top_kb) / 4 - 1) & 0xff) << 16) | ((base_kb) / 4 & 0xff)) ++ ++void secure_timer_init(void); ++void sgrf_init(void); ++ ++#endif /* SECURE_H */ +diff --git a/plat/rockchip/rk3588/drivers/soc/soc.c b/plat/rockchip/rk3588/drivers/soc/soc.c +new file mode 100644 +index 0000000..06c784c +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/soc/soc.c +@@ -0,0 +1,100 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define RK3588_DEV_RNG0_BASE 0xf0000000 ++#define RK3588_DEV_RNG0_SIZE 0x0ffff000 ++ ++const mmap_region_t plat_rk_mmap[] = { ++ MAP_REGION_FLAT(RK3588_DEV_RNG0_BASE, RK3588_DEV_RNG0_SIZE, ++ MT_DEVICE | MT_RW | MT_SECURE), ++ MAP_REGION_FLAT(DDR_SHARE_MEM, DDR_SHARE_SIZE, ++ MT_DEVICE | MT_RW | MT_NS), ++ { 0 } ++}; ++ ++/* The RockChip power domain tree descriptor */ ++const unsigned char rockchip_power_domain_tree_desc[] = { ++ /* No of root nodes */ ++ PLATFORM_SYSTEM_COUNT, ++ /* No of children for the root node */ ++ PLATFORM_CLUSTER_COUNT, ++ /* No of children for the first cluster node */ ++ PLATFORM_CLUSTER0_CORE_COUNT, ++ /* No of children for the second cluster node */ ++ PLATFORM_CLUSTER1_CORE_COUNT ++}; ++ ++void timer_hp_init(void) ++{ ++ if ((mmio_read_32(TIMER_HP_BASE + TIMER_HP_CTRL) & 0x1) != 0) ++ return; ++ ++ mmio_write_32(TIMER_HP_BASE + TIMER_HP_CTRL, 0x0); ++ dsb(); ++ mmio_write_32(TIMER_HP_BASE + TIMER_HP_LOAD_COUNT0, 0xffffffff); ++ mmio_write_32(TIMER_HP_BASE + TIMER_HP_LOAD_COUNT1, 0xffffffff); ++ mmio_write_32(TIMER_HP_BASE + TIMER_HP_INT_EN, 0); ++ dsb(); ++ mmio_write_32(TIMER_HP_BASE + TIMER_HP_CTRL, 0x1); ++} ++ ++static void system_reset_init(void) ++{ ++ /* enable wdt_ns0~4 trigger global reset and select first reset. ++ * enable tsadc trigger global reset and select first reset. ++ * enable global reset and wdt trigger pmu reset. ++ * select first reset trigger pmu reset.s ++ */ ++ mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 0xffdf); ++ ++ /* enable wdt_s, wdt_ns reset */ ++ mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(2), 0x0c000c00); ++ ++ /* reset width = 0xffff */ ++ mmio_write_32(PMU1GRF_BASE + PMU1GRF_SOC_CON(1), 0xffffffff); ++ ++ /* enable first/tsadc/wdt reset output */ ++ mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(0), 0x00070007); ++ ++ /* pmu1_grf pmu1_ioc hold */ ++ mmio_write_32(PMU1GRF_BASE + PMU1GRF_SOC_CON(7), 0x30003000); ++ ++ /* pmu1sgrf hold */ ++ mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(14), 0x00200020); ++ ++ /* select tsadc_shut_m0 ionmux*/ ++ mmio_write_32(PMU0IOC_BASE + 0x0, 0x00f00020); ++} ++ ++void plat_rockchip_soc_init(void) ++{ ++ rockchip_clock_init(); ++ secure_timer_init(); ++ timer_hp_init(); ++ system_reset_init(); ++ sgrf_init(); ++ rockchip_init_scmi_server(); ++} +diff --git a/plat/rockchip/rk3588/drivers/soc/soc.h b/plat/rockchip/rk3588/drivers/soc/soc.h +new file mode 100644 +index 0000000..9af179a +--- /dev/null ++++ b/plat/rockchip/rk3588/drivers/soc/soc.h +@@ -0,0 +1,198 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef __SOC_H__ ++#define __SOC_H__ ++ ++enum pll_id { ++ APLL_ID, ++ DPLL_ID, ++ GPLL_ID, ++ CPLL_ID, ++ NPLL_ID, ++ VPLL_ID, ++}; ++ ++enum pmu_pll_id { ++ PPLL_ID = 0, ++ HPLL_ID ++}; ++ ++enum cru_mode_con00 { ++ CLK_APLL, ++ CLK_DPLL, ++ CLK_CPLL, ++ CLK_GPLL, ++ CLK_REVSERVED, ++ CLK_NPLL, ++ CLK_VPLL, ++ CLK_USBPLL, ++}; ++ ++#define KHz 1000 ++#define MHz (1000 * KHz) ++#define OSC_HZ (24 * MHz) ++ ++/* CRU */ ++#define GLB_SRST_FST_CFG_VAL 0xfdb9 ++ ++#define CRU_PLLS_CON(pll_id, i) (0x160 + (pll_id) * 0x20 + (i) * 0x4) ++#define CRU_PLL_CON(i) ((i) * 0x4) ++#define CRU_MODE_CON0 0x280 ++#define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) ++#define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) ++#define CRU_CLKGATE_CON_CNT 78 ++#define CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) ++#define CRU_GLB_CNT_TH 0xc00 ++#define CRU_GLB_SRST_FST 0xc08 ++#define CRU_GLB_SRST_SND 0xc0c ++#define CRU_GLB_RST_CON 0xc10 ++#define CRU_GLB_RST_ST 0xc04 ++#define CRU_SDIO_CON0 0xc24 ++#define CRU_SDIO_CON1 0xc28 ++#define CRU_SDMMC_CON0 0xc30 ++#define CRU_SDMMC_CON1 0xc34 ++#define CRU_AUTOCS_CON0(id) (0xd00 + (id) * 8) ++#define CRU_AUTOCS_CON1(id) (0xd04 + (id) * 8) ++ ++#define CRU_AUTOCS_ID_CNT 74 ++ ++#define CRU_PLLCON0_M_MASK 0x3ff ++#define CRU_PLLCON0_M_SHIFT 0 ++#define CRU_PLLCON1_P_MASK 0x3f ++#define CRU_PLLCON1_P_SHIFT 0 ++#define CRU_PLLCON1_S_MASK 0x7 ++#define CRU_PLLCON1_S_SHIFT 6 ++#define CRU_PLLCON2_K_MASK 0xffff ++#define CRU_PLLCON2_K_SHIFT 0 ++#define CRU_PLLCON1_PWRDOWN BIT(13) ++#define CRU_PLLCON6_LOCK_STATUS BIT(15) ++ ++#define CRU_BIGCPU02_RST_MSK 0x30 ++#define CRU_BIGCPU13_RST_MSK 0x300 ++ ++#define PHPCRU_CLKGATE_CON 0x800 ++#define PHPCRU_CLKGATE_CON_CNT 1 ++ ++#define SECURECRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) ++#define SECURECRU_CLKGATE_CON_CNT 4 ++ ++#define PMU1CRU_CLKGATE_CON_CNT 6 ++ ++/* CENTER GRF */ ++#define CENTER_GRF_CON(i) ((i) * 4) ++ ++/* PMU1GRF */ ++#define PMU1GRF_SOC_CON(n) ((n) * 4) ++#define PMU1GRF_SOC_ST 0x60 ++#define PMU1GRF_OS_REG(n) (0x200 + ((n) * 4)) ++ ++#define PMU_MCU_HALT BIT(7) ++#define PMU_MCU_SLEEP BIT(9) ++#define PMU_MCU_DEEPSLEEP BIT(10) ++#define PMU_MCU_STOP_MSK \ ++ (PMU_MCU_HALT | PMU_MCU_SLEEP | PMU_MCU_DEEPSLEEP) ++ ++/* SYSGRF */ ++#define SYS_GRF_NOC_CON(n) (0x100 + (n) * 4) ++#define SYS_GRF_SOC_CON(n) (0x300 + (n) * 4) ++#define SYS_GRF_SOC_STATUS(n) (0x380 + (n) * 4) ++ ++#define SYS_GRF_LITTLE_CPUS_WFE 0xf ++#define SYS_GRF_CORE0_CPUS_WFE 0x30 ++#define SYS_GRF_CORE1_CPUS_WFE 0xc0 ++#define SYS_GRF_BIG_CPUS_WFE 0xf0 ++#define SYS_GRF_LITTLE_CPUS_WFI 0xf00 ++#define SYS_GRF_CORE0_CPUS_WFI 0x3000 ++#define SYS_GRF_CORE1_CPUS_WFI 0xc000 ++ ++/* pvtm */ ++#define PVTM_CON(i) (0x4 + (i) * 4) ++#define PVTM_INTEN 0x70 ++#define PVTM_INTSTS 0x74 ++#define PVTM_STATUS(i) (0x80 + (i) * 4) ++#define PVTM_CALC_CNT 0x200 ++ ++enum pvtm_con0 { ++ pvtm_start = 0, ++ pvtm_osc_en = 1, ++ pvtm_osc_sel = 2, ++ pvtm_rnd_seed_en = 5, ++}; ++ ++/* timer */ ++#define TIMER_LOAD_COUNT0 0x00 ++#define TIMER_LOAD_COUNT1 0x04 ++#define TIMER_CURRENT_VALUE0 0x08 ++#define TIMER_CURRENT_VALUE1 0x0c ++#define TIMER_CONTROL_REG 0x10 ++#define TIMER_INTSTATUS 0x18 ++ ++#define TIMER_DIS 0x0 ++#define TIMER_EN 0x1 ++ ++#define TIMER_FMODE (0x0 << 1) ++#define TIMER_RMODE (0x1 << 1) ++ ++#define STIMER0_CHN_BASE(n) (STIMER0_BASE + 0x20 * (n)) ++#define STIMER1_CHN_BASE(n) (STIMER1_BASE + 0x20 * (n)) ++ ++/* cpu timer */ ++#define TIMER_HP_REVISION 0x0 ++#define TIMER_HP_CTRL 0x4 ++#define TIMER_HP_INT_EN 0x8 ++#define TIMER_HP_T24_GCD 0xc ++#define TIMER_HP_T32_GCD 0x10 ++#define TIMER_HP_LOAD_COUNT0 0x14 ++#define TIMER_HP_LOAD_COUNT1 0x18 ++#define TIMER_HP_T24_DELAT_COUNT0 0x1c ++#define TIMER_HP_T24_DELAT_COUNT1 0x20 ++#define TIMER_HP_CURR_32K_VALUE0 0x24 ++#define TIMER_HP_CURR_32K_VALUE1 0x28 ++#define TIMER_HP_CURR_TIMER_VALUE0 0x2c ++#define TIMER_HP_CURR_TIMER_VALUE1 0x30 ++#define TIMER_HP_T24_32BEGIN0 0x34 ++#define TIMER_HP_T24_32BEGIN1 0x38 ++#define TIMER_HP_T32_24END0 0x3c ++#define TIMER_HP_T32_24END1 0x40 ++#define TIMER_HP_BEGIN_END_VALID 0x44 ++#define TIMER_HP_SYNC_REQ 0x48 ++#define TIMER_HP_INTR_STATUS 0x4c ++ ++ /* GPIO */ ++#define GPIO_SWPORT_DR_L 0x0000 ++#define GPIO_SWPORT_DR_H 0x0004 ++#define GPIO_SWPORT_DDR_L 0x0008 ++#define GPIO_SWPORT_DDR_H 0x000c ++#define GPIO_INT_EN_L 0x0010 ++#define GPIO_INT_EN_H 0x0014 ++#define GPIO_INT_MASK_L 0x0018 ++#define GPIO_INT_MASK_H 0x001c ++#define GPIO_INT_TYPE_L 0x0020 ++#define GPIO_INT_TYPE_H 0x0024 ++#define GPIO_INT_POLARITY_L 0x0028 ++#define GPIO_INT_POLARITY_H 0x002c ++#define GPIO_INT_BOTHEDGE_L 0x0030 ++#define GPIO_INT_BOTHEDGE_H 0x0034 ++#define GPIO_DEBOUNCE_L 0x0038 ++#define GPIO_DEBOUNCE_H 0x003c ++#define GPIO_DBCLK_DIV_EN_L 0x0040 ++#define GPIO_DBCLK_DIV_EN_H 0x0044 ++#define GPIO_DBCLK_DIV_CON 0x0048 ++#define GPIO_INT_STATUS 0x0050 ++#define GPIO_INT_RAWSTATUS 0x0058 ++#define GPIO_PORT_EOI_L 0x0060 ++#define GPIO_PORT_EOI_H 0x0064 ++#define GPIO_EXT_PORT 0x0070 ++#define GPIO_VER_ID 0x0078 ++ ++/* DDRGRF */ ++#define DDRGRF_CHA_CON(i) ((i) * 4) ++#define DDRGRF_CHB_CON(i) (0x30 + (i) * 4) ++ ++#define DDR_CHN_CNT 4 ++ ++#endif /* __SOC_H__ */ +diff --git a/plat/rockchip/rk3588/include/plat.ld.S b/plat/rockchip/rk3588/include/plat.ld.S +new file mode 100644 +index 0000000..e3ea9cc +--- /dev/null ++++ b/plat/rockchip/rk3588/include/plat.ld.S +@@ -0,0 +1,42 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef ROCKCHIP_PLAT_LD_S ++#define ROCKCHIP_PLAT_LD_S ++ ++MEMORY { ++ PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE ++} ++ ++SECTIONS ++{ ++ . = PMUSRAM_BASE; ++ ++ /* ++ * pmu_cpuson_entrypoint request address ++ * align 64K when resume, so put it in the ++ * start of pmusram ++ */ ++ .text_pmusram : { ++ ASSERT(. == ALIGN(64 * 1024), ++ ".pmusram.entry request 64K aligned."); ++ KEEP(*(.pmusram.entry)) ++ __bl31_pmusram_text_start = .; ++ *(.pmusram.text) ++ *(.pmusram.rodata) ++ . = ALIGN(PAGE_SIZE); ++ __bl31_pmusram_text_end = .; ++ __bl31_pmusram_data_start = .; ++ *(.pmusram.data) ++ . = ALIGN(PAGE_SIZE); ++ __bl31_pmusram_data_end = .; ++ ++ ASSERT(__bl31_pmusram_data_end <= PMUSRAM_BASE + PMUSRAM_RSIZE, ++ ".pmusram has exceeded its limit."); ++ } >PMUSRAM ++} ++ ++#endif /* ROCKCHIP_PLAT_LD_S */ +diff --git a/plat/rockchip/rk3588/include/plat_sip_calls.h b/plat/rockchip/rk3588/include/plat_sip_calls.h +new file mode 100644 +index 0000000..bc4455f +--- /dev/null ++++ b/plat/rockchip/rk3588/include/plat_sip_calls.h +@@ -0,0 +1,12 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef __PLAT_SIP_CALLS_H__ ++#define __PLAT_SIP_CALLS_H__ ++ ++#define RK_PLAT_SIP_NUM_CALLS 0 ++ ++#endif /* __PLAT_SIP_CALLS_H__ */ +diff --git a/plat/rockchip/rk3588/include/platform_def.h b/plat/rockchip/rk3588/include/platform_def.h +new file mode 100644 +index 0000000..5946af0 +--- /dev/null ++++ b/plat/rockchip/rk3588/include/platform_def.h +@@ -0,0 +1,119 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef __PLATFORM_DEF_H__ ++#define __PLATFORM_DEF_H__ ++ ++#include ++#include ++ ++#include ++ ++#define DEBUG_XLAT_TABLE 0 ++ ++/******************************************************************************* ++ * Platform binary types for linking ++ ******************************************************************************/ ++#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" ++#define PLATFORM_LINKER_ARCH aarch64 ++ ++/******************************************************************************* ++ * Generic platform constants ++ ******************************************************************************/ ++ ++/* Size of cacheable stacks */ ++#if DEBUG_XLAT_TABLE ++#define PLATFORM_STACK_SIZE 0x800 ++#elif IMAGE_BL1 ++#define PLATFORM_STACK_SIZE 0x440 ++#elif IMAGE_BL2 ++#define PLATFORM_STACK_SIZE 0x400 ++#elif IMAGE_BL31 ++#define PLATFORM_STACK_SIZE 0x800 ++#elif IMAGE_BL32 ++#define PLATFORM_STACK_SIZE 0x440 ++#endif ++ ++#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" ++ ++#define PLATFORM_SYSTEM_COUNT 1 ++#define PLATFORM_CLUSTER_COUNT 1 ++#define PLATFORM_CLUSTER0_CORE_COUNT 8 ++#define PLATFORM_CLUSTER1_CORE_COUNT 0 ++#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ ++ PLATFORM_CLUSTER0_CORE_COUNT) ++ ++#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ ++ PLATFORM_CLUSTER_COUNT + \ ++ PLATFORM_CORE_COUNT) ++ ++#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 ++ ++#define PLAT_RK_CLST_TO_CPUID_SHIFT 8 ++ ++/* ++ * This macro defines the deepest retention state possible. A higher state ++ * id will represent an invalid or a power down state. ++ */ ++#define PLAT_MAX_RET_STATE 1 ++ ++/* ++ * This macro defines the deepest power down states possible. Any state ID ++ * higher than this is invalid. ++ */ ++#define PLAT_MAX_OFF_STATE 2 ++/******************************************************************************* ++ * Platform memory map related constants ++ ******************************************************************************/ ++/* TF txet, ro, rw, Size: 512KB */ ++#define TZRAM_BASE (0x0) ++#define TZRAM_SIZE (0x100000) ++ ++/******************************************************************************* ++ * BL31 specific defines. ++ ******************************************************************************/ ++/* ++ * Put BL3-1 at the top of the Trusted RAM ++ */ ++#define BL31_BASE (TZRAM_BASE + 0x40000) ++#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) ++ ++/******************************************************************************* ++ * Platform specific page table and MMU setup constants ++ ******************************************************************************/ ++#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) ++#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) ++ ++#define ADDR_SPACE_SIZE (1ULL << 32) ++#define MAX_XLAT_TABLES 18 ++#define MAX_MMAP_REGIONS 27 ++ ++/******************************************************************************* ++ * Declarations and constants to access the mailboxes safely. Each mailbox is ++ * aligned on the biggest cache line size in the platform. This is known only ++ * to the platform as it might have a combination of integrated and external ++ * caches. Such alignment ensures that two maiboxes do not sit on the same cache ++ * line at any cache level. They could belong to different cpus/clusters & ++ * get written while being protected by different locks causing corruption of ++ * a valid mailbox address. ++ ******************************************************************************/ ++#define CACHE_WRITEBACK_SHIFT 6 ++#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) ++ ++/* ++ * Define GICD and GICC and GICR base ++ */ ++#define PLAT_RK_GICD_BASE PLAT_GICD_BASE ++#define PLAT_RK_GICC_BASE PLAT_GICC_BASE ++#define PLAT_RK_GICR_BASE PLAT_GICR_BASE ++ ++#define PLAT_RK_UART_BASE RK_DBG_UART_BASE ++#define PLAT_RK_UART_CLOCK RK_DBG_UART_CLOCK ++#define PLAT_RK_UART_BAUDRATE RK_DBG_UART_BAUDRATE ++ ++#define PLAT_RK_PRIMARY_CPU 0x0 ++ ++#endif /* __PLATFORM_DEF_H__ */ +diff --git a/plat/rockchip/rk3588/plat_sip_calls.c b/plat/rockchip/rk3588/plat_sip_calls.c +new file mode 100644 +index 0000000..496e8d7 +--- /dev/null ++++ b/plat/rockchip/rk3588/plat_sip_calls.c +@@ -0,0 +1,32 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid, ++ u_register_t x1, ++ u_register_t x2, ++ u_register_t x3, ++ u_register_t x4, ++ void *cookie, ++ void *handle, ++ u_register_t flags) ++{ ++ switch (smc_fid) { ++ case RK_SIP_SCMI_AGENT0: ++ scmi_smt_fastcall_smc_entry(0); ++ SMC_RET1(handle, 0); ++ ++ default: ++ ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); ++ SMC_RET1(handle, SMC_UNK); ++ } ++} +diff --git a/plat/rockchip/rk3588/platform.mk b/plat/rockchip/rk3588/platform.mk +new file mode 100644 +index 0000000..07eda40 +--- /dev/null ++++ b/plat/rockchip/rk3588/platform.mk +@@ -0,0 +1,98 @@ ++# ++# Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++# ++# SPDX-License-Identifier: BSD-3-Clause ++# ++ ++RK_PLAT := plat/rockchip ++RK_PLAT_SOC := ${RK_PLAT}/${PLAT} ++RK_PLAT_COMMON := ${RK_PLAT}/common ++ ++DISABLE_BIN_GENERATION := 1 ++include lib/libfdt/libfdt.mk ++include lib/xlat_tables_v2/xlat_tables.mk ++ ++# GIC-600 configuration ++GICV3_IMPL := GIC600 ++GICV3_SUPPORT_GIC600 := 1 ++ ++# Include GICv3 driver files ++include drivers/arm/gic/v3/gicv3.mk ++ ++PLAT_INCLUDES := -Iinclude/plat/common \ ++ -Idrivers/arm/gic/v3/ \ ++ -Idrivers/scmi-msg/ \ ++ -I${RK_PLAT_COMMON}/ \ ++ -I${RK_PLAT_COMMON}/drivers/pmu/ \ ++ -I${RK_PLAT_COMMON}/drivers/parameter/ \ ++ -I${RK_PLAT_COMMON}/include/ \ ++ -I${RK_PLAT_COMMON}/pmusram/ \ ++ -I${RK_PLAT_COMMON}/scmi/ \ ++ -I${RK_PLAT_SOC}/ \ ++ -I${RK_PLAT_SOC}/drivers/pmu/ \ ++ -I${RK_PLAT_SOC}/drivers/scmi/ \ ++ -I${RK_PLAT_SOC}/drivers/secure/ \ ++ -I${RK_PLAT_SOC}/drivers/soc/ \ ++ -I${RK_PLAT_SOC}/include/ ++ ++RK_GIC_SOURCES := ${GICV3_SOURCES} \ ++ plat/common/plat_gicv3.c \ ++ ${RK_PLAT}/common/rockchip_gicv3.c ++ ++PLAT_BL_COMMON_SOURCES := ${XLAT_TABLES_LIB_SRCS} \ ++ common/desc_image_load.c \ ++ plat/common/aarch64/crash_console_helpers.S \ ++ lib/bl_aux_params/bl_aux_params.c \ ++ plat/common/plat_psci_common.c ++ ++ifneq (${ENABLE_STACK_PROTECTOR},0) ++PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c ++endif ++ ++BL31_SOURCES += ${RK_GIC_SOURCES} \ ++ drivers/ti/uart/aarch64/16550_console.S \ ++ drivers/delay_timer/delay_timer.c \ ++ drivers/delay_timer/generic_delay_timer.c \ ++ drivers/scmi-msg/base.c \ ++ drivers/scmi-msg/clock.c \ ++ drivers/scmi-msg/entry.c \ ++ drivers/scmi-msg/reset_domain.c \ ++ drivers/scmi-msg/smt.c \ ++ lib/cpus/aarch64/cortex_a55.S \ ++ lib/cpus/aarch64/cortex_a76.S \ ++ ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ ++ ${RK_PLAT_COMMON}/aarch64/platform_common.c \ ++ ${RK_PLAT_COMMON}/bl31_plat_setup.c \ ++ ${RK_PLAT_COMMON}/plat_pm.c \ ++ ${RK_PLAT_COMMON}/plat_pm_helpers.c \ ++ ${RK_PLAT_COMMON}/plat_topology.c \ ++ ${RK_PLAT_COMMON}/params_setup.c \ ++ ${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \ ++ ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ ++ ${RK_PLAT_COMMON}/scmi/scmi.c \ ++ ${RK_PLAT_COMMON}/scmi/scmi_clock.c \ ++ ${RK_PLAT_COMMON}/scmi/scmi_rstd.c \ ++ ${RK_PLAT_SOC}/plat_sip_calls.c \ ++ ${RK_PLAT_SOC}/drivers/secure/secure.c \ ++ ${RK_PLAT_SOC}/drivers/soc/soc.c \ ++ ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ ++ ${RK_PLAT_SOC}/drivers/pmu/pm_pd_regs.c \ ++ ${RK_PLAT_SOC}/drivers/scmi/rk3588_clk.c \ ++ ${RK_PLAT_SOC}/drivers/scmi/rk3588_rstd.c ++ ++CTX_INCLUDE_AARCH32_REGS := 0 ++ENABLE_PLAT_COMPAT := 0 ++MULTI_CONSOLE_API := 1 ++ERRATA_A55_1530923 := 1 ++ ++# System coherency is managed in hardware ++HW_ASSISTED_COHERENCY := 1 ++ ++# When building for systems with hardware-assisted coherency, there's no need to ++# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. ++USE_COHERENT_MEM := 0 ++ ++ENABLE_SPE_FOR_LOWER_ELS := 0 ++ ++$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) ++$(eval $(call add_define,PLAT_SKIP_DFS_TLB_DCACHE_MAINTENANCE)) +diff --git a/plat/rockchip/rk3588/rk3588_def.h b/plat/rockchip/rk3588/rk3588_def.h +new file mode 100644 +index 0000000..75b685a +--- /dev/null ++++ b/plat/rockchip/rk3588/rk3588_def.h +@@ -0,0 +1,221 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef __PLAT_DEF_H__ ++#define __PLAT_DEF_H__ ++ ++#define SIZE_K(n) ((n) * 1024) ++ ++#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) ++ ++/* Special value used to verify platform parameters from BL2 to BL3-1 */ ++#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL ++ ++#define UMCTL0_BASE 0xf7000000 ++#define UMCTL1_BASE 0xf8000000 ++#define UMCTL2_BASE 0xf9000000 ++#define UMCTL3_BASE 0xfa000000 ++ ++#define GIC600_BASE 0xfe600000 ++#define GIC600_SIZE SIZE_K(64) ++ ++#define DAPLITE_BASE 0xfd100000 ++#define PMU0SGRF_BASE 0xfd580000 ++#define PMU1SGRF_BASE 0xfd582000 ++#define BUSSGRF_BASE 0xfd586000 ++#define DSUSGRF_BASE 0xfd587000 ++#define PMU0GRF_BASE 0xfd588000 ++#define PMU1GRF_BASE 0xfd58a000 ++ ++#define SYSGRF_BASE 0xfd58c000 ++#define BIGCORE0GRF_BASE 0xfd590000 ++#define BIGCORE1GRF_BASE 0xfd592000 ++#define LITCOREGRF_BASE 0xfd594000 ++#define DSUGRF_BASE 0xfd598000 ++#define DDR01GRF_BASE 0xfd59c000 ++#define DDR23GRF_BASE 0xfd59d000 ++#define CENTERGRF_BASE 0xfd59e000 ++#define GPUGRF_BASE 0xfd5a0000 ++#define NPUGRF_BASE 0xfd5a2000 ++#define USBGRF_BASE 0xfd5ac000 ++#define PHPGRF_BASE 0xfd5b0000 ++#define PCIE3PHYGRF_BASE 0xfd5b8000 ++#define USB2PHY0_GRF_BASE 0xfd5d0000 ++#define USB2PHY1_GRF_BASE 0xfd5d4000 ++#define USB2PHY2_GRF_BASE 0xfd5d8000 ++#define USB2PHY3_GRF_BASE 0xfd5dc000 ++ ++#define PMU0IOC_BASE 0xfd5f0000 ++#define PMU1IOC_BASE 0xfd5f4000 ++#define BUSIOC_BASE 0xfd5f8000 ++#define VCCIO1_4_IOC_BASE 0xfd5f9000 ++#define VCCIO3_5_IOC_BASE 0xfd5fa000 ++#define VCCIO2_IOC_BASE 0xfd5fb000 ++#define VCCIO6_IOC_BASE 0xfd5fc000 ++ ++#define SRAM_BASE 0xff000000 ++#define PMUSRAM_BASE 0xff100000 ++#define PMUSRAM_SIZE SIZE_K(128) ++#define PMUSRAM_RSIZE SIZE_K(64) ++ ++#define CRU_BASE 0xfd7c0000 ++#define PHP_CRU_BASE 0xfd7c8000 ++#define SCRU_BASE 0xfd7d0000 ++#define BUSSCRU_BASE 0xfd7d8000 ++#define PMU1SCRU_BASE 0xfd7e0000 ++#define PMU1CRU_BASE 0xfd7f0000 ++ ++#define DDR0CRU_BASE 0xfd800000 ++#define DDR1CRU_BASE 0xfd804000 ++#define DDR2CRU_BASE 0xfd808000 ++#define DDR3CRU_BASE 0xfd80c000 ++ ++#define BIGCORE0CRU_BASE 0xfd810000 ++#define BIGCORE1CRU_BASE 0xfd812000 ++#define LITCRU_BASE 0xfd814000 ++#define DSUCRU_BASE 0xfd818000 ++ ++#define I2C0_BASE 0xfd880000 ++#define UART0_BASE 0xfd890000 ++#define GPIO0_BASE 0xfd8a0000 ++#define PWM0_BASE 0xfd8b0000 ++#define PMUPVTM_BASE 0xfd8c0000 ++#define TIMER_HP_BASE 0xfd8c8000 ++#define PMU0_BASE 0xfd8d0000 ++#define PMU1_BASE 0xfd8d4000 ++#define PMU2_BASE 0xfd8d8000 ++#define PMU_BASE PMU0_BASE ++#define PMUWDT_BASE 0xfd8e0000 ++#define PMUTIMER_BASE 0xfd8f0000 ++#define OSC_CHK_BASE 0xfd9b0000 ++#define VOP_BASE 0xfdd90000 ++#define HDMIRX_BASE 0xfdee0000 ++ ++#define MSCH0_BASE 0xfe000000 ++#define MSCH1_BASE 0xfe002000 ++#define MSCH2_BASE 0xfe004000 ++#define MSCH3_BASE 0xfe006000 ++#define FIREWALL_DSU_BASE 0xfe010000 ++#define FIREWALL_DDR_BASE 0xfe030000 ++#define FIREWALL_SYSMEM_BASE 0xfe038000 ++#define DDRPHY0_BASE 0xfe0c0000 ++#define DDRPHY1_BASE 0xfe0d0000 ++#define DDRPHY2_BASE 0xfe0e0000 ++#define DDRPHY3_BASE 0xfe0f0000 ++#define TIMER_DDR_BASE 0xfe118000 ++#define KEYLADDER_BASE 0xfe380000 ++#define CRYPTO_S_BASE 0xfe390000 ++#define OTP_S_BASE 0xfe3a0000 ++#define DCF_BASE 0xfe3c0000 ++#define STIMER0_BASE 0xfe3d0000 ++#define WDT_S_BASE 0xfe3e0000 ++#define CRYPTO_S_BY_KEYLAD_BASE 0xfe420000 ++#define NSTIMER0_BASE 0xfeae0000 ++#define NSTIMER1_BASE 0xfeae8000 ++#define WDT_NS_BASE 0xfeaf0000 ++ ++#define UART1_BASE 0xfeb40000 ++#define UART2_BASE 0xfeb50000 ++#define UART3_BASE 0xfeb60000 ++#define UART4_BASE 0xfeb70000 ++#define UART5_BASE 0xfeb80000 ++#define UART6_BASE 0xfeb90000 ++#define UART7_BASE 0xfeba0000 ++#define UART8_BASE 0xfebb0000 ++#define UART9_BASE 0xfebc0000 ++ ++#define GPIO1_BASE 0xfec20000 ++#define GPIO2_BASE 0xfec30000 ++#define GPIO3_BASE 0xfec40000 ++#define GPIO4_BASE 0xfec50000 ++ ++#define MAILBOX1_BASE 0xfec70000 ++#define OTP_NS_BASE 0xfecc0000 ++#define INTMUX0_DDR_BASE 0Xfecf8000 ++#define INTMUX1_DDR_BASE 0Xfecfc000 ++#define STIMER1_BASE 0xfed30000 ++ ++/************************************************************************** ++ * sys sram allocation ++ **************************************************************************/ ++#define SRAM_ENTRY_BASE SRAM_BASE ++#define SRAM_PMUM0_SHMEM_BASE (SRAM_ENTRY_BASE + SIZE_K(3)) ++#define SRAM_LD_BASE (SRAM_ENTRY_BASE + SIZE_K(4)) ++#define SRAM_LD_SIZE SIZE_K(64) ++ ++#define SRAM_LD_SP (SRAM_LD_BASE + SRAM_LD_SIZE -\ ++ 128) ++ ++/************************************************************************** ++ * share mem region allocation: 1M~2M ++ **************************************************************************/ ++#define DDR_SHARE_MEM SIZE_K(1024) ++#define DDR_SHARE_SIZE SIZE_K(64) ++ ++#define SHARE_MEM_BASE DDR_SHARE_MEM ++#define SHARE_MEM_PAGE_NUM 15 ++#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) ++ ++#define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE) ++#define SCMI_SHARE_MEM_SIZE SIZE_K(4) ++ ++/************************************************************************** ++ * UART related constants ++ **************************************************************************/ ++#define RK_DBG_UART_BASE UART2_BASE ++#define RK_DBG_UART_BAUDRATE 1500000 ++#define RK_DBG_UART_CLOCK 24000000 ++ ++/****************************************************************************** ++ * System counter frequency related constants ++ ******************************************************************************/ ++#define SYS_COUNTER_FREQ_IN_TICKS 24000000 ++#define SYS_COUNTER_FREQ_IN_MHZ 24 ++ ++/****************************************************************************** ++ * GIC-600 & interrupt handling related constants ++ ******************************************************************************/ ++ ++/* Base rk_platform compatible GIC memory map */ ++#define PLAT_GICD_BASE GIC600_BASE ++#define PLAT_GICC_BASE 0 ++#define PLAT_GICR_BASE (GIC600_BASE + 0x80000) ++#define PLAT_GICITS0_BASE 0xfe640000 ++#define PLAT_GICITS1_BASE 0xfe660000 ++ ++/****************************************************************************** ++ * sgi, ppi ++ ******************************************************************************/ ++#define RK_IRQ_SEC_SGI_0 8 ++#define RK_IRQ_SEC_SGI_1 9 ++#define RK_IRQ_SEC_SGI_2 10 ++#define RK_IRQ_SEC_SGI_3 11 ++#define RK_IRQ_SEC_SGI_4 12 ++#define RK_IRQ_SEC_SGI_5 13 ++#define RK_IRQ_SEC_SGI_6 14 ++#define RK_IRQ_SEC_SGI_7 15 ++#define RK_IRQ_SEC_PHY_TIMER 29 ++ ++/* ++ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 ++ * terminology. On a GICv2 system or mode, the lists will be merged and treated ++ * as Group 0 interrupts. ++ */ ++ ++#define PLAT_RK_GICV3_G1S_IRQS \ ++ INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ ++ INTR_GROUP1S, GIC_INTR_CFG_LEVEL) ++ ++#define PLAT_RK_GICV3_G0_IRQS \ ++ INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ ++ INTR_GROUP0, GIC_INTR_CFG_LEVEL) ++ ++/****************************************************************************** ++ * pm reg region memory ++ ******************************************************************************/ ++#define ROCKCHIP_PM_REG_REGION_MEM_SIZE SIZE_K(4) ++ ++#endif /* __PLAT_DEF_H__ */ diff --git a/atf.patches/feat-rockchip-support-SCMI-for-clock-reset-domain.patch b/atf.patches/feat-rockchip-support-SCMI-for-clock-reset-domain.patch new file mode 100644 index 0000000..06da3bf --- /dev/null +++ b/atf.patches/feat-rockchip-support-SCMI-for-clock-reset-domain.patch @@ -0,0 +1,465 @@ +From 3bd5d90889173031e1a4177835225e3f9ffd6e49 Mon Sep 17 00:00:00 2001 +From: XiaoDong Huang +Date: Sun, 25 Jun 2023 17:38:13 +0800 +Subject: [PATCH] feat(rockchip): support SCMI for clock/reset domain + +Signed-off-by: XiaoDong Huang +Change-Id: I5b983877a5b4e8acababbf7e0a3e2725e6479e08 +--- + +diff --git a/plat/rockchip/common/include/rockchip_sip_svc.h b/plat/rockchip/common/include/rockchip_sip_svc.h +index 340d653..8836f9b 100644 +--- a/plat/rockchip/common/include/rockchip_sip_svc.h ++++ b/plat/rockchip/common/include/rockchip_sip_svc.h +@@ -11,6 +11,7 @@ + #define SIP_SVC_CALL_COUNT 0x8200ff00 + #define SIP_SVC_UID 0x8200ff01 + #define SIP_SVC_VERSION 0x8200ff03 ++#define RK_SIP_SCMI_AGENT0 0x82000010 + + /* rockchip SiP Service Calls version numbers */ + #define RK_SIP_SVC_VERSION_MAJOR 0x0 +diff --git a/plat/rockchip/common/scmi/scmi.c b/plat/rockchip/common/scmi/scmi.c +new file mode 100644 +index 0000000..23ea991 +--- /dev/null ++++ b/plat/rockchip/common/scmi/scmi.c +@@ -0,0 +1,88 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define MAX_PROTOCOL_IN_LIST 8U ++ ++static const char vendor[] = "rockchip"; ++static const char sub_vendor[] = ""; ++ ++#pragma weak rockchip_scmi_protocol_table ++ ++const uint8_t rockchip_scmi_protocol_table[1][MAX_PROTOCOL_IN_LIST] = { ++ { SCMI_PROTOCOL_ID_CLOCK, ++ SCMI_PROTOCOL_ID_RESET_DOMAIN, ++ 0 ++ } ++}; ++ ++const char *plat_scmi_vendor_name(void) ++{ ++ return vendor; ++} ++ ++const char *plat_scmi_sub_vendor_name(void) ++{ ++ return sub_vendor; ++} ++ ++size_t plat_scmi_protocol_count(void) ++{ ++ unsigned int count = 0U; ++ const uint8_t *protocol_list = rockchip_scmi_protocol_table[0]; ++ ++ while (protocol_list[count]) ++ count++; ++ ++ return count; ++} ++ ++const uint8_t *plat_scmi_protocol_list(unsigned int agent_id) ++{ ++ assert(agent_id < ARRAY_SIZE(rockchip_scmi_protocol_table)); ++ ++ return rockchip_scmi_protocol_table[agent_id]; ++} ++ ++static struct scmi_msg_channel scmi_channel[] = { ++ [0] = { ++ .shm_addr = SMT_BUFFER0_BASE, ++ .shm_size = SMT_BUF_SLOT_SIZE, ++ }, ++ ++#ifdef SMT_BUFFER1_BASE ++ [1] = { ++ .shm_addr = SMT_BUFFER1_BASE, ++ .shm_size = SMT_BUF_SLOT_SIZE, ++ }, ++#endif ++}; ++ ++struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) ++{ ++ assert(agent_id < ARRAY_SIZE(scmi_channel)); ++ ++ return &scmi_channel[agent_id]; ++} ++ ++#pragma weak rockchip_init_scmi_server ++ ++void rockchip_init_scmi_server(void) ++{ ++ size_t i; ++ ++ for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++) ++ scmi_smt_init_agent_channel(&scmi_channel[i]); ++} +diff --git a/plat/rockchip/common/scmi/scmi_clock.c b/plat/rockchip/common/scmi/scmi_clock.c +new file mode 100644 +index 0000000..4921d49 +--- /dev/null ++++ b/plat/rockchip/common/scmi/scmi_clock.c +@@ -0,0 +1,157 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include "scmi_clock.h" ++ ++#pragma weak rockchip_scmi_clock_count ++#pragma weak rockchip_scmi_get_clock ++ ++size_t rockchip_scmi_clock_count(unsigned int agent_id __unused) ++{ ++ return 0; ++} ++ ++rk_scmi_clock_t *rockchip_scmi_get_clock(uint32_t agent_id __unused, ++ uint32_t scmi_id __unused) ++{ ++ return NULL; ++} ++ ++size_t plat_scmi_clock_count(unsigned int agent_id) ++{ ++ return rockchip_scmi_clock_count(agent_id); ++} ++ ++const char *plat_scmi_clock_get_name(unsigned int agent_id, ++ unsigned int scmi_id) ++{ ++ rk_scmi_clock_t *clock; ++ ++ clock = rockchip_scmi_get_clock(agent_id, scmi_id); ++ if (clock == 0) ++ return NULL; ++ ++ return clock->name; ++} ++ ++int32_t plat_scmi_clock_rates_array(unsigned int agent_id, ++ unsigned int scmi_id, ++ unsigned long *rates, ++ size_t *nb_elts, ++ uint32_t start_idx) ++{ ++ uint32_t i; ++ unsigned long *rate_table; ++ rk_scmi_clock_t *clock; ++ ++ clock = rockchip_scmi_get_clock(agent_id, scmi_id); ++ if (clock == 0) ++ return SCMI_NOT_FOUND; ++ ++ rate_table = clock->rate_table; ++ if (rate_table == 0) ++ return SCMI_NOT_SUPPORTED; ++ ++ if (rates == 0) { ++ *nb_elts = clock->rate_cnt; ++ goto out; ++ } ++ ++ if (start_idx + *nb_elts > clock->rate_cnt) ++ return SCMI_OUT_OF_RANGE; ++ ++ for (i = 0; i < *nb_elts; i++) ++ rates[i] = rate_table[start_idx + i]; ++ ++out: ++ return SCMI_SUCCESS; ++} ++ ++int32_t plat_scmi_clock_rates_by_step(unsigned int agent_id __unused, ++ unsigned int scmi_id __unused, ++ unsigned long *steps __unused) ++{ ++ return SCMI_NOT_SUPPORTED; ++} ++ ++unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, ++ unsigned int scmi_id) ++{ ++ rk_scmi_clock_t *clock; ++ unsigned long rate = 0; ++ ++ clock = rockchip_scmi_get_clock(agent_id, scmi_id); ++ if (clock == 0) ++ return 0; ++ ++ if (clock->clk_ops && clock->clk_ops->get_rate) ++ rate = clock->clk_ops->get_rate(clock); ++ ++ /* return cur_rate if no get_rate ops or get_rate return 0 */ ++ if (rate == 0) ++ rate = clock->cur_rate; ++ ++ return rate; ++} ++ ++int32_t plat_scmi_clock_set_rate(unsigned int agent_id, ++ unsigned int scmi_id, ++ unsigned long rate) ++{ ++ rk_scmi_clock_t *clock; ++ int32_t status = 0; ++ ++ clock = rockchip_scmi_get_clock(agent_id, scmi_id); ++ if (clock == 0) ++ return SCMI_NOT_FOUND; ++ ++ if (clock->clk_ops && clock->clk_ops->set_rate) { ++ status = clock->clk_ops->set_rate(clock, rate); ++ if (status == SCMI_SUCCESS) ++ clock->cur_rate = rate; ++ } else { ++ status = SCMI_NOT_SUPPORTED; ++ } ++ ++ return status; ++} ++ ++int32_t plat_scmi_clock_get_state(unsigned int agent_id, ++ unsigned int scmi_id) ++{ ++ rk_scmi_clock_t *clock; ++ ++ clock = rockchip_scmi_get_clock(agent_id, scmi_id); ++ if (clock == 0) ++ return 0; ++ ++ return clock->enable; ++} ++ ++int32_t plat_scmi_clock_set_state(unsigned int agent_id, ++ unsigned int scmi_id, ++ bool enable_not_disable) ++{ ++ rk_scmi_clock_t *clock; ++ int32_t status = 0; ++ ++ clock = rockchip_scmi_get_clock(agent_id, scmi_id); ++ if (clock == 0) ++ return SCMI_NOT_FOUND; ++ ++ if (clock->clk_ops && clock->clk_ops->set_status) { ++ status = clock->clk_ops->set_status(clock, enable_not_disable); ++ if (status == SCMI_SUCCESS) ++ clock->enable = enable_not_disable; ++ } else { ++ status = SCMI_NOT_SUPPORTED; ++ } ++ ++ return status; ++} +diff --git a/plat/rockchip/common/scmi/scmi_clock.h b/plat/rockchip/common/scmi/scmi_clock.h +new file mode 100644 +index 0000000..e640fe1 +--- /dev/null ++++ b/plat/rockchip/common/scmi/scmi_clock.h +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef RK_SCMI_CLOCK_H ++#define RK_SCMI_CLOCK_H ++ ++#include ++ ++#include ++ ++struct rk_scmi_clock; ++ ++struct rk_clk_ops { ++ unsigned long (*get_rate)(struct rk_scmi_clock *clock); ++ int (*set_rate)(struct rk_scmi_clock *clock, unsigned long rate); ++ int (*set_status)(struct rk_scmi_clock *clock, bool status); ++}; ++ ++typedef struct rk_scmi_clock { ++ char name[SCMI_CLOCK_NAME_LENGTH_MAX]; ++ uint8_t enable; ++ int8_t is_security; ++ uint32_t id; ++ uint32_t rate_cnt; ++ uint64_t cur_rate; ++ uint32_t enable_count; ++ const struct rk_clk_ops *clk_ops; ++ unsigned long *rate_table; ++} rk_scmi_clock_t; ++ ++/* ++ * Return number of clock controllers for an agent ++ * @agent_id: SCMI agent ID ++ * Return number of clock controllers ++ */ ++size_t rockchip_scmi_clock_count(unsigned int agent_id); ++ ++/* ++ * Get rk_scmi_clock_t point ++ * @agent_id: SCMI agent ID ++ * @scmi_id: SCMI clock ID ++ * Return a rk_scmi_clock_t point ++ */ ++rk_scmi_clock_t *rockchip_scmi_get_clock(uint32_t agent_id, ++ uint32_t scmi_id); ++ ++#endif /* RK_SCMI_CLOCK_H */ +diff --git a/plat/rockchip/common/scmi/scmi_rstd.c b/plat/rockchip/common/scmi/scmi_rstd.c +new file mode 100644 +index 0000000..404d85e +--- /dev/null ++++ b/plat/rockchip/common/scmi/scmi_rstd.c +@@ -0,0 +1,74 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include "scmi_rstd.h" ++ ++#pragma weak rockchip_scmi_rstd_count ++#pragma weak rockchip_scmi_get_rstd ++ ++size_t rockchip_scmi_rstd_count(unsigned int agent_id __unused) ++{ ++ return 0U; ++} ++ ++rk_scmi_rstd_t *rockchip_scmi_get_rstd(unsigned int agent_id __unused, ++ unsigned int scmi_id __unused) ++{ ++ return NULL; ++} ++ ++size_t plat_scmi_rstd_count(unsigned int agent_id) ++{ ++ return rockchip_scmi_rstd_count(agent_id); ++} ++ ++const char *plat_scmi_rstd_get_name(unsigned int agent_id, ++ unsigned int scmi_id) ++{ ++ rk_scmi_rstd_t *rstd; ++ ++ rstd = rockchip_scmi_get_rstd(agent_id, scmi_id); ++ if (rstd == 0) ++ return NULL; ++ ++ return rstd->name; ++} ++ ++int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, ++ unsigned int scmi_id, ++ unsigned int state) ++{ ++ rk_scmi_rstd_t *rstd; ++ ++ rstd = rockchip_scmi_get_rstd(agent_id, scmi_id); ++ if (rstd == 0) ++ return SCMI_NOT_FOUND; ++ ++ if ((rstd->rstd_ops && rstd->rstd_ops->reset_auto) != 0) ++ return rstd->rstd_ops->reset_auto(rstd, state); ++ else ++ return SCMI_NOT_SUPPORTED; ++} ++ ++int32_t plat_scmi_rstd_set_state(unsigned int agent_id, ++ unsigned int scmi_id, ++ bool assert_not_deassert) ++{ ++ rk_scmi_rstd_t *rstd; ++ ++ rstd = rockchip_scmi_get_rstd(agent_id, scmi_id); ++ if (rstd == 0) ++ return SCMI_NOT_FOUND; ++ ++ if ((rstd->rstd_ops && rstd->rstd_ops->reset_explicit) != 0) ++ return rstd->rstd_ops->reset_explicit(rstd, ++ assert_not_deassert); ++ else ++ return SCMI_NOT_SUPPORTED; ++} +diff --git a/plat/rockchip/common/scmi/scmi_rstd.h b/plat/rockchip/common/scmi/scmi_rstd.h +new file mode 100644 +index 0000000..1af5881 +--- /dev/null ++++ b/plat/rockchip/common/scmi/scmi_rstd.h +@@ -0,0 +1,45 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef RK_SCMI_RESET_DOMAIN_H ++#define RK_SCMI_RESET_DOMAIN_H ++ ++#include ++ ++#include ++ ++struct rk_scmi_rstd; ++ ++struct rk_scmi_rstd_ops { ++ int (*reset_auto)(struct rk_scmi_rstd *rstd, uint32_t state); ++ int (*reset_explicit)(struct rk_scmi_rstd *rstd, bool assert_not_deassert); ++}; ++ ++typedef struct rk_scmi_rstd { ++ char name[SCMI_RESET_DOMAIN_ATTR_NAME_SZ]; ++ uint32_t id; ++ uint32_t attribute; ++ uint32_t latency; ++ struct rk_scmi_rstd_ops *rstd_ops; ++} rk_scmi_rstd_t; ++ ++/* ++ * Return number of reset domain for an agent ++ * @agent_id: SCMI agent ID ++ * Return number of reset domain ++ */ ++size_t rockchip_scmi_rstd_count(unsigned int agent_id); ++ ++/* ++ * Get rk_scmi_rstd_t point ++ * @agent_id: SCMI agent ID ++ * @scmi_id: SCMI rstd ID ++ * Return a rk_scmi_rstd_t point ++ */ ++rk_scmi_rstd_t *rockchip_scmi_get_rstd(unsigned int agent_id, ++ unsigned int scmi_id); ++ ++#endif /* RK_SCMI_RESET_DOMAIN_H */ diff --git a/atf.patches/rk3588-enable-crypto-function.patch b/atf.patches/rk3588-enable-crypto-function.patch new file mode 100644 index 0000000..62097d9 --- /dev/null +++ b/atf.patches/rk3588-enable-crypto-function.patch @@ -0,0 +1,139 @@ +From c805c14c1026b3ae5445e211c2101c60cd76ad0e Mon Sep 17 00:00:00 2001 +From: XiaoDong Huang +Date: Mon, 17 Jun 2024 10:55:27 +0800 +Subject: [PATCH] feat(rk3588): enable crypto function + +Signed-off-by: XiaoDong Huang +Change-Id: Ifee2eab55d9c13cef5f15926fb80016845e2a66d +--- + +diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S +index dfb14e9..6d1e11e 100644 +--- a/bl31/aarch64/bl31_entrypoint.S ++++ b/bl31/aarch64/bl31_entrypoint.S +@@ -16,6 +16,11 @@ + .globl bl31_entrypoint + .globl bl31_warm_entrypoint + ++#ifdef PLAT_RK_BL31_ENTRYPOINT ++ .globl plat_rockchip_bl31_entrypoint ++ .globl plat_rockchip_bl31_entrypoint_set_sp ++#endif ++ + /* ----------------------------------------------------- + * bl31_entrypoint() is the cold boot entrypoint, + * executed only by the primary cpu. +@@ -23,6 +28,10 @@ + */ + + func bl31_entrypoint ++#ifdef PLAT_RK_BL31_ENTRYPOINT ++ bl plat_rockchip_bl31_entrypoint_set_sp ++ bl plat_rockchip_bl31_entrypoint ++#endif + /* --------------------------------------------------------------- + * Stash the previous bootloader arguments x0 - x3 for later use. + * --------------------------------------------------------------- +diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c +index 83d6cad..a7c1c47 100644 +--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c ++++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c +@@ -136,6 +136,22 @@ + + static __pmusramfunc void ddr_resume(void) + { ++ /* check the crypto function had been enabled or not */ ++ if (mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) { ++ /* enable the crypto function */ ++ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4)); ++ dsb(); ++ isb(); ++ ++ __asm__ volatile ("mov x0, #3\n" ++ "dsb sy\n" ++ "msr rmr_el3, x0\n" ++ "1:\n" ++ "isb\n" ++ "wfi\n" ++ "b 1b\n"); ++ } ++ + dsu_restore_early(); + } + +@@ -1437,3 +1453,66 @@ + + pm_reg_rgns_init(); + } ++ ++void bl31_entrypoint(void); ++ ++static uint64_t boot_cpu_save[4]; ++ ++void plat_rockchip_bl31_entrypoint_set_sp(uint64_t reg0, uint64_t reg1, ++ uint64_t reg2, uint64_t reg3) ++{ ++ __asm__ volatile("mov x10, %0\n" : : "r" (reg0) : ); ++ ++ reg0 = PSRAM_SP_TOP; ++ __asm__ volatile("mov sp, %0\n" : : "r" (reg0) : ); ++ ++ __asm__ volatile("mov %0, x10\n" : "=r" (reg0) : :); ++} ++ ++void plat_rockchip_bl31_entrypoint(uint64_t reg0, uint64_t reg1, ++ uint64_t reg2, uint64_t reg3) ++{ ++ uint32_t tmp = mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)); ++ ++ /* check the crypto function had been enabled or not */ ++ if (tmp & BIT(4)) { ++ /* save x0~x3 */ ++ boot_cpu_save[0] = reg0; ++ boot_cpu_save[1] = reg1; ++ boot_cpu_save[2] = reg2; ++ boot_cpu_save[3] = reg3; ++ ++ /* enable the crypto function */ ++ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4)); ++ ++ /* remap pmusram to 0xffff0000 */ ++ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001); ++ dsb(); ++ psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT; ++ cpuson_flags[0] = PMU_CPU_HOTPLUG; ++ cpuson_entry_point[0] = (uintptr_t)bl31_entrypoint; ++ dsb(); ++ ++ /* to enable the crypto function, must reset the core0 */ ++ __asm__ volatile ("mov x0, #3\n" ++ "dsb sy\n" ++ "msr rmr_el3, x0\n" ++ "1:\n" ++ "isb\n" ++ "wfi\n" ++ "b 1b\n"); ++ } else { ++ /* remap bootrom to 0xffff0000 */ ++ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000); ++ ++ /* ++ * the crypto function has been enabled, ++ * restore the x0~x3. ++ */ ++ __asm__ volatile ("ldr x0, [%0]\n" ++ "ldr x1, [%0 , 0x8]\n" ++ "ldr x2, [%0 , 0x10]\n" ++ "ldr x3, [%0 , 0x18]\n" ++ : : "r" (&boot_cpu_save[0])); ++ } ++} +diff --git a/plat/rockchip/rk3588/platform.mk b/plat/rockchip/rk3588/platform.mk +index 07eda40..3d9dc59 100644 +--- a/plat/rockchip/rk3588/platform.mk ++++ b/plat/rockchip/rk3588/platform.mk +@@ -96,3 +96,4 @@ + + $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) + $(eval $(call add_define,PLAT_SKIP_DFS_TLB_DCACHE_MAINTENANCE)) ++$(eval $(call add_define,PLAT_RK_BL31_ENTRYPOINT)) diff --git a/atf.patches/rockchip-add-some-pm-helpers-functions.patch b/atf.patches/rockchip-add-some-pm-helpers-functions.patch new file mode 100644 index 0000000..ae94f59 --- /dev/null +++ b/atf.patches/rockchip-add-some-pm-helpers-functions.patch @@ -0,0 +1,293 @@ +From eb5dfe2a76180d85f33fa2e7ed5131852a003dac Mon Sep 17 00:00:00 2001 +From: XiaoDong Huang +Date: Sun, 25 Jun 2023 19:23:07 +0800 +Subject: [PATCH] feat(rockchip): add some pm helpers functions + +Some power domains will be powered off when the system suspends, +so registers in the power domain need to be save/restore. +Now we add some functions to save/restore registers easily: +use rockchip_alloc_region_mem to allocate memory to save/restore registers in regions; +use rockchip_reg_rgn_save to save registers regions in regions; +use rockchip_reg_rgn_restore to restore registers in regions; +use rockchip_dump_reg_rgns to dump registers in regions; + +Signed-off-by: XiaoDong Huang +Change-Id: I34f909a103fbe2d51456e1d92df0be570e35e2a1 +--- + +diff --git a/plat/rockchip/common/include/plat_pm_helpers.h b/plat/rockchip/common/include/plat_pm_helpers.h +new file mode 100644 +index 0000000..2204a65 +--- /dev/null ++++ b/plat/rockchip/common/include/plat_pm_helpers.h +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef PLAT_PM_HELPERS_H ++#define PLAT_PM_HELPERS_H ++ ++#include ++ ++/** ++ * Use this macro to define a register region. ++ * start: start offset from the base address. ++ * end: end offset from the base address. ++ * stride: stride of registers in region. ++ * base: base address of registers in region. ++ * wmsk: write mask of registers in region. ++ */ ++#define REG_REGION(_start, _end, _stride, _base, _wmsk) \ ++{ \ ++ .start = (_base) + (_start), \ ++ .end = (_base) + (_end), \ ++ .stride = _stride, \ ++ .wmsk = _wmsk \ ++} ++ ++struct reg_region { ++ /* Start address of region */ ++ uint32_t start; ++ /* End address of region */ ++ uint32_t end; ++ /* Stride of registers in region */ ++ uint32_t stride; ++ /* Write mask of registers in region */ ++ uint32_t wmsk; ++ /* Buffer to save/restore registers in region */ ++ uint32_t *buf; ++}; ++ ++void rockchip_alloc_region_mem(struct reg_region *rgns, uint32_t rgn_num); ++void rockchip_reg_rgn_save(struct reg_region *rgns, uint32_t rgn_num); ++void rockchip_reg_rgn_restore(struct reg_region *rgns, uint32_t rgn_num); ++void rockchip_reg_rgn_restore_reverse(struct reg_region *rgns, uint32_t rgn_num); ++void rockchip_regs_dump(uint32_t base, ++ uint32_t start_offset, ++ uint32_t end_offset, ++ uint32_t stride); ++void rockchip_dump_reg_rgns(struct reg_region *rgns, uint32_t rgn_num); ++ ++#endif /* PLAT_PM_HELPERS_H */ +diff --git a/plat/rockchip/common/plat_pm_helpers.c b/plat/rockchip/common/plat_pm_helpers.c +new file mode 100644 +index 0000000..191b0ca +--- /dev/null ++++ b/plat/rockchip/common/plat_pm_helpers.c +@@ -0,0 +1,213 @@ ++/* ++ * Copyright (c) 2024, Rockchip, Inc. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define ROCKCHIP_PM_REG_REGION_MEM_LEN (ROCKCHIP_PM_REG_REGION_MEM_SIZE / sizeof(uint32_t)) ++ ++/* REG region */ ++#define RGN_LEN(_rgn) (((_rgn)->end - (_rgn)->start) / (_rgn)->stride + 1) ++ ++#ifndef ROCKCHIP_PM_REG_REGION_MEM_SIZE ++#define ROCKCHIP_PM_REG_REGION_MEM_SIZE 0 ++#endif ++ ++#ifdef ROCKCHIP_REG_RGN_MEM_BASE ++static uint32_t *region_mem = (uint32_t *)ROCKCHIP_REG_RGN_MEM_BASE; ++#else ++static uint32_t region_mem[ROCKCHIP_PM_REG_REGION_MEM_LEN]; ++#endif ++ ++static int region_mem_idx; ++ ++static int alloc_region_mem(uint32_t *buf, int max_len, ++ struct reg_region *rgns, uint32_t rgn_num) ++{ ++ int i; ++ int total_len = 0, len = 0; ++ struct reg_region *r = rgns; ++ ++ assert(buf && rgns && rgn_num); ++ ++ for (i = 0; i < rgn_num; i++, r++) { ++ if (total_len < max_len) ++ r->buf = &buf[total_len]; ++ ++ len = RGN_LEN(r); ++ total_len += len; ++ } ++ ++ if (total_len > max_len) { ++ ERROR("%s The buffer remain length:%d is too small for region:0x%x, at least %d\n", ++ __func__, max_len, rgns[0].start, total_len); ++ panic(); ++ } ++ ++ return total_len; ++} ++ ++/** ++ * Alloc memory to reg_region->buf from region_mem. ++ * @rgns - struct reg_region array. ++ * @rgn_num - struct reg_region array length. ++ */ ++void rockchip_alloc_region_mem(struct reg_region *rgns, uint32_t rgn_num) ++{ ++ int max_len = 0, len; ++ ++ assert(rgns && rgn_num); ++ ++ max_len = ROCKCHIP_PM_REG_REGION_MEM_LEN - region_mem_idx; ++ ++ len = alloc_region_mem(region_mem + region_mem_idx, max_len, ++ rgns, rgn_num); ++ ++ region_mem_idx += len; ++} ++ ++/** ++ * Save (reg_region->start ~ reg_region->end) to reg_region->buf. ++ * @rgns - struct reg_region array. ++ * @rgn_num - struct reg_region array length. ++ */ ++void rockchip_reg_rgn_save(struct reg_region *rgns, uint32_t rgn_num) ++{ ++ struct reg_region *r; ++ uint32_t addr; ++ int i, j; ++ ++ assert(rgns && rgn_num); ++ ++ for (i = 0; i < rgn_num; i++) { ++ r = &rgns[i]; ++ for (j = 0, addr = r->start; addr <= r->end; addr += r->stride, j++) ++ r->buf[j] = mmio_read_32(addr); ++ } ++} ++ ++/** ++ * Restore reg_region->buf to (reg_region->start ~ reg_region->end). ++ * @rgns - struct reg_region array. ++ * @rgn_num - struct reg_region array length. ++ */ ++void rockchip_reg_rgn_restore(struct reg_region *rgns, uint32_t rgn_num) ++{ ++ struct reg_region *r; ++ uint32_t addr; ++ int i, j; ++ ++ assert(rgns && rgn_num); ++ ++ for (i = 0; i < rgn_num; i++) { ++ r = &rgns[i]; ++ for (j = 0, addr = r->start; addr <= r->end; addr += r->stride, j++) ++ mmio_write_32(addr, r->buf[j] | r->wmsk); ++ ++ dsb(); ++ } ++} ++ ++/** ++ * Restore reg_region->buf to (reg_region->start ~ reg_region->end) reversely. ++ * @rgns - struct reg_region array. ++ * @rgn_num - struct reg_region array length. ++ */ ++void rockchip_reg_rgn_restore_reverse(struct reg_region *rgns, uint32_t rgn_num) ++{ ++ struct reg_region *r; ++ uint32_t addr; ++ int i, j; ++ ++ assert(rgns && rgn_num); ++ ++ for (i = rgn_num - 1; i >= 0; i--) { ++ r = &rgns[i]; ++ j = RGN_LEN(r) - 1; ++ for (addr = r->end; addr >= r->start; addr -= r->stride, j--) ++ mmio_write_32(addr, r->buf[j] | r->wmsk); ++ ++ dsb(); ++ } ++} ++ ++static void rockchip_print_hex(uint32_t val) ++{ ++ int i; ++ unsigned char tmp; ++ ++ putchar('0'); ++ putchar('x'); ++ for (i = 0; i < 8; val <<= 4, ++i) { ++ tmp = (val & 0xf0000000) >> 28; ++ if (tmp < 10) ++ putchar('0' + tmp); ++ else ++ putchar('a' + tmp - 10); ++ } ++} ++ ++/** ++ * Dump registers (base + start_offset ~ base + end_offset) ++ * @base - the base addr of the register. ++ * @start_offset - the start offset to dump. ++ * @end_offset - the end offset to dump. ++ * @stride - the stride of the registers. ++ */ ++void rockchip_regs_dump(uint32_t base, ++ uint32_t start_offset, ++ uint32_t end_offset, ++ uint32_t stride) ++{ ++ uint32_t i; ++ ++ for (i = start_offset; i <= end_offset; i += stride) { ++ if ((i - start_offset) % 16 == 0) { ++ putchar('\n'); ++ rockchip_print_hex(base + i); ++ putchar(':'); ++ putchar(' '); ++ putchar(' '); ++ putchar(' '); ++ putchar(' '); ++ } ++ rockchip_print_hex(mmio_read_32(base + i)); ++ putchar(' '); ++ putchar(' '); ++ putchar(' '); ++ putchar(' '); ++ } ++ putchar('\n'); ++} ++ ++/** ++ * Dump reg regions ++ * @rgns - struct reg_region array. ++ * @rgn_num - struct reg_region array length. ++ */ ++void rockchip_dump_reg_rgns(struct reg_region *rgns, uint32_t rgn_num) ++{ ++ struct reg_region *r; ++ int i; ++ ++ assert(rgns && rgn_num); ++ ++ for (i = 0; i < rgn_num; i++) { ++ r = &rgns[i]; ++ rockchip_regs_dump(0x0, r->start, r->end, r->stride); ++ } ++} diff --git a/boot.scr b/boot.scr index ec2a38f..a6b5d83 100644 Binary files a/boot.scr and b/boot.scr differ diff --git a/cmd/gokr-build-kernel/build.go b/cmd/gokr-build-kernel/build.go index 4bae763..38aaf97 100644 --- a/cmd/gokr-build-kernel/build.go +++ b/cmd/gokr-build-kernel/build.go @@ -19,7 +19,7 @@ import ( var configContents []byte // see https://www.kernel.org/releases.json -var latest = "https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-6.9.8.tar.xz" +var latest = "https://git.kernel.org/torvalds/t/linux-6.10-rc7.tar.gz" func downloadKernel() error { out, err := os.Create(filepath.Base(latest)) @@ -42,7 +42,7 @@ func downloadKernel() error { } func applyPatches(srcdir string) error { - patches, err := filepath.Glob("*.patch") + patches, err := filepath.Glob("kernel.patches/*.patch") if err != nil { return err } @@ -152,7 +152,7 @@ func main() { log.Fatalf("untar: %v", err) } - srcdir := strings.TrimSuffix(filepath.Base(latest), ".tar.xz") + srcdir := strings.TrimSuffix(filepath.Base(latest), ".tar.gz") log.Printf("applying patches") if err := applyPatches(srcdir); err != nil { @@ -172,7 +172,7 @@ func main() { log.Fatal(err) } - if err := copyFile("/tmp/buildresult/rk3328-rock64.dtb", "arch/arm64/boot/dts/rockchip/rk3328-rock64.dtb"); err != nil { + if err := copyFile("/tmp/buildresult/rk3588-friendlyelec-cm3588-nas.dtb", "arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dtb"); err != nil { log.Fatal(err) } } diff --git a/cmd/gokr-build-uboot/build.go b/cmd/gokr-build-uboot/build.go index be3988c..f3315db 100644 --- a/cmd/gokr-build-uboot/build.go +++ b/cmd/gokr-build-uboot/build.go @@ -13,15 +13,15 @@ import ( const ubootRev = "fd46ea0e701920eb205c2bce9d527bf0dec10b59" const ubootTS = 1720219003 -const trustedRepoRev = "10eb851f92acc67f7cdb955770e3bdced3026677" +const trustedRepoRev = "c970c1c38f6d06a3e48e00ea7533c0e427311bcb" const ( uBootRepo = "https://github.com/u-boot/u-boot" trustedFirmwareRepo = "https://github.com/ARM-software/arm-trusted-firmware" ) -func applyPatches(srcdir string) error { - patches, err := filepath.Glob("*.patch") +func applyPatches(srcdir, t string) error { + patches, err := filepath.Glob(t+".patches/*.patch") if err != nil { return err } @@ -47,7 +47,7 @@ func applyPatches(srcdir string) error { } func compile(trustedFirmwareDir string) error { - defconfig := exec.Command("make", "ARCH=arm64", "rock64-rk3328_defconfig") + defconfig := exec.Command("make", "ARCH=arm64", "nanopc-t6-rk3588_defconfig") defconfig.Stdout = os.Stdout defconfig.Stderr = os.Stderr if err := defconfig.Run(); err != nil { @@ -70,7 +70,8 @@ func compile(trustedFirmwareDir string) error { "ARCH=arm64", "CROSS_COMPILE=aarch64-linux-gnu-", "SOURCE_DATE_EPOCH="+strconv.Itoa(ubootTS), - fmt.Sprintf("BL31=%s/build/rk3328/release/bl31/bl31.elf", trustedFirmwareDir), + fmt.Sprintf("BL31=%s/build/rk3588/release/bl31/bl31.elf", trustedFirmwareDir), + fmt.Sprintf("ROCKCHIP_TPL=%s","/usr/src/uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin"), ) make.Stdout = os.Stdout make.Stderr = os.Stderr @@ -140,7 +141,23 @@ func main() { {"git", "remote", "add", "origin", trustedFirmwareRepo}, {"git", "fetch", "--depth=1", "origin", trustedRepoRev}, {"git", "checkout", "FETCH_HEAD"}, - {"make", "SOURCE_DATE_EPOCH=1600000000", "CROSS_COMPILE=aarch64-linux-gnu-", "PLAT=rk3328"}, + } { + log.Printf("Running %s", cmd) + cmdObj := exec.Command(cmd[0], cmd[1:]...) + cmdObj.Stdout = os.Stdout + cmdObj.Stderr = os.Stderr + cmdObj.Dir = trustedFirmwareDir + if err := cmdObj.Run(); err != nil { + log.Fatal(err) + } + } + + log.Printf("applying patches") + if err := applyPatches(trustedFirmwareDir, "atf"); err != nil { + log.Fatal(err) + } + for _, cmd := range [][]string{ + {"make", "SOURCE_DATE_EPOCH=1600000000", "CROSS_COMPILE=aarch64-linux-gnu-", "PLAT=rk3588"}, } { log.Printf("Running %s", cmd) cmdObj := exec.Command(cmd[0], cmd[1:]...) @@ -153,7 +170,7 @@ func main() { } var bootCmdPath string - if p, err := filepath.Abs("boot.cmd"); err != nil { + if p, err := filepath.Abs("uboot.patches/boot.cmd"); err != nil { log.Fatal(err) } else { bootCmdPath = p @@ -180,7 +197,7 @@ func main() { } log.Printf("applying patches") - if err := applyPatches(ubootDir); err != nil { + if err := applyPatches(ubootDir, "uboot"); err != nil { log.Fatal(err) } diff --git a/cmd/gokr-rebuild-kernel/kernel.go b/cmd/gokr-rebuild-kernel/kernel.go index b521e44..fc3dd22 100644 --- a/cmd/gokr-rebuild-kernel/kernel.go +++ b/cmd/gokr-rebuild-kernel/kernel.go @@ -18,6 +18,7 @@ const dockerFileContents = ` FROM debian:bullseye RUN apt-get update && apt-get install -y crossbuild-essential-arm64 bc libssl-dev bison flex +RUN mkdir -p /usr/src/kernel.patches COPY gokr-build-kernel /usr/bin/gokr-build-kernel {{- range $idx, $path := .Patches }} @@ -41,8 +42,43 @@ var dockerFileTmpl = template.Must(template.New("dockerfile"). Parse(dockerFileContents)) var patchFiles = []string{ - // "0001-ODROID-XU4-regulator-s2mps11-call-shutdown-function-.patch", - // "0002-ODROID-XU4-regulator-s2mps11-add-ethernet-power-rese.patch", + "kernel.patches/0001-dt-bindings-arm-rockchip-Add-FriendlyElec-CM3588-NAS.patch", + "kernel.patches/0002-arm64-dts-rockchip-Add-FriendlyElec-CM3588-NAS-board.patch", + "kernel.patches/0010-fix-clk-divisions.patch", + "kernel.patches/0011-irqchip-fix-its-timeout-issue.patch", + "kernel.patches/0012-fix-initial-PERST-GPIO-value.patch", + "kernel.patches/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch", + "kernel.patches/0024-RK3588-Add-Crypto-Support.patch", + "kernel.patches/0025-RK3588-Add-HW-RNG-Support.patch", + "kernel.patches/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch", + "kernel.patches/0027-RK3588-Add-rkvdec2-Support-v3.patch", + "kernel.patches/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch", + "kernel.patches/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch", + "kernel.patches/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch", + "kernel.patches/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch", + "kernel.patches/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch", + "kernel.patches/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch", + "kernel.patches/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch", + "kernel.patches/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch", + "kernel.patches/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch", + "kernel.patches/0170-drm-rockchip-vop2-add-clocks-reset-support.patch", + "kernel.patches/0801-wireless-add-bcm43752.patch", + "kernel.patches/0802-wireless-add-clk-property.patch", + "kernel.patches/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch", + "kernel.patches/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch", + "kernel.patches/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch", + "kernel.patches/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch", + "kernel.patches/1015-board-rock5b-automatic-fan-control.patch", + "kernel.patches/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch", + "kernel.patches/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch", + "kernel.patches/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch", + "kernel.patches/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch", + "kernel.patches/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch", + "kernel.patches/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch", + "kernel.patches/1040-board-khadas-edge2-add-nodes.patch", + "kernel.patches/1041-board-khadas-edge2-mcu.patch", + "kernel.patches/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch", + // "linux-6.10-rc7.tar.gz", } func copyFile(dest, src string) error { @@ -135,8 +171,8 @@ func main() { } defer os.RemoveAll(tmp) - cmd := exec.Command("go", "install", "github.com/anupcshan/gokrazy-rock64-kernel/cmd/gokr-build-kernel") - cmd.Env = append(os.Environ(), "GOOS=linux", "CGO_ENABLED=0", "GOBIN="+tmp) + cmd := exec.Command("go", "build", "-o", tmp, "github.com/anupcshan/gokrazy-rock64-kernel/cmd/gokr-build-kernel") + cmd.Env = append(os.Environ(), "GOOS=linux", "CGO_ENABLED=0") cmd.Stderr = os.Stderr if err := cmd.Run(); err != nil { log.Fatalf("%v: %v", cmd.Args, err) @@ -157,15 +193,18 @@ func main() { if err != nil { log.Fatal(err) } - dtbPath, err := find("rk3328-rock64.dtb") + dtbPath, err := find("rk3588-friendlyelec-cm3588-nas.dtb") + if err != nil { + log.Fatal(err) + } + err = os.MkdirAll(filepath.Join(tmp, "kernel.patches"), 0750) if err != nil { log.Fatal(err) } - // Copy all files into the temporary directory so that docker // includes them in the build context. for _, path := range patchPaths { - if err := copyFile(filepath.Join(tmp, filepath.Base(path)), path); err != nil { + if err := copyFile(filepath.Join(tmp, "kernel.patches", filepath.Base(path)), path); err != nil { log.Fatal(err) } } @@ -239,7 +278,7 @@ func main() { log.Fatal(err) } - if err := copyFile(dtbPath, filepath.Join(tmp, "rk3328-rock64.dtb")); err != nil { + if err := copyFile(dtbPath, filepath.Join(tmp, "rk3588-friendlyelec-cm3588-nas.dtb")); err != nil { log.Fatal(err) } } diff --git a/cmd/gokr-rebuild-uboot/uboot.go b/cmd/gokr-rebuild-uboot/uboot.go index c17904c..345d4c6 100644 --- a/cmd/gokr-rebuild-uboot/uboot.go +++ b/cmd/gokr-rebuild-uboot/uboot.go @@ -19,6 +19,8 @@ FROM debian:bookworm RUN apt-get update && apt-get install -y crossbuild-essential-arm64 bc libssl-dev bison flex git python3 python3-setuptools swig python3-dev python3-pyelftools uuid-dev libgnutls28-dev COPY gokr-build-uboot /usr/bin/gokr-build-uboot +RUN mkdir -p /usr/src/atf.patches +RUN mkdir -p /usr/src/uboot.patches {{- range $idx, $path := .Patches }} COPY {{ $path }} /usr/src/{{ $path }} {{- end }} @@ -39,7 +41,16 @@ var dockerFileTmpl = template.Must(template.New("dockerfile"). }). Parse(dockerFileContents)) -var patchFiles = []string{"boot.cmd"} +var ubootPatchFiles = []string{ + "uboot.patches/boot.cmd", + "uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin", +} +var atfPatchFiles = []string{ + "atf.patches/feat-rk3588-support-rk3588.patch", + "atf.patches/rk3588-enable-crypto-function.patch", + "atf.patches/feat-rockchip-support-SCMI-for-clock-reset-domain.patch", + "atf.patches/rockchip-add-some-pm-helpers-functions.patch", +} func copyFile(dest, src string) error { out, err := os.Create(dest) @@ -131,8 +142,8 @@ func main() { } defer os.RemoveAll(tmp) - cmd := exec.Command("go", "install", "github.com/anupcshan/gokrazy-rock64-kernel/cmd/gokr-build-uboot") - cmd.Env = append(os.Environ(), "GOOS=linux", "CGO_ENABLED=0", "GOBIN="+tmp) + cmd := exec.Command("go", "build", "-o", tmp, "github.com/anupcshan/gokrazy-rock64-kernel/cmd/gokr-build-uboot") + cmd.Env = append(os.Environ(), "GOOS=linux", "CGO_ENABLED=0") cmd.Stderr = os.Stderr if err := cmd.Run(); err != nil { log.Fatalf("%v: %v", cmd.Args, err) @@ -141,7 +152,8 @@ func main() { buildPath := filepath.Join(tmp, "gokr-build-uboot") var patchPaths []string - for _, filename := range patchFiles { + + for _, filename := range ubootPatchFiles { path, err := find(filename) if err != nil { log.Fatal(err) @@ -149,10 +161,37 @@ func main() { patchPaths = append(patchPaths, path) } + err = os.MkdirAll(filepath.Join(tmp, "uboot.patches"), 0750) + if err != nil { + log.Fatal(err) + } // Copy all files into the temporary directory so that docker // includes them in the build context. for _, path := range patchPaths { - if err := copyFile(filepath.Join(tmp, filepath.Base(path)), path); err != nil { + if err = copyFile(filepath.Join(tmp, "uboot.patches", filepath.Base(path)), path); err != nil { + log.Fatal(err) + } + } + + + patchPaths = patchPaths[0:0] + for _, filename := range atfPatchFiles { + path, err := find(filename) + if err != nil { + log.Fatal(err) + } + patchPaths = append(patchPaths, path) + } + + + err = os.MkdirAll(filepath.Join(tmp, "atf.patches"), 0750) + if err != nil { + log.Fatal(err) + } + // Copy all files into the temporary directory so that docker + // includes them in the build context. + for _, path := range patchPaths { + if err := copyFile(filepath.Join(tmp, "atf.patches", filepath.Base(path)), path); err != nil { log.Fatal(err) } } @@ -175,7 +214,7 @@ func main() { Uid: u.Uid, Gid: u.Gid, BuildPath: buildPath, - Patches: patchFiles, + Patches: append(atfPatchFiles, ubootPatchFiles...), }); err != nil { log.Fatal(err) } diff --git a/kernel.patches/0001-dt-bindings-arm-rockchip-Add-FriendlyElec-CM3588-NAS.patch b/kernel.patches/0001-dt-bindings-arm-rockchip-Add-FriendlyElec-CM3588-NAS.patch new file mode 100644 index 0000000..a15190c --- /dev/null +++ b/kernel.patches/0001-dt-bindings-arm-rockchip-Add-FriendlyElec-CM3588-NAS.patch @@ -0,0 +1,37 @@ +From e6b6a82789baf275a597ef312a145c3b4a44da19 Mon Sep 17 00:00:00 2001 +From: Sebastian Kropatsch +Date: Sun, 16 Jun 2024 23:48:29 +0200 +Subject: [PATCH 1/2] dt-bindings: arm: rockchip: Add FriendlyElec CM3588 NAS + +Add devicetree bindings for the FriendlyElec CM3588 NAS board. + +The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based on +the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Sebastian Kropatsch +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index fcf7316ec..86379b8cc 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -236,6 +236,13 @@ properties: + - const: friendlyarm,nanopc-t6 + - const: rockchip,rk3588 + ++ - description: FriendlyElec CM3588-based boards ++ items: ++ - enum: ++ - friendlyarm,cm3588-nas ++ - const: friendlyarm,cm3588 ++ - const: rockchip,rk3588 ++ + - description: GeekBuying GeekBox + items: + - const: geekbuying,geekbox +-- +2.45.2 + diff --git a/kernel.patches/0001-general-add-overlay-support.patch b/kernel.patches/0001-general-add-overlay-support.patch new file mode 100644 index 0000000..e7d5768 --- /dev/null +++ b/kernel.patches/0001-general-add-overlay-support.patch @@ -0,0 +1,69 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sun, 2 Jun 2024 21:53:01 +0200 +Subject: compile .scr and install overlays in right path + +--- + scripts/Makefile.dtbinst | 13 +++++++++- + scripts/Makefile.lib | 8 +++++- + 2 files changed, 19 insertions(+), 2 deletions(-) + +diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst +index 111111111111..222222222222 100644 +--- a/scripts/Makefile.dtbinst ++++ b/scripts/Makefile.dtbinst +@@ -33,7 +33,18 @@ endef + + $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d)))) + +-dtbs := $(notdir $(dtbs)) ++# Very convoluted way to flatten all the device tree ++# directories, but keep the "/overlay/" directory ++ ++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip) ++topmost_dir = $(firstword $(subst /, ,$(dtbs))) ++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir" ++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs))) ++# collect the non-overlay dtbs ++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs)) ++# compose the dtbs variable flattening all the non-overlays entries ++# and appending the overlays entries ++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays) + + endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL + +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index 111111111111..222222222222 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -402,7 +402,7 @@ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE + + quiet_cmd_dtc = DTC $@ + cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ +- $(DTC) -o $@ -b 0 \ ++ $(DTC) -@ -o $@ -b 0 \ + $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) +@@ -427,12 +427,18 @@ quiet_cmd_dtb = $(quiet_cmd_dtc) + cmd_dtb = $(cmd_dtc) + endif + ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ + $(obj)/%.dtb: $(obj)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(call if_changed_dep,dtb) + + $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE + $(call if_changed_dep,dtc) + ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) ++ + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + + # Bzip2 +-- +Armbian + diff --git a/kernel.patches/0002-arm64-dts-rockchip-Add-FriendlyElec-CM3588-NAS-board.patch b/kernel.patches/0002-arm64-dts-rockchip-Add-FriendlyElec-CM3588-NAS-board.patch new file mode 100644 index 0000000..a3b3256 --- /dev/null +++ b/kernel.patches/0002-arm64-dts-rockchip-Add-FriendlyElec-CM3588-NAS-board.patch @@ -0,0 +1,1503 @@ +From ba3cba5c61886504d0593c03966368e4d321774f Mon Sep 17 00:00:00 2001 +From: Sebastian Kropatsch +Date: Sun, 16 Jun 2024 23:48:30 +0200 +Subject: [PATCH 2/2] arm64: dts: rockchip: Add FriendlyElec CM3588 NAS board + +The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based on +the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board. +To reflect the hardware setup, add device tree sources for the SoM and +the NAS daughter board as separate files. + +Hardware features: + - Rockchip RK3588 SoC + - 4GB/8GB/16GB LPDDR4x RAM + - 64GB eMMC + - MicroSD card slot + - 1x RTL8125B 2.5G Ethernet + - 4x M.2 M-Key with PCIe 3.0 x1 (via bifurcation) for NVMe SSDs + - 2x USB 3.0 (USB 3.1 Gen1) Type-A, 1x USB 2.0 Type-A + - 1x USB 3.0 Type-C with DP AltMode support + - 2x HDMI 2.1 out, 1x HDMI in + - MIPI-CSI Connector, MIPI-DSI Connector + - 40-pin GPIO header + - 4 buttons: power, reset, recovery, MASK, user button + - 3.5mm Headphone out, 2.0mm PH-2A Mic in + - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector + +PCIe bifurcation is used to handle all four M.2 sockets at PCIe 3.0 x1 +speed. Data lane mapping in the DT is done like described in commit +f8020dfb311d ("phy: rockchip-snps-pcie3: fix bifurcation on rk3588"). + +This device tree includes support for eMMC, SD card, ethernet, all USB2 +and USB3 ports, all four M.2 slots, GPU, beeper, IR, RTC, UART debugging +as well as the buttons and LEDs. +The GPIOs are labeled according to the schematics. + +Reviewed-by: Space Meyer +Signed-off-by: Sebastian Kropatsch +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../rk3588-friendlyelec-cm3588-nas.dts | 778 ++++++++++++++++++ + .../rockchip/rk3588-friendlyelec-cm3588.dtsi | 653 +++++++++++++++ + 3 files changed, 1432 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index f906a868b..c528f5382 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -112,6 +112,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +new file mode 100644 +index 000000000..83103e4c7 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +@@ -0,0 +1,778 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2023 Thomas McKahan ++ * Copyright (c) 2024 Sebastian Kropatsch ++ * ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include "rk3588-friendlyelec-cm3588.dtsi" ++ ++/ { ++ model = "FriendlyElec CM3588 NAS"; ++ compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588"; ++ ++ adc_key_recovery: adc-key-recovery { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 1>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <100>; ++ ++ button-recovery { ++ label = "Recovery"; ++ linux,code = ; ++ press-threshold-microvolt = <17000>; ++ }; ++ }; ++ ++ analog-sound { ++ compatible = "simple-audio-card"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&headphone_detect>; ++ ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,name = "realtek,rt5616-codec"; ++ ++ simple-audio-card,routing = ++ "Headphones", "HPOL", ++ "Headphones", "HPOR", ++ "MIC1", "Microphone Jack", ++ "Microphone Jack", "micbias1"; ++ simple-audio-card,widgets = ++ "Headphone", "Headphones", ++ "Microphone", "Microphone Jack"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s0_8ch>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rt5616>; ++ }; ++ }; ++ ++ buzzer: pwm-beeper { ++ compatible = "pwm-beeper"; ++ amp-supply = <&vcc_5v0_sys>; ++ beeper-hz = <500>; ++ pwms = <&pwm8 0 500000 0>; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ #cooling-cells = <2>; ++ cooling-levels = <0 50 80 120 160 220>; ++ fan-supply = <&vcc_5v0_sys>; ++ pwms = <&pwm1 0 50000 0>; ++ }; ++ ++ gpio_keys: gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&key1_pin>; ++ ++ button-user { ++ debounce-interval = <50>; ++ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; ++ label = "User Button"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ vcc_12v_dcin: regulator-vcc-12v-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ vcc_3v3_m2_a: regulator-vcc-3v3-m2-a { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_m2_a"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_12v_dcin>; ++ }; ++ ++ vcc_3v3_m2_b: regulator-vcc-3v3-m2-b { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_m2_b"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_12v_dcin>; ++ }; ++ ++ vcc_3v3_m2_c: regulator-vcc-3v3-m2-c { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_m2_c"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_12v_dcin>; ++ }; ++ ++ vcc_3v3_m2_d: regulator-vcc-3v3-m2-d { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_m2_d"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_12v_dcin>; ++ }; ++ ++ /* vcc_5v0_sys powers the peripherals */ ++ vcc_5v0_sys: regulator-vcc-5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_12v_dcin>; ++ }; ++ ++ /* SY6280AAC power switch (U14 in schematics) */ ++ vcc_5v0_host_20: regulator-vcc-5v0-host-20 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_5v0_host20_en>; ++ regulator-name = "vcc_5v0_host_20"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++ ++ /* SY6280AAC power switch (U8 in schematics) */ ++ vcc_5v0_host_30_p1: regulator-vcc-5v0-host-30-p1 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_5v0_host30p1_en>; ++ regulator-name = "vcc_5v0_host_30_p1"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++ ++ /* SY6280AAC power switch (U9 in schematics) */ ++ vcc_5v0_host_30_p2: regulator-vcc-5v0-host-30-p2 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_5v0_host30p2_en>; ++ regulator-name = "vcc_5v0_host_30_p2"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++ ++ /* SY6280AAC power switch (U10 in schematics) */ ++ vbus_5v0_typec: regulator-vbus-5v0-typec { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec_5v_pwr_en>; ++ regulator-name = "vbus_5v0_typec"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v0_sys>; ++ }; ++}; ++ ++/* vcc_4v0_sys powers the RK806 and RK860's */ ++&vcc_4v0_sys { ++ vin-supply = <&vcc_12v_dcin>; ++}; ++ ++/* Combo PHY 1 is configured to act as as PCIe 2.0 PHY */ ++/* Used by PCIe controller 2 (pcie2x1l0) */ ++&combphy1_ps { ++ status = "okay"; ++}; ++ ++/* Combo PHY 2 is configured to act as USB3 PHY */ ++/* Used by USB 3.0 OTG 2 controller (USB 3.0 Type-A port 2) */ ++/* CM3588 USB Controller Config Table: USB30 HOST2 */ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++/* GPIO names are in the format "Human-readable-name [SIGNAL_LABEL]" */ ++/* Signal labels match the official CM3588 NAS SDK schematic revision 2309 */ ++&gpio0 { ++ gpio-line-names = ++ /* GPIO0 A0-A7 */ ++ "", "", "", "", ++ "MicroSD detect [SDMMC_DET_L]", "", "", "", ++ /* GPIO0 B0-B7 */ ++ "", "", "", "", ++ "", "", "", "", ++ /* GPIO0 C0-C7 */ ++ "", "", "", "", ++ "Pin 10 [UART0_RX_M0]", "Pin 08 [UART0_TX_M0/PWM4_M0]", "Pin 32 [PWM5_M1]", "", ++ /* GPIO0 D0-D7 */ ++ "", "", "", "USB3 Type-C [CC_INT_L]", ++ "IR receiver [PWM3_IR_M0]", "User Button", "", ""; ++}; ++ ++&gpio1 { ++ gpio-line-names = ++ /* GPIO1 A0-A7 */ ++ "Pin 27 [UART6_RX_M1]", "Pin 28 [UART6_TX_M1]", "", "", ++ "USB2 Type-A [USB2_PWREN]", "", "", "Pin 15", ++ /* GPIO1 B0-B7 */ ++ "Pin 26", "Pin 21 [SPI0_MISO_M2]", "Pin 19 [SPI0_MOSI_M2/UART4_RX_M2]", "Pin 23 [SPI0_CLK_M2/UART4_TX_M2]", ++ "Pin 24 [SPI0_CS0_M2/UART7_RX_M2]", "Pin 22 [SPI0_CS1_M0/UART7_TX_M2]", "", "CSI-Pin 14 [MIPI_CAM2_CLKOUT]", ++ /* GPIO1 C0-C7 */ ++ "", "", "", "", ++ "Headphone detect [HP_DET_L]", "", "", "", ++ /* GPIO1 D0-D7 */ ++ "", "", "USB3 Type-C [TYPEC5V_PWREN_H]", "5V Fan [PWM1_M1]", ++ "", "HDMI-in detect [HDMIIRX_DET_L]", "Pin 05 [I2C8_SCL_M2]", "Pin 03 [I2C8_SDA_M2]"; ++}; ++ ++&gpio2 { ++ gpio-line-names = ++ /* GPIO2 A0-A7 */ ++ "", "", "", "", ++ "", "", "SPI NOR Flash [FSPI_D0_M1]", "SPI NOR Flash [FSPI_D1_M1]", ++ /* GPIO2 B0-B7 */ ++ "SPI NOR Flash [FSPI_D2_M1]", "SPI NOR Flash [FSPI_D3_M1]", "", "SPI NOR Flash [FSPI_CLK_M1]", ++ "SPI NOR Flash [FSPI_CSN0_M1]", "", "", "", ++ /* GPIO2 C0-C7 */ ++ "", "CSI-Pin 11 [MIPI_CAM2_RESET_L]", "CSI-Pin 12 [MIPI_CAM2_PDN_L]", "", ++ "", "", "", "", ++ /* GPIO2 D0-D7 */ ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpio3 { ++ gpio-line-names = ++ /* GPIO3 A0-A7 */ ++ "Pin 35 [SPI4_MISO_M1/PWM10_M0]", "Pin 38 [SPI4_MOSI_M1]", "Pin 40 [SPI4_CLK_M1/UART8_TX_M1]", "Pin 36 [SPI4_CS0_M1/UART8_RX_M1]", ++ "Pin 37 [SPI4_CS1_M1]", "USB3-A #2 [USB3_2_PWREN]", "DSI-Pin 12 [LCD_RST]", "Buzzer [PWM8_M0]", ++ /* GPIO3 B0-B7 */ ++ "Pin 33 [PWM9_M0]", "DSI-Pin 10 [PWM2_M1/LCD_BL]", "Pin 07", "Pin 16", ++ "Pin 18", "Pin 29 [UART3_TX_M1/PWM12_M0]", "Pin 31 [UART3_RX_M1/PWM13_M0]", "Pin 12", ++ /* GPIO3 C0-C7 */ ++ "DSI-Pin 08 [TP_INT_L]", "DSI-Pin 14 [TP_RST_L]", "Pin 11 [PWM14_M0]", "Pin 13 [PWM15_IR_M0]", ++ "", "", "", "DSI-Pin 06 [I2C5_SCL_M0_TP]", ++ /* GPIO3 D0-D7 */ ++ "DSI-Pin 05 [I2C5_SDA_M0_TP]", "", "", "", ++ "", "", "", ""; ++}; ++ ++&gpio4 { ++ gpio-line-names = ++ /* GPIO4 A0-A7 */ ++ "", "", "M.2 M-Key Slot4 [M2_D_PERST_L]", "", ++ "", "", "", "", ++ /* GPIO4 B0-B7 */ ++ "USB3-A #1 [USB3_TYPEC1_PWREN]", "", "", "M.2 M-Key Slot3 [M2_C_PERST_L]", ++ "M.2 M-Key Slot2 [M2_B_PERST_L]", "M.2 M-Key Slot1 [M2_A_CLKREQ_L]", "M.2 M-Key Slot1 [M2_A_PERST_L]", "", ++ /* GPIO4 C0-C7 */ ++ "", "", "", "", ++ "", "", "", "", ++ /* GPIO4 D0-D7 */ ++ "", "", "", "", ++ "", "", "", ""; ++}; ++ ++/* Connected to MIPI-DSI0 */ ++&i2c5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c5m0_xfer>; ++ status = "disabled"; ++}; ++ ++&i2c6 { ++ fusb302: typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc0_int>; ++ vbus-supply = <&vbus_5v0_typec>; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ data-role = "dual"; ++ label = "USB-C"; ++ power-role = "source"; ++ source-pdos = ; ++ try-power-role = "source"; ++ vbus-supply = <&vbus_5v0_typec>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usbc0_orien_sw: endpoint { ++ remote-endpoint = <&usbdp_phy0_orientation_switch>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usbc0_role_sw: endpoint { ++ remote-endpoint = <&dwc3_0_role_switch>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ dp_altmode_mux: endpoint { ++ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++/* Connected to MIPI-CSI1 */ ++/* &i2c7 */ ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8m2_xfer>; ++ status = "okay"; ++}; ++ ++&pcie2x1l0 { ++ /* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */ ++ max-link-speed = <3>; ++ num-lanes = <1>; ++ phys = <&pcie30phy>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_rst>; ++ reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_m2_b>; ++ status = "okay"; ++}; ++ ++&pcie2x1l1 { ++ /* 4. M.2 socket, CON16: pcie30phy port1 lane1, @fe180000 */ ++ max-link-speed = <3>; ++ num-lanes = <1>; ++ phys = <&pcie30phy>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_1_rst>; ++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_m2_d>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ /* ++ * Data lane mapping <1 3 2 4> = x1x1 x1x1 (bifurcation of both ports) ++ * port 0 lane 0 - always mapped to controller 0 (4L) ++ * port 0 lane 1 - map to controller 2 (1L0) ++ * port 1 lane 0 - map to controller 1 (2L) ++ * port 1 lane 1 - map to controller 3 (1L1) ++ */ ++ data-lanes = <1 3 2 4>; ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ /* 1. M.2 socket, CON13: pcie30phy port0 lane0, @fe150000 */ ++ max-link-speed = <3>; ++ num-lanes = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3x4_rst>; ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_m2_a>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ /* 3. M.2 socket, CON15: pcie30phy port1 lane0, @fe160000 */ ++ max-link-speed = <3>; ++ num-lanes = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3x2_rst>; ++ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_m2_c>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ audio { ++ headphone_detect: headphone-detect { ++ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ gpio-key { ++ key1_pin: key1-pin { ++ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pcie { ++ pcie2_0_rst: pcie2-0-rst { ++ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_1_rst: pcie2-1-rst { ++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie3x2_rst: pcie3x2-rst { ++ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie3x4_rst: pcie3x4-rst { ++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc_5v0_host20_en: vcc-5v0-host20-en { ++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc_5v0_host30p1_en: vcc-5v0-host30p1-en { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc_5v0_host30p2_en: vcc-5v0-host30p2-en { ++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb-typec { ++ usbc0_int: usbc0-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ typec_5v_pwr_en: typec-5v-pwr-en { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++/* Connected to 5V Fan */ ++&pwm1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm1m1_pins>; ++ status = "okay"; ++}; ++ ++/* Connected to MIPI-DSI0 */ ++&pwm2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm2m1_pins>; ++}; ++ ++/* Connected to IR Receiver */ ++&pwm3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm3m0_pins>; ++ status = "okay"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with UART0 */ ++&pwm4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm4m1_pins>; ++ status = "disabled"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++&pwm5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm5m1_pins>; ++ status = "okay"; ++}; ++ ++/* Connected to Buzzer */ ++&pwm8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm8m0_pins>; ++ status = "okay"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++&pwm9 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm9m0_pins>; ++ status = "okay"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with SPI4 */ ++&pwm10 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm10m0_pins>; ++ status = "disabled"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with UART3 */ ++&pwm12 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm12m0_pins>; ++ status = "disabled"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with UART3 */ ++&pwm13 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm13m0_pins>; ++ status = "disabled"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++&pwm14 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm14m0_pins>; ++ status = "okay"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Optimized for infrared applications */ ++&pwm15 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm15m0_pins>; ++ status = "disabled"; ++}; ++ ++/* microSD card */ ++&sdmmc { ++ status = "okay"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with UART4, UART7 and PWM10 */ ++&spi0 { ++ num-cs = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; ++ status = "disabled"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with UART8 */ ++&spi4 { ++ num-cs = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi4m1_cs0 &spi4m1_pins>; ++ status = "disabled"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with PWM4 */ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0m0_xfer>; ++ status = "disabled"; ++}; ++ ++/* Debug UART */ ++&uart2 { ++ status = "okay"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with PWM12 and PWM13 */ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3m1_xfer>; ++ status = "disabled"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with SPI0 */ ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4m2_xfer>; ++ status = "disabled"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++&uart6 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart6m1_xfer>; ++ status = "okay"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with SPI0 */ ++&uart7 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart7m2_xfer>; ++ status = "disabled"; ++}; ++ ++/* GPIO Connector, connected to 40-pin GPIO header */ ++/* Shared with SPI4 */ ++&uart8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart8m1_xfer>; ++ status = "disabled"; ++}; ++ ++/* USB2 PHY for USB Type-C port */ ++/* CM3588 USB Controller Config Table: USB20 OTG0 */ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ phy-supply = <&vbus_5v0_typec>; ++ status = "okay"; ++}; ++ ++/* USB2 PHY for USB 3.0 Type-A port 1 */ ++/* CM3588 USB Controller Config Table: USB20 OTG1 */ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ phy-supply = <&vcc_5v0_host_30_p1>; ++ status = "okay"; ++}; ++ ++/* USB2 PHY for USB 2.0 Type-A */ ++/* CM3588 USB Controller Config Table: USB20 HOST0 */ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ phy-supply = <&vcc_5v0_host_20>; ++ status = "okay"; ++}; ++ ++/* USB2 PHY for USB 3.0 Type-A port 2 */ ++/* CM3588 USB Controller Config Table: USB20 HOST1 */ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc_5v0_host_30_p2>; ++ status = "okay"; ++}; ++ ++/* USB 2.0 Type-A */ ++/* PHY: <&u2phy2_host> */ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++/* USB 2.0 Type-A */ ++/* PHY: <&u2phy2_host> */ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++/* USB Type-C */ ++/* PHYs: <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3> */ ++&usb_host0_xhci { ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ dwc3_0_role_switch: endpoint { ++ remote-endpoint = <&usbc0_role_sw>; ++ }; ++ }; ++}; ++ ++/* Lower USB 3.0 Type-A (port 2) */ ++/* PHY: <&u2phy3_host> */ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++/* Lower USB 3.0 Type-A (port 2) */ ++/* PHY: <&u2phy3_host> */ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++/* Upper USB 3.0 Type-A (port 1) */ ++/* PHYs: <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3> */ ++&usb_host1_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++/* Lower USB 3.0 Type-A (port 2) */ ++/* PHYs: <&combphy2_psu PHY_TYPE_USB3> */ ++&usb_host2_xhci { ++ status = "okay"; ++}; ++ ++/* USB3 PHY for USB Type-C port */ ++/* CM3588 USB Controller Config Table: USB30 OTG0 */ ++&usbdp_phy0 { ++ mode-switch; ++ orientation-switch; ++ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; ++ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy0_orientation_switch: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_orien_sw>; ++ }; ++ ++ usbdp_phy0_dp_altmode_mux: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dp_altmode_mux>; ++ }; ++ }; ++}; ++ ++/* USB3 PHY for USB 3.0 Type-A port 1 */ ++/* CM3588 USB Controller Config Table: USB30 OTG1 */ ++&usbdp_phy1 { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +new file mode 100644 +index 000000000..e3a9598b9 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +@@ -0,0 +1,653 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2023 Thomas McKahan ++ * Copyright (c) 2024 Sebastian Kropatsch ++ * ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3588.dtsi" ++ ++/ { ++ model = "FriendlyElec CM3588"; ++ compatible = "friendlyarm,cm3588", "rockchip,rk3588"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_sys: led-0 { ++ color = ; ++ function = LED_FUNCTION_HEARTBEAT; ++ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_sys_pin>; ++ }; ++ ++ led_usr: led-1 { ++ color = ; ++ function = LED_FUNCTION_INDICATOR; ++ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_usr_pin>; ++ }; ++ }; ++ ++ /* vcc_4v0_sys powers the RK806 and RK860's */ ++ vcc_4v0_sys: regulator-vcc-4v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_4v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ }; ++ ++ vcc_3v3_pcie20: regulator-vcc-3v3-pcie20 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_pcie20"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 { ++ compatible = "regulator-fixed"; ++ gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sd_s0_pwr>; ++ regulator-boot-on; ++ regulator-max-microvolt = <3300000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_sd_s0"; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-1v1-nldo-s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc_4v0_sys>; ++ }; ++}; ++ ++/* Combo PHY 0 is configured to act as as PCIe 2.0 PHY */ ++/* Used by PCIe controller 4 (pcie2x1l2) */ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ sram-supply = <&vdd_gpu_mem_s0>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_4v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_4v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ vdd_npu_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_npu_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_4v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ clock-frequency = <200000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c6m0_xfer>; ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&i2c7 { ++ clock-frequency = <200000>; ++ status = "okay"; ++ ++ rt5616: audio-codec@1b { ++ compatible = "realtek,rt5616"; ++ reg = <0x1b>; ++ #sound-dai-cells = <0>; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++}; ++ ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ ++&i2s7_8ch { ++ status = "okay"; ++}; ++ ++&pcie2x1l2 { ++ /* r8125 ethernet, @fe190000 */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_2_rst>; ++ reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_pcie20>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ led_sys_pin: led-sys-pin { ++ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ led_usr_pin: led-usr-pin { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: rtc-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pcie { ++ pcie2_2_rst: pcie2-2-rst { ++ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc { ++ sd_s0_pwr: sd-s0-pwr { ++ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++/* eMMC */ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ no-sd; ++ no-sdio; ++ non-removable; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vcc_1v8_s3>; ++ status = "okay"; ++}; ++ ++/* microSD card */ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ no-mmc; ++ no-sdio; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_sd_s0>; ++ vqmmc-supply = <&vccio_sd_s0>; ++}; ++ ++&spi2 { ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ num-cs = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ status = "okay"; ++ ++ rk806_single: pmic@0 { ++ compatible = "rockchip,rk806"; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ spi-max-frequency = <1000000>; ++ system-power-controller; ++ ++ vcc1-supply = <&vcc_4v0_sys>; ++ vcc2-supply = <&vcc_4v0_sys>; ++ vcc3-supply = <&vcc_4v0_sys>; ++ vcc4-supply = <&vcc_4v0_sys>; ++ vcc5-supply = <&vcc_4v0_sys>; ++ vcc6-supply = <&vcc_4v0_sys>; ++ vcc7-supply = <&vcc_4v0_sys>; ++ vcc8-supply = <&vcc_4v0_sys>; ++ vcc9-supply = <&vcc_4v0_sys>; ++ vcc10-supply = <&vcc_4v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc_4v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc_4v0_sys>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++/* Debug UART */ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2m0_xfer>; ++}; +-- +2.45.2 + diff --git a/kernel.patches/0010-fix-clk-divisions.patch b/kernel.patches/0010-fix-clk-divisions.patch new file mode 100644 index 0000000..25c4a67 --- /dev/null +++ b/kernel.patches/0010-fix-clk-divisions.patch @@ -0,0 +1,142 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 24 Oct 2023 16:09:35 +0200 +Subject: math.h: add DIV_ROUND_UP_NO_OVERFLOW + +Add a new DIV_ROUND_UP helper, which cannot overflow when +big numbers are being used. + +Signed-off-by: Sebastian Reichel +--- + include/linux/math.h | 11 ++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/include/linux/math.h b/include/linux/math.h +index 111111111111..222222222222 100644 +--- a/include/linux/math.h ++++ b/include/linux/math.h +@@ -36,6 +36,17 @@ + + #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP + ++/** ++ * DIV_ROUND_UP_NO_OVERFLOW - divide two numbers and always round up ++ * @n: numerator / dividend ++ * @d: denominator / divisor ++ * ++ * This functions does the same as DIV_ROUND_UP, but internally uses a ++ * division and a modulo operation instead of math tricks. This way it ++ * avoids overflowing when handling big numbers. ++ */ ++#define DIV_ROUND_UP_NO_OVERFLOW(n, d) (((n) / (d)) + !!((n) % (d))) ++ + #define DIV_ROUND_DOWN_ULL(ll, d) \ + ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) + +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 24 Oct 2023 16:13:50 +0200 +Subject: clk: divider: Fix divisor masking on 64 bit platforms + +The clock framework handles clock rates as "unsigned long", so u32 on +32-bit architectures and u64 on 64-bit architectures. + +The current code casts the dividend to u64 on 32-bit to avoid a +potential overflow. For example DIV_ROUND_UP(3000000000, 1500000000) += (3.0G + 1.5G - 1) / 1.5G = = OVERFLOW / 1.5G, which has been +introduced in commit 9556f9dad8f5 ("clk: divider: handle integer overflow +when dividing large clock rates"). + +On 64 bit platforms this masks the divisor, so that only the lower +32 bit are used. Thus requesting a frequency >= 4.3GHz results +in incorrect values. For example requesting 4300000000 (4.3 GHz) will +effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX) +is a bit of a special case, since that still returns correct values as +long as the parent clock is below 8.5 GHz. + +Fix this by switching to DIV_ROUND_UP_NO_OVERFLOW, which cannot +overflow. This avoids any requirements on the arguments (except +that divisor should not be 0 obviously). + +Signed-off-by: Sebastian Reichel +--- + drivers/clk/clk-divider.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c +index 111111111111..222222222222 100644 +--- a/drivers/clk/clk-divider.c ++++ b/drivers/clk/clk-divider.c +@@ -220,7 +220,7 @@ static int _div_round_up(const struct clk_div_table *table, + unsigned long parent_rate, unsigned long rate, + unsigned long flags) + { +- int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); ++ int div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); + + if (flags & CLK_DIVIDER_POWER_OF_TWO) + div = __roundup_pow_of_two(div); +@@ -237,7 +237,7 @@ static int _div_round_closest(const struct clk_div_table *table, + int up, down; + unsigned long up_rate, down_rate; + +- up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); ++ up = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); + down = parent_rate / rate; + + if (flags & CLK_DIVIDER_POWER_OF_TWO) { +@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate, + { + unsigned int div, value; + +- div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); ++ div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); + + if (!_is_valid_div(table, div, flags)) + return -EINVAL; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 24 Oct 2023 18:09:57 +0200 +Subject: clk: composite: replace open-coded abs_diff() + +Replace the open coded abs_diff() with the existing helper function. + +Suggested-by: Andy Shevchenko +Signed-off-by: Sebastian Reichel +--- + drivers/clk/clk-composite.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c +index 111111111111..222222222222 100644 +--- a/drivers/clk/clk-composite.c ++++ b/drivers/clk/clk-composite.c +@@ -6,6 +6,7 @@ + #include + #include + #include ++#include + #include + + static u8 clk_composite_get_parent(struct clk_hw *hw) +@@ -119,10 +120,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw, + if (ret) + continue; + +- if (req->rate >= tmp_req.rate) +- rate_diff = req->rate - tmp_req.rate; +- else +- rate_diff = tmp_req.rate - req->rate; ++ rate_diff = abs_diff(req->rate, tmp_req.rate); + + if (!rate_diff || !req->best_parent_hw + || best_rate_diff > rate_diff) { +-- +Armbian + diff --git a/kernel.patches/0011-irqchip-fix-its-timeout-issue.patch b/kernel.patches/0011-irqchip-fix-its-timeout-issue.patch new file mode 100644 index 0000000..afbe379 --- /dev/null +++ b/kernel.patches/0011-irqchip-fix-its-timeout-issue.patch @@ -0,0 +1,214 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Fri, 11 Aug 2023 17:56:00 +0300 +Subject: irqchip/irq-gic-v3-its: fix its timeout issue for rk35xx boards + +--- + drivers/irqchip/irq-gic-v3-its.c | 79 +++++++++- + 1 file changed, 72 insertions(+), 7 deletions(-) + +diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c +index 111111111111..222222222222 100644 +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -163,6 +163,7 @@ struct its_device { + struct its_node *its; + struct event_lpi_map event_map; + void *itt; ++ u32 itt_sz; + u32 nr_ites; + u32 device_id; + bool shared; +@@ -2191,6 +2192,9 @@ static void gic_reset_prop_table(void *va) + static struct page *its_allocate_prop_table(gfp_t gfp_flags) + { + struct page *prop_page; ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; + + prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); + if (!prop_page) +@@ -2315,6 +2319,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, + u32 alloc_pages, psz; + struct page *page; + void *base; ++ gfp_t gfp_flags; + + psz = baser->psz; + alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); +@@ -2326,7 +2331,11 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, + order = get_order(GITS_BASER_PAGES_MAX * psz); + } + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); ++ gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; ++ ++ page = alloc_pages_node(its->numa_node, gfp_flags, order); + if (!page) + return -ENOMEM; + +@@ -2376,6 +2385,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, + its_write_baser(its, baser, val); + tmp = baser->val; + ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || ++ of_machine_is_compatible("rockchip,rk3588")) { ++ if (tmp & GITS_BASER_SHAREABILITY_MASK) ++ tmp &= ~GITS_BASER_SHAREABILITY_MASK; ++ else ++ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); ++ } ++ + if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { + /* + * Shareability didn't stick. Just use +@@ -2965,7 +2983,9 @@ static int its_alloc_collections(struct its_node *its) + static struct page *its_allocate_pending_table(gfp_t gfp_flags) + { + struct page *pend_page; +- ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; + pend_page = alloc_pages(gfp_flags | __GFP_ZERO, + get_order(LPI_PENDBASE_SZ)); + if (!pend_page) +@@ -3124,6 +3144,11 @@ static void its_cpu_init_lpis(void) + if (!rdists_support_shareable()) + tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; + ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || ++ of_machine_is_compatible("rockchip,rk3588")) ++ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; ++ + if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { + if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { + /* +@@ -3151,6 +3176,11 @@ static void its_cpu_init_lpis(void) + if (!rdists_support_shareable()) + tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; + ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || ++ of_machine_is_compatible("rockchip,rk3588")) ++ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; ++ + if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { + /* + * The HW reports non-shareable, we must remove the +@@ -3314,7 +3344,11 @@ static bool its_alloc_table_entry(struct its_node *its, + + /* Allocate memory for 2nd level table */ + if (!table[idx]) { +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, ++ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; ++ page = alloc_pages_node(its->numa_node, gfp_flags, + get_order(baser->psz)); + if (!page) + return false; +@@ -3403,6 +3437,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, + int nr_lpis; + int nr_ites; + int sz; ++ gfp_t gfp_flags; + + if (!its_alloc_device_table(its, dev_id)) + return NULL; +@@ -3418,7 +3453,15 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, + nr_ites = max(2, nvecs); + sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); + sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; +- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); ++ gfp_flags = GFP_KERNEL; ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) { ++ gfp_flags |= GFP_DMA32; ++ itt = (void *)__get_free_pages(gfp_flags, get_order(sz)); ++ } else { ++ itt = kzalloc_node(sz, gfp_flags, its->numa_node); ++ } ++ + if (alloc_lpis) { + lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); + if (lpi_map) +@@ -3432,7 +3475,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, + + if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { + kfree(dev); +- kfree(itt); ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ free_pages((unsigned long)itt, get_order(sz)); ++ else ++ kfree(itt); ++ + bitmap_free(lpi_map); + kfree(col_map); + return NULL; +@@ -3442,6 +3491,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, + + dev->its = its; + dev->itt = itt; ++ dev->itt_sz = sz; + dev->nr_ites = nr_ites; + dev->event_map.lpi_map = lpi_map; + dev->event_map.col_map = col_map; +@@ -3469,7 +3519,13 @@ static void its_free_device(struct its_device *its_dev) + list_del(&its_dev->entry); + raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); + kfree(its_dev->event_map.col_map); +- kfree(its_dev->itt); ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz)); ++ else ++ kfree(its_dev->itt); ++ + kfree(its_dev); + } + +@@ -5078,6 +5134,7 @@ static int __init its_probe_one(struct its_node *its) + struct page *page; + u32 ctlr; + int err; ++ gfp_t gfp_flags; + + its_enable_quirks(its); + +@@ -5111,7 +5168,10 @@ static int __init its_probe_one(struct its_node *its) + } + } + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, ++ gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; ++ page = alloc_pages_node(its->numa_node, gfp_flags, + get_order(ITS_CMD_QUEUE_SZ)); + if (!page) { + err = -ENOMEM; +@@ -5140,6 +5200,11 @@ static int __init its_probe_one(struct its_node *its) + if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) + tmp &= ~GITS_CBASER_SHAREABILITY_MASK; + ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || ++ of_machine_is_compatible("rockchip,rk3588")) ++ tmp &= ~GITS_CBASER_SHAREABILITY_MASK; ++ + if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { + if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { + /* +-- +Armbian + diff --git a/kernel.patches/0012-fix-initial-PERST-GPIO-value.patch b/kernel.patches/0012-fix-initial-PERST-GPIO-value.patch new file mode 100644 index 0000000..8212b62 --- /dev/null +++ b/kernel.patches/0012-fix-initial-PERST-GPIO-value.patch @@ -0,0 +1,30 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: yangchaohong <45483831+yangchaohong@users.noreply.github.com> +Date: Wed, 1 May 2024 08:30:43 +0100 +Subject: [ARCHEOLOGY] Fix PCIe for RK35xx+Fix ROCK5A PCIe device tree + +> X-Git-Archeology: - Revision b1f648ee755de73a922a33d6a432f310ea4ff3e0: https://github.com/armbian/build/commit/b1f648ee755de73a922a33d6a432f310ea4ff3e0 +> X-Git-Archeology: Date: Wed, 01 May 2024 08:30:43 +0100 +> X-Git-Archeology: From: yangchaohong <45483831+yangchaohong@users.noreply.github.com> +> X-Git-Archeology: Subject: Fix PCIe for RK35xx+Fix ROCK5A PCIe device tree +> X-Git-Archeology: +--- + drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c +index 111111111111..222222222222 100644 +--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c ++++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c +@@ -240,7 +240,7 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev, + return PTR_ERR(rockchip->apb_base); + + rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", +- GPIOD_OUT_HIGH); ++ GPIOD_OUT_LOW); + if (IS_ERR(rockchip->rst_gpio)) + return PTR_ERR(rockchip->rst_gpio); + +-- +Armbian + diff --git a/kernel.patches/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch b/kernel.patches/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch new file mode 100644 index 0000000..502bd2a --- /dev/null +++ b/kernel.patches/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch @@ -0,0 +1,758 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 6 May 2024 13:36:32 +0400 +Subject: arm64: dts: rockchip: add thermal zones information on RK3588 + +This includes the necessary device tree data to allow thermal +monitoring on RK3588(s) using the on-chip TSADC device, along with +trip points for automatic thermal management. + +Each of the CPU clusters (one for the little cores and two for +the big cores) get a passive cooling trip point at 85C, which +will trigger DVFS throttling of the respective cluster upon +reaching a high temperature condition. + +All zones also have a critical trip point at 115C, which will +trigger a reset. + +Signed-off-by: Alexey Charkov +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 147 ++++++++++ + 1 file changed, 147 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + / { + compatible = "rockchip,rk3588"; +@@ -2368,6 +2369,152 @@ pwm15: pwm@febf0030 { + status = "disabled"; + }; + ++ thermal_zones: thermal-zones { ++ /* sensor near the center of the SoC */ ++ package_thermal: package-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 0>; ++ ++ trips { ++ package_crit: package-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ /* sensor between A76 cores 0 and 1 */ ++ bigcore0_thermal: bigcore0-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 1>; ++ ++ trips { ++ bigcore0_alert: bigcore0-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ bigcore0_crit: bigcore0-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ cooling-maps { ++ map0 { ++ trip = <&bigcore0_alert>; ++ cooling-device = ++ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ /* sensor between A76 cores 2 and 3 */ ++ bigcore2_thermal: bigcore2-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 2>; ++ ++ trips { ++ bigcore2_alert: bigcore2-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ bigcore2_crit: bigcore2-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ cooling-maps { ++ map0 { ++ trip = <&bigcore2_alert>; ++ cooling-device = ++ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ /* sensor between the four A55 cores */ ++ little_core_thermal: littlecore-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 3>; ++ ++ trips { ++ littlecore_alert: littlecore-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ littlecore_crit: littlecore-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ cooling-maps { ++ map0 { ++ trip = <&littlecore_alert>; ++ cooling-device = ++ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ /* sensor near the PD_CENTER power domain */ ++ center_thermal: center-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 4>; ++ ++ trips { ++ center_crit: center-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gpu_thermal: gpu-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 5>; ++ ++ trips { ++ gpu_crit: gpu-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ npu_thermal: npu-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsadc 6>; ++ ++ trips { ++ npu_crit: npu-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 6 May 2024 13:36:33 +0400 +Subject: arm64: dts: rockchip: enable thermal management on all RK3588 boards + +This enables the on-chip thermal monitoring sensor (TSADC) on all +RK3588(s) boards that don't have it enabled yet. It provides temperature +monitoring for the SoC and emergency thermal shutdowns, and is thus +important to have in place before CPU DVFS is enabled, as high CPU +operating performance points can overheat the chip quickly in the +absence of thermal management. + +Signed-off-by: Alexey Charkov +--- + arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++ + arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++ + arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++ + arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++ + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ + arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++ + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++ + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++ + 8 files changed, 32 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +@@ -673,6 +673,10 @@ regulator-state-mem { + }; + }; + ++&tsadc { ++ status = "okay"; ++}; ++ + &u2phy0 { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +@@ -466,3 +466,7 @@ regulator-state-mem { + }; + }; + }; ++ ++&tsadc { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -1131,6 +1131,10 @@ &sata0 { + status = "okay"; + }; + ++&tsadc { ++ status = "okay"; ++}; ++ + &u2phy0 { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +@@ -376,6 +376,10 @@ &sdmmc { + status = "okay"; + }; + ++&tsadc { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -743,6 +743,10 @@ regulator-state-mem { + }; + }; + ++&tsadc { ++ status = "okay"; ++}; ++ + &uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +@@ -648,6 +648,10 @@ regulator-state-mem { + }; + }; + ++&tsadc { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -601,6 +601,10 @@ regulator-state-mem { + }; + }; + ++&tsadc { ++ status = "okay"; ++}; ++ + &uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -699,6 +699,10 @@ regulator-state-mem { + }; + }; + ++&tsadc { ++ status = "okay"; ++}; ++ + &u2phy0 { + status = "okay"; + }; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 6 May 2024 13:36:34 +0400 +Subject: arm64: dts: rockchip: add passive GPU cooling on RK3588 + +As the GPU support on RK3588 has been merged upstream, along with OPP +values, add a corresponding cooling map for passive cooling using the GPU. + +Signed-off-by: Alexey Charkov +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 14 +++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -2487,17 +2487,29 @@ center_crit: center-crit { + }; + + gpu_thermal: gpu-thermal { +- polling-delay-passive = <0>; ++ polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { ++ gpu_alert: gpu-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; ++ cooling-maps { ++ map0 { ++ trip = <&gpu_alert>; ++ cooling-device = ++ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; + }; + + npu_thermal: npu-thermal { +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 6 May 2024 13:36:36 +0400 +Subject: arm64: dts: rockchip: Add CPU/memory regulator coupling for RK3588 + +RK3588 chips allow for their CPU cores to be powered by a different +supply vs. their corresponding memory interfaces, and two of the +boards currently upstream do that (EVB1 and QuartzPro64). + +The voltage of the memory interface though has to match that of the +CPU cores that use it, which downstream kernels achieve by the means +of a custom cpufreq driver which adjusts both at the same time. + +It seems that regulator coupling is a more appropriate generic +interface for it, so this patch introduces coupling to affected +device trees to ensure that memory interface voltage is also updated +whenever cpufreq switches between CPU OPPs. + +Note that other boards, such as Radxa Rock 5B, define both the CPU +and memory interface regulators as aliases to the same DT node, so +this doesn't apply there. + +Signed-off-by: Alexey Charkov +--- + arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 12 ++++++++++ + arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 12 ++++++++++ + 2 files changed, 24 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -878,6 +878,8 @@ regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; +@@ -890,6 +892,8 @@ regulator-state-mem { + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; +@@ -902,6 +906,8 @@ regulator-state-mem { + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; +@@ -926,6 +932,8 @@ regulator-state-mem { + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_big1_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; +@@ -939,6 +947,8 @@ regulator-state-mem { + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_big0_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; +@@ -963,6 +973,8 @@ regulator-state-mem { + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_lit_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +@@ -833,6 +833,8 @@ vdd_cpu_big1_s0: dcdc-reg1 { + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; +@@ -846,6 +848,8 @@ vdd_cpu_big0_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; +@@ -859,6 +863,8 @@ vdd_cpu_lit_s0: dcdc-reg3 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; +@@ -885,6 +891,8 @@ vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_big1_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; +@@ -899,6 +907,8 @@ vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_big0_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; +@@ -925,6 +935,8 @@ vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-always-on; + regulator-boot-on; ++ regulator-coupled-with = <&vdd_cpu_lit_s0>; ++ regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 6 May 2024 13:36:37 +0400 +Subject: arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 + +By default the CPUs on RK3588 start up in a conservative performance +mode. Add frequency and voltage mappings to the device tree to enable +dynamic scaling via cpufreq. + +OPP values are adapted from Radxa's downstream kernel for Rock 5B [1], +stripping them down to the minimum frequency and voltage combinations +as expected by the generic upstream cpufreq-dt driver, and also dropping +those OPPs that don't differ in voltage but only in frequency (keeping +the top frequency OPP in each case). + +Note that this patch ignores voltage scaling for the CPU memory +interface which the downstream kernel does through a custom cpufreq +driver, and which is why the downstream version has two sets of voltage +values for each OPP (the second one being meant for the memory +interface supply regulator). This is done instead via regulator +coupling between CPU and memory interface supplies on affected boards. + +This has been tested on Rock 5B with u-boot 2023.11 compiled from +Collabora's integration tree [2] with binary bl31 and appears to be +stable both under active cooling and passive cooling (with throttling) + +[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot + +Signed-off-by: Alexey Charkov +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 122 ++++++++++ + 1 file changed, 122 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -97,6 +97,7 @@ cpu_l0: cpu@0 { + clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates = <816000000>; ++ operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; +@@ -116,6 +117,7 @@ cpu_l1: cpu@100 { + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; +@@ -135,6 +137,7 @@ cpu_l2: cpu@200 { + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; +@@ -154,6 +157,7 @@ cpu_l3: cpu@300 { + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; +@@ -175,6 +179,7 @@ cpu_b0: cpu@400 { + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <816000000>; ++ operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -194,6 +199,7 @@ cpu_b1: cpu@500 { + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; ++ operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -215,6 +221,7 @@ cpu_b2: cpu@600 { + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>; ++ operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -234,6 +241,7 @@ cpu_b3: cpu@700 { + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; ++ operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -348,6 +356,120 @@ l3_cache: l3-cache { + }; + }; + ++ cluster0_opp_table: opp-table-cluster0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <675000 675000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <712500 712500 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <762500 762500 950000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <850000 850000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <950000 950000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster1_opp_table: opp-table-cluster1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <725000 725000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <762500 762500 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <850000 850000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <925000 925000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <987500 987500 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2400000000 { ++ opp-hz = /bits/ 64 <2400000000>; ++ opp-microvolt = <1000000 1000000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster2_opp_table: opp-table-cluster2 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <725000 725000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <762500 762500 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <850000 850000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <925000 925000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <987500 987500 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2400000000 { ++ opp-hz = /bits/ 64 <2400000000>; ++ opp-microvolt = <1000000 1000000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; +-- +Armbian + diff --git a/kernel.patches/0024-RK3588-Add-Crypto-Support.patch b/kernel.patches/0024-RK3588-Add-Crypto-Support.patch new file mode 100644 index 0000000..e11ce51 --- /dev/null +++ b/kernel.patches/0024-RK3588-Add-Crypto-Support.patch @@ -0,0 +1,2328 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 7 Nov 2023 15:55:27 +0000 +Subject: dt-bindings: crypto: add support for rockchip,crypto-rk3588 + +Add device tree binding documentation for the Rockchip cryptographic +offloader V2. + +Signed-off-by: Corentin Labbe +--- + Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml | 65 ++++++++++ + 1 file changed, 65 insertions(+) + +diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml +@@ -0,0 +1,65 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/crypto/rockchip,rk3588-crypto.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip cryptographic offloader V2 ++ ++maintainers: ++ - Corentin Labbe ++ ++properties: ++ compatible: ++ enum: ++ - rockchip,rk3568-crypto ++ - rockchip,rk3588-crypto ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 3 ++ ++ clock-names: ++ items: ++ - const: core ++ - const: a ++ - const: h ++ ++ resets: ++ minItems: 1 ++ ++ reset-names: ++ items: ++ - const: core ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ crypto@fe370000 { ++ compatible = "rockchip,rk3588-crypto"; ++ reg = <0xfe370000 0x4000>; ++ interrupts = ; ++ clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>, ++ <&scmi_clk SCMI_HCLK_SECURE_NS>; ++ clock-names = "core", "a", "h"; ++ resets = <&scmi_reset SRST_CRYPTO_CORE>; ++ reset-names = "core"; ++ }; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 7 Nov 2023 15:55:29 +0000 +Subject: ARM64: dts: rk3588: add crypto node + +The rk3588 has a crypto IP handled by the rk3588 crypto driver so adds a +node for it. + +Signed-off-by: Corentin Labbe +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1923,6 +1923,18 @@ sdhci: mmc@fe2e0000 { + status = "disabled"; + }; + ++ crypto: crypto@fe370000 { ++ compatible = "rockchip,rk3588-crypto"; ++ reg = <0x0 0xfe370000 0x0 0x2000>; ++ interrupts = ; ++ clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>, ++ <&scmi_clk SCMI_HCLK_SECURE_NS>; ++ clock-names = "core", "aclk", "hclk"; ++ resets = <&scmi_reset SRST_CRYPTO_CORE>; ++ reset-names = "core"; ++ status = "okay"; ++ }; ++ + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 7 Nov 2023 15:55:30 +0000 +Subject: ARM64: dts: rk356x: add crypto node + +Both RK3566 and RK3568 have a crypto IP handled by the rk3588 crypto driver so adds a +node for it. + +Tested-by: Ricardo Pardini +Signed-off-by: Corentin Labbe +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1112,6 +1112,18 @@ sdhci: mmc@fe310000 { + status = "disabled"; + }; + ++ crypto: crypto@fe380000 { ++ compatible = "rockchip,rk3568-crypto"; ++ reg = <0x0 0xfe380000 0x0 0x2000>; ++ interrupts = ; ++ clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, ++ <&cru CLK_CRYPTO_NS_CORE>; ++ clock-names = "aclk", "hclk", "core"; ++ resets = <&cru SRST_CRYPTO_NS_CORE>; ++ reset-names = "core"; ++ status = "okay"; ++ }; ++ + i2s0_8ch: i2s@fe400000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe400000 0x0 0x1000>; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 7 Nov 2023 15:55:31 +0000 +Subject: reset: rockchip: secure reset must be used by SCMI + +While working on the rk3588 crypto driver, I loose lot of time +understanding why resetting the IP failed. +This is due to RK3588_SECURECRU_RESET_OFFSET being in the secure world, +so impossible to operate on it from the kernel. +All resets in this block must be handled via SCMI call. + +Signed-off-by: Corentin Labbe +--- + drivers/clk/rockchip/rst-rk3588.c | 42 ------ + include/dt-bindings/reset/rockchip,rk3588-cru.h | 68 +++++----- + 2 files changed, 34 insertions(+), 76 deletions(-) + +diff --git a/drivers/clk/rockchip/rst-rk3588.c b/drivers/clk/rockchip/rst-rk3588.c +index 111111111111..222222222222 100644 +--- a/drivers/clk/rockchip/rst-rk3588.c ++++ b/drivers/clk/rockchip/rst-rk3588.c +@@ -16,9 +16,6 @@ + /* 0xFD7C8000 + 0x0A00 */ + #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) + +-/* 0xFD7D0000 + 0x0A00 */ +-#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) +- + /* 0xFD7F0000 + 0x0A00 */ + #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) + +@@ -807,45 +804,6 @@ static const int rk3588_register_offset[] = { + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4), + RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5), + RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6), +- +- /* SECURECRU_SOFTRST_CON00 */ +- RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10), +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11), +- RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12), +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13), +- RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14), +- RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15), +- +- /* SECURECRU_SOFTRST_CON01 */ +- RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0), +- RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1), +- RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2), +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3), +- RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9), +- RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10), +- RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11), +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12), +- RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13), +- RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14), +- RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15), +- +- /* SECURECRU_SOFTRST_CON02 */ +- RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0), +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1), +- RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2), +- RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3), +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5), +- RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14), +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15), +- +- /* SECURECRU_SOFTRST_CON03 */ +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0), +- RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1), +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2), +- RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3), +- RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4), +- RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5), +- RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6), + }; + + void rk3588_rst_init(struct device_node *np, void __iomem *reg_base) +diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h +index 111111111111..222222222222 100644 +--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h ++++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h +@@ -716,40 +716,40 @@ + #define SRST_P_GPIO0 627 + #define SRST_GPIO0 628 + +-#define SRST_A_SECURE_NS_BIU 629 +-#define SRST_H_SECURE_NS_BIU 630 +-#define SRST_A_SECURE_S_BIU 631 +-#define SRST_H_SECURE_S_BIU 632 +-#define SRST_P_SECURE_S_BIU 633 +-#define SRST_CRYPTO_CORE 634 +- +-#define SRST_CRYPTO_PKA 635 +-#define SRST_CRYPTO_RNG 636 +-#define SRST_A_CRYPTO 637 +-#define SRST_H_CRYPTO 638 +-#define SRST_KEYLADDER_CORE 639 +-#define SRST_KEYLADDER_RNG 640 +-#define SRST_A_KEYLADDER 641 +-#define SRST_H_KEYLADDER 642 +-#define SRST_P_OTPC_S 643 +-#define SRST_OTPC_S 644 +-#define SRST_WDT_S 645 +- +-#define SRST_T_WDT_S 646 +-#define SRST_H_BOOTROM 647 +-#define SRST_A_DCF 648 +-#define SRST_P_DCF 649 +-#define SRST_H_BOOTROM_NS 650 +-#define SRST_P_KEYLADDER 651 +-#define SRST_H_TRNG_S 652 +- +-#define SRST_H_TRNG_NS 653 +-#define SRST_D_SDMMC_BUFFER 654 +-#define SRST_H_SDMMC 655 +-#define SRST_H_SDMMC_BUFFER 656 +-#define SRST_SDMMC 657 +-#define SRST_P_TRNG_CHK 658 +-#define SRST_TRNG_S 659 ++#define SRST_A_SECURE_NS_BIU 10 ++#define SRST_H_SECURE_NS_BIU 11 ++#define SRST_A_SECURE_S_BIU 12 ++#define SRST_H_SECURE_S_BIU 13 ++#define SRST_P_SECURE_S_BIU 14 ++#define SRST_CRYPTO_CORE 15 ++ ++#define SRST_CRYPTO_PKA 16 ++#define SRST_CRYPTO_RNG 17 ++#define SRST_A_CRYPTO 18 ++#define SRST_H_CRYPTO 19 ++#define SRST_KEYLADDER_CORE 25 ++#define SRST_KEYLADDER_RNG 26 ++#define SRST_A_KEYLADDER 27 ++#define SRST_H_KEYLADDER 28 ++#define SRST_P_OTPC_S 29 ++#define SRST_OTPC_S 30 ++#define SRST_WDT_S 31 ++ ++#define SRST_T_WDT_S 32 ++#define SRST_H_BOOTROM 33 ++#define SRST_A_DCF 34 ++#define SRST_P_DCF 35 ++#define SRST_H_BOOTROM_NS 37 ++#define SRST_P_KEYLADDER 46 ++#define SRST_H_TRNG_S 47 ++ ++#define SRST_H_TRNG_NS 48 ++#define SRST_D_SDMMC_BUFFER 49 ++#define SRST_H_SDMMC 50 ++#define SRST_H_SDMMC_BUFFER 51 ++#define SRST_SDMMC 52 ++#define SRST_P_TRNG_CHK 53 ++#define SRST_TRNG_S 54 + + #define SRST_A_HDMIRX_BIU 660 + +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 7 Nov 2023 15:55:32 +0000 +Subject: crypto: rockchip: add rk3588 driver + +RK3588 have a new crypto IP, this patch adds basic support for it. +Only hashes and cipher are handled for the moment. + +Signed-off-by: Corentin Labbe +--- + drivers/crypto/Kconfig | 29 + + drivers/crypto/rockchip/Makefile | 5 + + drivers/crypto/rockchip/rk2_crypto.c | 739 ++++++++++ + drivers/crypto/rockchip/rk2_crypto.h | 246 +++ + drivers/crypto/rockchip/rk2_crypto_ahash.c | 344 +++++ + drivers/crypto/rockchip/rk2_crypto_skcipher.c | 576 ++++++++ + 6 files changed, 1939 insertions(+) + +diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig +index 111111111111..222222222222 100644 +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -653,6 +653,35 @@ config CRYPTO_DEV_TEGRA + Select this to enable Tegra Security Engine which accelerates various + AES encryption/decryption and HASH algorithms. + ++config CRYPTO_DEV_ROCKCHIP2 ++ tristate "Rockchip's cryptographic offloader V2" ++ depends on OF && ARCH_ROCKCHIP ++ depends on PM ++ select CRYPTO_ECB ++ select CRYPTO_CBC ++ select CRYPTO_AES ++ select CRYPTO_MD5 ++ select CRYPTO_SHA1 ++ select CRYPTO_SHA256 ++ select CRYPTO_SHA512 ++ select CRYPTO_SM3_GENERIC ++ select CRYPTO_HASH ++ select CRYPTO_SKCIPHER ++ select CRYPTO_ENGINE ++ ++ help ++ This driver interfaces with the hardware crypto offloader present ++ on RK3566, RK3568 and RK3588. ++ ++config CRYPTO_DEV_ROCKCHIP2_DEBUG ++ bool "Enable Rockchip V2 crypto stats" ++ depends on CRYPTO_DEV_ROCKCHIP2 ++ depends on DEBUG_FS ++ help ++ Say y to enable Rockchip crypto debug stats. ++ This will create /sys/kernel/debug/rk3588_crypto/stats for displaying ++ the number of requests per algorithm and other internal stats. ++ + config CRYPTO_DEV_ZYNQMP_AES + tristate "Support for Xilinx ZynqMP AES hw accelerator" + depends on ZYNQMP_FIRMWARE || COMPILE_TEST +diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/crypto/rockchip/Makefile ++++ b/drivers/crypto/rockchip/Makefile +@@ -3,3 +3,8 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o + rk_crypto-objs := rk3288_crypto.o \ + rk3288_crypto_skcipher.o \ + rk3288_crypto_ahash.o ++ ++obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP2) += rk_crypto2.o ++rk_crypto2-objs := rk2_crypto.o \ ++ rk2_crypto_skcipher.o \ ++ rk2_crypto_ahash.o +diff --git a/drivers/crypto/rockchip/rk2_crypto.c b/drivers/crypto/rockchip/rk2_crypto.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/crypto/rockchip/rk2_crypto.c +@@ -0,0 +1,739 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * hardware cryptographic offloader for RK3568/RK3588 SoC ++ * ++ * Copyright (c) 2022-2023, Corentin Labbe ++ */ ++ ++#include "rk2_crypto.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct rockchip_ip rocklist = { ++ .dev_list = LIST_HEAD_INIT(rocklist.dev_list), ++ .lock = __SPIN_LOCK_UNLOCKED(rocklist.lock), ++}; ++ ++struct rk2_crypto_dev *get_rk2_crypto(void) ++{ ++ struct rk2_crypto_dev *first; ++ ++ spin_lock(&rocklist.lock); ++ first = list_first_entry_or_null(&rocklist.dev_list, ++ struct rk2_crypto_dev, list); ++ list_rotate_left(&rocklist.dev_list); ++ spin_unlock(&rocklist.lock); ++ return first; ++} ++ ++static const struct rk2_variant rk3568_variant = { ++ .num_clks = 3, ++}; ++ ++static const struct rk2_variant rk3588_variant = { ++ .num_clks = 3, ++}; ++ ++static int rk2_crypto_get_clks(struct rk2_crypto_dev *dev) ++{ ++ int i, j, err; ++ unsigned long cr; ++ ++ dev->num_clks = devm_clk_bulk_get_all(dev->dev, &dev->clks); ++ if (dev->num_clks < dev->variant->num_clks) { ++ dev_err(dev->dev, "Missing clocks, got %d instead of %d\n", ++ dev->num_clks, dev->variant->num_clks); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < dev->num_clks; i++) { ++ cr = clk_get_rate(dev->clks[i].clk); ++ for (j = 0; j < ARRAY_SIZE(dev->variant->rkclks); j++) { ++ if (dev->variant->rkclks[j].max == 0) ++ continue; ++ if (strcmp(dev->variant->rkclks[j].name, dev->clks[i].id)) ++ continue; ++ if (cr > dev->variant->rkclks[j].max) { ++ err = clk_set_rate(dev->clks[i].clk, ++ dev->variant->rkclks[j].max); ++ if (err) ++ dev_err(dev->dev, "Fail downclocking %s from %lu to %lu\n", ++ dev->variant->rkclks[j].name, cr, ++ dev->variant->rkclks[j].max); ++ else ++ dev_info(dev->dev, "Downclocking %s from %lu to %lu\n", ++ dev->variant->rkclks[j].name, cr, ++ dev->variant->rkclks[j].max); ++ } ++ } ++ } ++ return 0; ++} ++ ++static int rk2_crypto_enable_clk(struct rk2_crypto_dev *dev) ++{ ++ int err; ++ ++ err = clk_bulk_prepare_enable(dev->num_clks, dev->clks); ++ if (err) ++ dev_err(dev->dev, "Could not enable clock clks\n"); ++ ++ return err; ++} ++ ++static void rk2_crypto_disable_clk(struct rk2_crypto_dev *dev) ++{ ++ clk_bulk_disable_unprepare(dev->num_clks, dev->clks); ++} ++ ++/* ++ * Power management strategy: The device is suspended until a request ++ * is handled. For avoiding suspend/resume yoyo, the autosuspend is set to 2s. ++ */ ++static int rk2_crypto_pm_suspend(struct device *dev) ++{ ++ struct rk2_crypto_dev *rkdev = dev_get_drvdata(dev); ++ ++ rk2_crypto_disable_clk(rkdev); ++ reset_control_assert(rkdev->rst); ++ ++ return 0; ++} ++ ++static int rk2_crypto_pm_resume(struct device *dev) ++{ ++ struct rk2_crypto_dev *rkdev = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = rk2_crypto_enable_clk(rkdev); ++ if (ret) ++ return ret; ++ ++ reset_control_deassert(rkdev->rst); ++ return 0; ++} ++ ++static const struct dev_pm_ops rk2_crypto_pm_ops = { ++ SET_RUNTIME_PM_OPS(rk2_crypto_pm_suspend, rk2_crypto_pm_resume, NULL) ++}; ++ ++static int rk2_crypto_pm_init(struct rk2_crypto_dev *rkdev) ++{ ++ int err; ++ ++ pm_runtime_use_autosuspend(rkdev->dev); ++ pm_runtime_set_autosuspend_delay(rkdev->dev, 2000); ++ ++ err = pm_runtime_set_suspended(rkdev->dev); ++ if (err) ++ return err; ++ pm_runtime_enable(rkdev->dev); ++ return err; ++} ++ ++static void rk2_crypto_pm_exit(struct rk2_crypto_dev *rkdev) ++{ ++ pm_runtime_disable(rkdev->dev); ++} ++ ++static irqreturn_t rk2_crypto_irq_handle(int irq, void *dev_id) ++{ ++ struct rk2_crypto_dev *rkc = platform_get_drvdata(dev_id); ++ u32 v; ++ ++ v = readl(rkc->reg + RK2_CRYPTO_DMA_INT_ST); ++ writel(v, rkc->reg + RK2_CRYPTO_DMA_INT_ST); ++ ++ rkc->status = 1; ++ if (v & 0xF8) { ++ dev_warn(rkc->dev, "DMA Error\n"); ++ rkc->status = 0; ++ } ++ complete(&rkc->complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct rk2_crypto_template rk2_crypto_algs[] = { ++ { ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, ++ .rk2_mode = RK2_CRYPTO_AES_ECB, ++ .alg.skcipher.base = { ++ .base.cra_name = "ecb(aes)", ++ .base.cra_driver_name = "ecb-aes-rk2", ++ .base.cra_priority = 300, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, ++ .base.cra_blocksize = AES_BLOCK_SIZE, ++ .base.cra_ctxsize = sizeof(struct rk2_cipher_ctx), ++ .base.cra_alignmask = 0x0f, ++ .base.cra_module = THIS_MODULE, ++ ++ .init = rk2_cipher_tfm_init, ++ .exit = rk2_cipher_tfm_exit, ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = rk2_aes_setkey, ++ .encrypt = rk2_skcipher_encrypt, ++ .decrypt = rk2_skcipher_decrypt, ++ }, ++ .alg.skcipher.op = { ++ .do_one_request = rk2_cipher_run, ++ }, ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, ++ .rk2_mode = RK2_CRYPTO_AES_CBC, ++ .alg.skcipher.base = { ++ .base.cra_name = "cbc(aes)", ++ .base.cra_driver_name = "cbc-aes-rk2", ++ .base.cra_priority = 300, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, ++ .base.cra_blocksize = AES_BLOCK_SIZE, ++ .base.cra_ctxsize = sizeof(struct rk2_cipher_ctx), ++ .base.cra_alignmask = 0x0f, ++ .base.cra_module = THIS_MODULE, ++ ++ .init = rk2_cipher_tfm_init, ++ .exit = rk2_cipher_tfm_exit, ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .ivsize = AES_BLOCK_SIZE, ++ .setkey = rk2_aes_setkey, ++ .encrypt = rk2_skcipher_encrypt, ++ .decrypt = rk2_skcipher_decrypt, ++ }, ++ .alg.skcipher.op = { ++ .do_one_request = rk2_cipher_run, ++ }, ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, ++ .rk2_mode = RK2_CRYPTO_AES_XTS, ++ .is_xts = true, ++ .alg.skcipher.base = { ++ .base.cra_name = "xts(aes)", ++ .base.cra_driver_name = "xts-aes-rk2", ++ .base.cra_priority = 300, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, ++ .base.cra_blocksize = AES_BLOCK_SIZE, ++ .base.cra_ctxsize = sizeof(struct rk2_cipher_ctx), ++ .base.cra_alignmask = 0x0f, ++ .base.cra_module = THIS_MODULE, ++ ++ .init = rk2_cipher_tfm_init, ++ .exit = rk2_cipher_tfm_exit, ++ .min_keysize = AES_MIN_KEY_SIZE * 2, ++ .max_keysize = AES_MAX_KEY_SIZE * 2, ++ .ivsize = AES_BLOCK_SIZE, ++ .setkey = rk2_aes_xts_setkey, ++ .encrypt = rk2_skcipher_encrypt, ++ .decrypt = rk2_skcipher_decrypt, ++ }, ++ .alg.skcipher.op = { ++ .do_one_request = rk2_cipher_run, ++ }, ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk2_mode = RK2_CRYPTO_MD5, ++ .alg.hash.base = { ++ .init = rk2_ahash_init, ++ .update = rk2_ahash_update, ++ .final = rk2_ahash_final, ++ .finup = rk2_ahash_finup, ++ .export = rk2_ahash_export, ++ .import = rk2_ahash_import, ++ .digest = rk2_ahash_digest, ++ .init_tfm = rk2_hash_init_tfm, ++ .exit_tfm = rk2_hash_exit_tfm, ++ .halg = { ++ .digestsize = MD5_DIGEST_SIZE, ++ .statesize = sizeof(struct md5_state), ++ .base = { ++ .cra_name = "md5", ++ .cra_driver_name = "rk2-md5", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = MD5_HMAC_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), ++ .cra_module = THIS_MODULE, ++ } ++ } ++ }, ++ .alg.hash.op = { ++ .do_one_request = rk2_hash_run, ++ }, ++ ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk2_mode = RK2_CRYPTO_SHA1, ++ .alg.hash.base = { ++ .init = rk2_ahash_init, ++ .update = rk2_ahash_update, ++ .final = rk2_ahash_final, ++ .finup = rk2_ahash_finup, ++ .export = rk2_ahash_export, ++ .import = rk2_ahash_import, ++ .digest = rk2_ahash_digest, ++ .init_tfm = rk2_hash_init_tfm, ++ .exit_tfm = rk2_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA1_DIGEST_SIZE, ++ .statesize = sizeof(struct sha1_state), ++ .base = { ++ .cra_name = "sha1", ++ .cra_driver_name = "rk2-sha1", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA1_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), ++ .cra_module = THIS_MODULE, ++ } ++ } ++ }, ++ .alg.hash.op = { ++ .do_one_request = rk2_hash_run, ++ }, ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk2_mode = RK2_CRYPTO_SHA256, ++ .alg.hash.base = { ++ .init = rk2_ahash_init, ++ .update = rk2_ahash_update, ++ .final = rk2_ahash_final, ++ .finup = rk2_ahash_finup, ++ .export = rk2_ahash_export, ++ .import = rk2_ahash_import, ++ .digest = rk2_ahash_digest, ++ .init_tfm = rk2_hash_init_tfm, ++ .exit_tfm = rk2_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA256_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "sha256", ++ .cra_driver_name = "rk2-sha256", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA256_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), ++ .cra_module = THIS_MODULE, ++ } ++ } ++ }, ++ .alg.hash.op = { ++ .do_one_request = rk2_hash_run, ++ }, ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk2_mode = RK2_CRYPTO_SHA384, ++ .alg.hash.base = { ++ .init = rk2_ahash_init, ++ .update = rk2_ahash_update, ++ .final = rk2_ahash_final, ++ .finup = rk2_ahash_finup, ++ .export = rk2_ahash_export, ++ .import = rk2_ahash_import, ++ .digest = rk2_ahash_digest, ++ .init_tfm = rk2_hash_init_tfm, ++ .exit_tfm = rk2_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA384_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "sha384", ++ .cra_driver_name = "rk2-sha384", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA384_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), ++ .cra_module = THIS_MODULE, ++ } ++ } ++ }, ++ .alg.hash.op = { ++ .do_one_request = rk2_hash_run, ++ }, ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk2_mode = RK2_CRYPTO_SHA512, ++ .alg.hash.base = { ++ .init = rk2_ahash_init, ++ .update = rk2_ahash_update, ++ .final = rk2_ahash_final, ++ .finup = rk2_ahash_finup, ++ .export = rk2_ahash_export, ++ .import = rk2_ahash_import, ++ .digest = rk2_ahash_digest, ++ .init_tfm = rk2_hash_init_tfm, ++ .exit_tfm = rk2_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA512_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "sha512", ++ .cra_driver_name = "rk2-sha512", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA512_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), ++ .cra_module = THIS_MODULE, ++ } ++ } ++ }, ++ .alg.hash.op = { ++ .do_one_request = rk2_hash_run, ++ }, ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk2_mode = RK2_CRYPTO_SM3, ++ .alg.hash.base = { ++ .init = rk2_ahash_init, ++ .update = rk2_ahash_update, ++ .final = rk2_ahash_final, ++ .finup = rk2_ahash_finup, ++ .export = rk2_ahash_export, ++ .import = rk2_ahash_import, ++ .digest = rk2_ahash_digest, ++ .init_tfm = rk2_hash_init_tfm, ++ .exit_tfm = rk2_hash_exit_tfm, ++ .halg = { ++ .digestsize = SM3_DIGEST_SIZE, ++ .statesize = sizeof(struct sm3_state), ++ .base = { ++ .cra_name = "sm3", ++ .cra_driver_name = "rk2-sm3", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SM3_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk2_ahash_ctx), ++ .cra_module = THIS_MODULE, ++ } ++ } ++ }, ++ .alg.hash.op = { ++ .do_one_request = rk2_hash_run, ++ }, ++ }, ++}; ++ ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG ++static int rk2_crypto_debugfs_stats_show(struct seq_file *seq, void *v) ++{ ++ struct rk2_crypto_dev *rkc; ++ unsigned int i; ++ ++ spin_lock(&rocklist.lock); ++ list_for_each_entry(rkc, &rocklist.dev_list, list) { ++ seq_printf(seq, "%s %s requests: %lu\n", ++ dev_driver_string(rkc->dev), dev_name(rkc->dev), ++ rkc->nreq); ++ } ++ spin_unlock(&rocklist.lock); ++ ++ for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) { ++ if (!rk2_crypto_algs[i].dev) ++ continue; ++ switch (rk2_crypto_algs[i].type) { ++ case CRYPTO_ALG_TYPE_SKCIPHER: ++ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n", ++ rk2_crypto_algs[i].alg.skcipher.base.base.cra_driver_name, ++ rk2_crypto_algs[i].alg.skcipher.base.base.cra_name, ++ rk2_crypto_algs[i].stat_req, rk2_crypto_algs[i].stat_fb); ++ seq_printf(seq, "\tfallback due to length: %lu\n", ++ rk2_crypto_algs[i].stat_fb_len); ++ seq_printf(seq, "\tfallback due to alignment: %lu\n", ++ rk2_crypto_algs[i].stat_fb_align); ++ seq_printf(seq, "\tfallback due to SGs: %lu\n", ++ rk2_crypto_algs[i].stat_fb_sgdiff); ++ break; ++ case CRYPTO_ALG_TYPE_AHASH: ++ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n", ++ rk2_crypto_algs[i].alg.hash.base.halg.base.cra_driver_name, ++ rk2_crypto_algs[i].alg.hash.base.halg.base.cra_name, ++ rk2_crypto_algs[i].stat_req, rk2_crypto_algs[i].stat_fb); ++ break; ++ } ++ } ++ return 0; ++} ++ ++static int rk2_crypto_debugfs_info_show(struct seq_file *seq, void *d) ++{ ++ struct rk2_crypto_dev *rkc; ++ u32 v; ++ ++ spin_lock(&rocklist.lock); ++ list_for_each_entry(rkc, &rocklist.dev_list, list) { ++ v = readl(rkc->reg + RK2_CRYPTO_CLK_CTL); ++ seq_printf(seq, "CRYPTO_CLK_CTL %x\n", v); ++ v = readl(rkc->reg + RK2_CRYPTO_RST_CTL); ++ seq_printf(seq, "CRYPTO_RST_CTL %x\n", v); ++ ++ v = readl(rkc->reg + CRYPTO_AES_VERSION); ++ seq_printf(seq, "CRYPTO_AES_VERSION %x\n", v); ++ if (v & BIT(17)) ++ seq_puts(seq, "AES 192\n"); ++ ++ v = readl(rkc->reg + CRYPTO_DES_VERSION); ++ seq_printf(seq, "CRYPTO_DES_VERSION %x\n", v); ++ v = readl(rkc->reg + CRYPTO_SM4_VERSION); ++ seq_printf(seq, "CRYPTO_SM4_VERSION %x\n", v); ++ v = readl(rkc->reg + CRYPTO_HASH_VERSION); ++ seq_printf(seq, "CRYPTO_HASH_VERSION %x\n", v); ++ v = readl(rkc->reg + CRYPTO_HMAC_VERSION); ++ seq_printf(seq, "CRYPTO_HMAC_VERSION %x\n", v); ++ v = readl(rkc->reg + CRYPTO_RNG_VERSION); ++ seq_printf(seq, "CRYPTO_RNG_VERSION %x\n", v); ++ v = readl(rkc->reg + CRYPTO_PKA_VERSION); ++ seq_printf(seq, "CRYPTO_PKA_VERSION %x\n", v); ++ v = readl(rkc->reg + CRYPTO_CRYPTO_VERSION); ++ seq_printf(seq, "CRYPTO_CRYPTO_VERSION %x\n", v); ++ } ++ spin_unlock(&rocklist.lock); ++ ++ return 0; ++} ++ ++DEFINE_SHOW_ATTRIBUTE(rk2_crypto_debugfs_stats); ++DEFINE_SHOW_ATTRIBUTE(rk2_crypto_debugfs_info); ++ ++#endif ++ ++static void register_debugfs(struct rk2_crypto_dev *crypto_dev) ++{ ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG ++ /* Ignore error of debugfs */ ++ rocklist.dbgfs_dir = debugfs_create_dir("rk2_crypto", NULL); ++ rocklist.dbgfs_stats = debugfs_create_file("stats", 0440, ++ rocklist.dbgfs_dir, ++ &rocklist, ++ &rk2_crypto_debugfs_stats_fops); ++ rocklist.dbgfs_stats = debugfs_create_file("info", 0440, ++ rocklist.dbgfs_dir, ++ &rocklist, ++ &rk2_crypto_debugfs_info_fops); ++#endif ++} ++ ++static int rk2_crypto_register(struct rk2_crypto_dev *rkc) ++{ ++ unsigned int i, k; ++ int err = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) { ++ rk2_crypto_algs[i].dev = rkc; ++ switch (rk2_crypto_algs[i].type) { ++ case CRYPTO_ALG_TYPE_SKCIPHER: ++ dev_info(rkc->dev, "Register %s as %s\n", ++ rk2_crypto_algs[i].alg.skcipher.base.base.cra_name, ++ rk2_crypto_algs[i].alg.skcipher.base.base.cra_driver_name); ++ err = crypto_engine_register_skcipher(&rk2_crypto_algs[i].alg.skcipher); ++ break; ++ case CRYPTO_ALG_TYPE_AHASH: ++ dev_info(rkc->dev, "Register %s as %s %d\n", ++ rk2_crypto_algs[i].alg.hash.base.halg.base.cra_name, ++ rk2_crypto_algs[i].alg.hash.base.halg.base.cra_driver_name, i); ++ err = crypto_engine_register_ahash(&rk2_crypto_algs[i].alg.hash); ++ break; ++ default: ++ dev_err(rkc->dev, "unknown algorithm\n"); ++ } ++ if (err) ++ goto err_cipher_algs; ++ } ++ return 0; ++ ++err_cipher_algs: ++ for (k = 0; k < i; k++) { ++ if (rk2_crypto_algs[k].type == CRYPTO_ALG_TYPE_SKCIPHER) ++ crypto_engine_unregister_skcipher(&rk2_crypto_algs[k].alg.skcipher); ++ else ++ crypto_engine_unregister_ahash(&rk2_crypto_algs[k].alg.hash); ++ } ++ return err; ++} ++ ++static void rk2_crypto_unregister(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(rk2_crypto_algs); i++) { ++ if (rk2_crypto_algs[i].type == CRYPTO_ALG_TYPE_SKCIPHER) ++ crypto_engine_unregister_skcipher(&rk2_crypto_algs[i].alg.skcipher); ++ else ++ crypto_engine_unregister_ahash(&rk2_crypto_algs[i].alg.hash); ++ } ++} ++ ++static const struct of_device_id crypto_of_id_table[] = { ++ { .compatible = "rockchip,rk3568-crypto", ++ .data = &rk3568_variant, ++ }, ++ { .compatible = "rockchip,rk3588-crypto", ++ .data = &rk3588_variant, ++ }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, crypto_of_id_table); ++ ++static int rk2_crypto_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rk2_crypto_dev *rkc, *first; ++ int err = 0; ++ ++ rkc = devm_kzalloc(&pdev->dev, sizeof(*rkc), GFP_KERNEL); ++ if (!rkc) { ++ err = -ENOMEM; ++ goto err_crypto; ++ } ++ ++ rkc->dev = &pdev->dev; ++ platform_set_drvdata(pdev, rkc); ++ ++ rkc->variant = of_device_get_match_data(&pdev->dev); ++ if (!rkc->variant) { ++ dev_err(&pdev->dev, "Missing variant\n"); ++ return -EINVAL; ++ } ++ ++ rkc->rst = devm_reset_control_array_get_exclusive(dev); ++ if (IS_ERR(rkc->rst)) { ++ err = PTR_ERR(rkc->rst); ++ dev_err(&pdev->dev, "Fail to get resets err=%d\n", err); ++ goto err_crypto; ++ } ++ ++ rkc->tl = dma_alloc_coherent(rkc->dev, ++ sizeof(struct rk2_crypto_lli) * MAX_LLI, ++ &rkc->t_phy, GFP_KERNEL); ++ if (!rkc->tl) { ++ dev_err(rkc->dev, "Cannot get DMA memory for task\n"); ++ err = -ENOMEM; ++ goto err_crypto; ++ } ++ ++ reset_control_assert(rkc->rst); ++ usleep_range(10, 20); ++ reset_control_deassert(rkc->rst); ++ ++ rkc->reg = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(rkc->reg)) { ++ err = PTR_ERR(rkc->reg); ++ dev_err(&pdev->dev, "Fail to get resources\n"); ++ goto err_crypto; ++ } ++ ++ err = rk2_crypto_get_clks(rkc); ++ if (err) ++ goto err_crypto; ++ ++ rkc->irq = platform_get_irq(pdev, 0); ++ if (rkc->irq < 0) { ++ dev_err(&pdev->dev, "control Interrupt is not available.\n"); ++ err = rkc->irq; ++ goto err_crypto; ++ } ++ ++ err = devm_request_irq(&pdev->dev, rkc->irq, ++ rk2_crypto_irq_handle, IRQF_SHARED, ++ "rk-crypto", pdev); ++ ++ if (err) { ++ dev_err(&pdev->dev, "irq request failed.\n"); ++ goto err_crypto; ++ } ++ ++ rkc->engine = crypto_engine_alloc_init(&pdev->dev, true); ++ crypto_engine_start(rkc->engine); ++ init_completion(&rkc->complete); ++ ++ err = rk2_crypto_pm_init(rkc); ++ if (err) ++ goto err_pm; ++ ++ err = pm_runtime_resume_and_get(&pdev->dev); ++ ++ spin_lock(&rocklist.lock); ++ first = list_first_entry_or_null(&rocklist.dev_list, ++ struct rk2_crypto_dev, list); ++ list_add_tail(&rkc->list, &rocklist.dev_list); ++ spin_unlock(&rocklist.lock); ++ ++ if (!first) { ++ dev_info(dev, "Registers crypto algos\n"); ++ err = rk2_crypto_register(rkc); ++ if (err) { ++ dev_err(dev, "Fail to register crypto algorithms"); ++ goto err_register_alg; ++ } ++ ++ register_debugfs(rkc); ++ } ++ ++ return 0; ++ ++err_register_alg: ++ rk2_crypto_pm_exit(rkc); ++err_pm: ++ crypto_engine_exit(rkc->engine); ++err_crypto: ++ dev_err(dev, "Crypto Accelerator not successfully registered\n"); ++ return err; ++} ++ ++static int rk2_crypto_remove(struct platform_device *pdev) ++{ ++ struct rk2_crypto_dev *rkc = platform_get_drvdata(pdev); ++ struct rk2_crypto_dev *first; ++ ++ spin_lock_bh(&rocklist.lock); ++ list_del(&rkc->list); ++ first = list_first_entry_or_null(&rocklist.dev_list, ++ struct rk2_crypto_dev, list); ++ spin_unlock_bh(&rocklist.lock); ++ ++ if (!first) { ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG ++ debugfs_remove_recursive(rocklist.dbgfs_dir); ++#endif ++ rk2_crypto_unregister(); ++ } ++ rk2_crypto_pm_exit(rkc); ++ crypto_engine_exit(rkc->engine); ++ return 0; ++} ++ ++static struct platform_driver crypto_driver = { ++ .probe = rk2_crypto_probe, ++ .remove = rk2_crypto_remove, ++ .driver = { ++ .name = "rk2-crypto", ++ .pm = &rk2_crypto_pm_ops, ++ .of_match_table = crypto_of_id_table, ++ }, ++}; ++ ++module_platform_driver(crypto_driver); ++ ++MODULE_DESCRIPTION("Rockchip Crypto Engine cryptographic offloader"); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Corentin Labbe "); +diff --git a/drivers/crypto/rockchip/rk2_crypto.h b/drivers/crypto/rockchip/rk2_crypto.h +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/crypto/rockchip/rk2_crypto.h +@@ -0,0 +1,246 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RK2_CRYPTO_CLK_CTL 0x0000 ++#define RK2_CRYPTO_RST_CTL 0x0004 ++ ++#define RK2_CRYPTO_DMA_INT_EN 0x0008 ++/* values for RK2_CRYPTO_DMA_INT_EN */ ++#define RK2_CRYPTO_DMA_INT_LISTDONE BIT(0) ++ ++#define RK2_CRYPTO_DMA_INT_ST 0x000C ++/* values in RK2_CRYPTO_DMA_INT_ST are the same than in RK2_CRYPTO_DMA_INT_EN */ ++ ++#define RK2_CRYPTO_DMA_CTL 0x0010 ++#define RK2_CRYPTO_DMA_CTL_START BIT(0) ++ ++#define RK2_CRYPTO_DMA_LLI_ADDR 0x0014 ++#define RK2_CRYPTO_DMA_ST 0x0018 ++#define RK2_CRYPTO_DMA_STATE 0x001C ++#define RK2_CRYPTO_DMA_LLI_RADDR 0x0020 ++#define RK2_CRYPTO_DMA_SRC_RADDR 0x0024 ++#define RK2_CRYPTO_DMA_DST_WADDR 0x0028 ++#define RK2_CRYPTO_DMA_ITEM_ID 0x002C ++ ++#define RK2_CRYPTO_FIFO_CTL 0x0040 ++ ++#define RK2_CRYPTO_BC_CTL 0x0044 ++#define RK2_CRYPTO_AES (0 << 8) ++#define RK2_CRYPTO_MODE_ECB (0 << 4) ++#define RK2_CRYPTO_MODE_CBC (1 << 4) ++#define RK2_CRYPTO_XTS (6 << 4) ++ ++#define RK2_CRYPTO_HASH_CTL 0x0048 ++#define RK2_CRYPTO_HW_PAD BIT(2) ++#define RK2_CRYPTO_SHA1 (0 << 4) ++#define RK2_CRYPTO_MD5 (1 << 4) ++#define RK2_CRYPTO_SHA224 (3 << 4) ++#define RK2_CRYPTO_SHA256 (2 << 4) ++#define RK2_CRYPTO_SHA384 (9 << 4) ++#define RK2_CRYPTO_SHA512 (8 << 4) ++#define RK2_CRYPTO_SM3 (4 << 4) ++ ++#define RK2_CRYPTO_AES_ECB (RK2_CRYPTO_AES | RK2_CRYPTO_MODE_ECB) ++#define RK2_CRYPTO_AES_CBC (RK2_CRYPTO_AES | RK2_CRYPTO_MODE_CBC) ++#define RK2_CRYPTO_AES_XTS (RK2_CRYPTO_AES | RK2_CRYPTO_XTS) ++#define RK2_CRYPTO_AES_CTR_MODE 3 ++#define RK2_CRYPTO_AES_128BIT_key (0 << 2) ++#define RK2_CRYPTO_AES_192BIT_key (1 << 2) ++#define RK2_CRYPTO_AES_256BIT_key (2 << 2) ++ ++#define RK2_CRYPTO_DEC BIT(1) ++#define RK2_CRYPTO_ENABLE BIT(0) ++ ++#define RK2_CRYPTO_CIPHER_ST 0x004C ++#define RK2_CRYPTO_CIPHER_STATE 0x0050 ++ ++#define RK2_CRYPTO_CH0_IV_0 0x0100 ++ ++#define RK2_CRYPTO_KEY0 0x0180 ++#define RK2_CRYPTO_KEY1 0x0184 ++#define RK2_CRYPTO_KEY2 0x0188 ++#define RK2_CRYPTO_KEY3 0x018C ++#define RK2_CRYPTO_KEY4 0x0190 ++#define RK2_CRYPTO_KEY5 0x0194 ++#define RK2_CRYPTO_KEY6 0x0198 ++#define RK2_CRYPTO_KEY7 0x019C ++#define RK2_CRYPTO_CH4_KEY0 0x01c0 ++ ++#define RK2_CRYPTO_CH0_PC_LEN_0 0x0280 ++ ++#define RK2_CRYPTO_CH0_IV_LEN 0x0300 ++ ++#define RK2_CRYPTO_HASH_DOUT_0 0x03A0 ++#define RK2_CRYPTO_HASH_VALID 0x03E4 ++ ++#define RK2_CRYPTO_TRNG_CTL 0x0400 ++#define RK2_CRYPTO_TRNG_START BIT(0) ++#define RK2_CRYPTO_TRNG_ENABLE BIT(1) ++#define RK2_CRYPTO_TRNG_256 (0x3 << 4) ++#define RK2_CRYPTO_TRNG_SAMPLE_CNT 0x0404 ++#define RK2_CRYPTO_TRNG_DOUT 0x0410 ++ ++#define CRYPTO_AES_VERSION 0x0680 ++#define CRYPTO_DES_VERSION 0x0684 ++#define CRYPTO_SM4_VERSION 0x0688 ++#define CRYPTO_HASH_VERSION 0x068C ++#define CRYPTO_HMAC_VERSION 0x0690 ++#define CRYPTO_RNG_VERSION 0x0694 ++#define CRYPTO_PKA_VERSION 0x0698 ++#define CRYPTO_CRYPTO_VERSION 0x06F0 ++ ++#define RK2_LLI_DMA_CTRL_SRC_INT BIT(10) ++#define RK2_LLI_DMA_CTRL_DST_INT BIT(9) ++#define RK2_LLI_DMA_CTRL_LIST_INT BIT(8) ++#define RK2_LLI_DMA_CTRL_LAST BIT(0) ++ ++#define RK2_LLI_STRING_LAST BIT(2) ++#define RK2_LLI_STRING_FIRST BIT(1) ++#define RK2_LLI_CIPHER_START BIT(0) ++ ++#define RK2_MAX_CLKS 4 ++ ++#define MAX_LLI 20 ++ ++struct rk2_crypto_lli { ++ __le32 src_addr; ++ __le32 src_len; ++ __le32 dst_addr; ++ __le32 dst_len; ++ __le32 user; ++ __le32 iv; ++ __le32 dma_ctrl; ++ __le32 next; ++}; ++ ++/* ++ * struct rockchip_ip - struct for managing a list of RK crypto instance ++ * @dev_list: Used for doing a list of rk2_crypto_dev ++ * @lock: Control access to dev_list ++ * @dbgfs_dir: Debugfs dentry for statistic directory ++ * @dbgfs_stats: Debugfs dentry for statistic counters ++ */ ++struct rockchip_ip { ++ struct list_head dev_list; ++ spinlock_t lock; /* Control access to dev_list */ ++ struct dentry *dbgfs_dir; ++ struct dentry *dbgfs_stats; ++}; ++ ++struct rk2_clks { ++ const char *name; ++ unsigned long max; ++}; ++ ++struct rk2_variant { ++ int num_clks; ++ struct rk2_clks rkclks[RK2_MAX_CLKS]; ++}; ++ ++struct rk2_crypto_dev { ++ struct list_head list; ++ struct device *dev; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ struct reset_control *rst; ++ void __iomem *reg; ++ int irq; ++ const struct rk2_variant *variant; ++ unsigned long nreq; ++ struct crypto_engine *engine; ++ struct completion complete; ++ int status; ++ struct rk2_crypto_lli *tl; ++ dma_addr_t t_phy; ++}; ++ ++/* the private variable of hash */ ++struct rk2_ahash_ctx { ++ /* for fallback */ ++ struct crypto_ahash *fallback_tfm; ++}; ++ ++/* the private variable of hash for fallback */ ++struct rk2_ahash_rctx { ++ struct rk2_crypto_dev *dev; ++ struct ahash_request fallback_req; ++ u32 mode; ++ int nrsgs; ++}; ++ ++/* the private variable of cipher */ ++struct rk2_cipher_ctx { ++ unsigned int keylen; ++ u8 key[AES_MAX_KEY_SIZE * 2]; ++ u8 iv[AES_BLOCK_SIZE]; ++ struct crypto_skcipher *fallback_tfm; ++}; ++ ++struct rk2_cipher_rctx { ++ struct rk2_crypto_dev *dev; ++ u8 backup_iv[AES_BLOCK_SIZE]; ++ u32 mode; ++ struct skcipher_request fallback_req; // keep at the end ++}; ++ ++struct rk2_crypto_template { ++ u32 type; ++ u32 rk2_mode; ++ bool is_xts; ++ struct rk2_crypto_dev *dev; ++ union { ++ struct skcipher_engine_alg skcipher; ++ struct ahash_engine_alg hash; ++ } alg; ++ unsigned long stat_req; ++ unsigned long stat_fb; ++ unsigned long stat_fb_len; ++ unsigned long stat_fb_sglen; ++ unsigned long stat_fb_align; ++ unsigned long stat_fb_sgdiff; ++}; ++ ++struct rk2_crypto_dev *get_rk2_crypto(void); ++int rk2_cipher_run(struct crypto_engine *engine, void *async_req); ++int rk2_hash_run(struct crypto_engine *engine, void *breq); ++ ++int rk2_cipher_tfm_init(struct crypto_skcipher *tfm); ++void rk2_cipher_tfm_exit(struct crypto_skcipher *tfm); ++int rk2_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, ++ unsigned int keylen); ++int rk2_aes_xts_setkey(struct crypto_skcipher *cipher, const u8 *key, ++ unsigned int keylen); ++int rk2_skcipher_encrypt(struct skcipher_request *req); ++int rk2_skcipher_decrypt(struct skcipher_request *req); ++int rk2_aes_ecb_encrypt(struct skcipher_request *req); ++int rk2_aes_ecb_decrypt(struct skcipher_request *req); ++int rk2_aes_cbc_encrypt(struct skcipher_request *req); ++int rk2_aes_cbc_decrypt(struct skcipher_request *req); ++ ++int rk2_ahash_init(struct ahash_request *req); ++int rk2_ahash_update(struct ahash_request *req); ++int rk2_ahash_final(struct ahash_request *req); ++int rk2_ahash_finup(struct ahash_request *req); ++int rk2_ahash_import(struct ahash_request *req, const void *in); ++int rk2_ahash_export(struct ahash_request *req, void *out); ++int rk2_ahash_digest(struct ahash_request *req); ++int rk2_hash_init_tfm(struct crypto_ahash *tfm); ++void rk2_hash_exit_tfm(struct crypto_ahash *tfm); +diff --git a/drivers/crypto/rockchip/rk2_crypto_ahash.c b/drivers/crypto/rockchip/rk2_crypto_ahash.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/crypto/rockchip/rk2_crypto_ahash.c +@@ -0,0 +1,344 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Crypto offloader support for Rockchip RK3568/RK3588 ++ * ++ * Copyright (c) 2022-2023 Corentin Labbe ++ */ ++#include ++#include ++#include "rk2_crypto.h" ++ ++static bool rk2_ahash_need_fallback(struct ahash_request *areq) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct ahash_alg *alg = crypto_ahash_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); ++ struct scatterlist *sg; ++ ++ sg = areq->src; ++ while (sg) { ++ if (!IS_ALIGNED(sg->offset, sizeof(u32))) { ++ algt->stat_fb_align++; ++ return true; ++ } ++ if (sg->length % 4) { ++ algt->stat_fb_sglen++; ++ return true; ++ } ++ sg = sg_next(sg); ++ } ++ return false; ++} ++ ++static int rk2_ahash_digest_fb(struct ahash_request *areq) ++{ ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct rk2_ahash_ctx *tfmctx = crypto_ahash_ctx(tfm); ++ struct ahash_alg *alg = crypto_ahash_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); ++ ++ algt->stat_fb++; ++ ++ ahash_request_set_tfm(&rctx->fallback_req, tfmctx->fallback_tfm); ++ rctx->fallback_req.base.flags = areq->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ rctx->fallback_req.nbytes = areq->nbytes; ++ rctx->fallback_req.src = areq->src; ++ rctx->fallback_req.result = areq->result; ++ ++ return crypto_ahash_digest(&rctx->fallback_req); ++} ++ ++static int zero_message_process(struct ahash_request *req) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct ahash_alg *alg = crypto_ahash_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); ++ int digestsize = crypto_ahash_digestsize(tfm); ++ ++ switch (algt->rk2_mode) { ++ case RK2_CRYPTO_SHA1: ++ memcpy(req->result, sha1_zero_message_hash, digestsize); ++ break; ++ case RK2_CRYPTO_SHA256: ++ memcpy(req->result, sha256_zero_message_hash, digestsize); ++ break; ++ case RK2_CRYPTO_SHA384: ++ memcpy(req->result, sha384_zero_message_hash, digestsize); ++ break; ++ case RK2_CRYPTO_SHA512: ++ memcpy(req->result, sha512_zero_message_hash, digestsize); ++ break; ++ case RK2_CRYPTO_MD5: ++ memcpy(req->result, md5_zero_message_hash, digestsize); ++ break; ++ case RK2_CRYPTO_SM3: ++ memcpy(req->result, sm3_zero_message_hash, digestsize); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int rk2_ahash_init(struct ahash_request *req) ++{ ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ return crypto_ahash_init(&rctx->fallback_req); ++} ++ ++int rk2_ahash_update(struct ahash_request *req) ++{ ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ rctx->fallback_req.nbytes = req->nbytes; ++ rctx->fallback_req.src = req->src; ++ ++ return crypto_ahash_update(&rctx->fallback_req); ++} ++ ++int rk2_ahash_final(struct ahash_request *req) ++{ ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ rctx->fallback_req.result = req->result; ++ ++ return crypto_ahash_final(&rctx->fallback_req); ++} ++ ++int rk2_ahash_finup(struct ahash_request *req) ++{ ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ rctx->fallback_req.nbytes = req->nbytes; ++ rctx->fallback_req.src = req->src; ++ rctx->fallback_req.result = req->result; ++ ++ return crypto_ahash_finup(&rctx->fallback_req); ++} ++ ++int rk2_ahash_import(struct ahash_request *req, const void *in) ++{ ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ return crypto_ahash_import(&rctx->fallback_req, in); ++} ++ ++int rk2_ahash_export(struct ahash_request *req, void *out) ++{ ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk2_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ return crypto_ahash_export(&rctx->fallback_req, out); ++} ++ ++int rk2_ahash_digest(struct ahash_request *req) ++{ ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct rk2_crypto_dev *dev; ++ struct crypto_engine *engine; ++ ++ if (rk2_ahash_need_fallback(req)) ++ return rk2_ahash_digest_fb(req); ++ ++ if (!req->nbytes) ++ return zero_message_process(req); ++ ++ dev = get_rk2_crypto(); ++ ++ rctx->dev = dev; ++ engine = dev->engine; ++ ++ return crypto_transfer_hash_request_to_engine(engine, req); ++} ++ ++static int rk2_hash_prepare(struct crypto_engine *engine, void *breq) ++{ ++ struct ahash_request *areq = container_of(breq, struct ahash_request, base); ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct rk2_crypto_dev *rkc = rctx->dev; ++ int ret; ++ ++ ret = dma_map_sg(rkc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); ++ if (ret <= 0) ++ return -EINVAL; ++ ++ rctx->nrsgs = ret; ++ ++ return 0; ++} ++ ++static void rk2_hash_unprepare(struct crypto_engine *engine, void *breq) ++{ ++ struct ahash_request *areq = container_of(breq, struct ahash_request, base); ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct rk2_crypto_dev *rkc = rctx->dev; ++ ++ dma_unmap_sg(rkc->dev, areq->src, rctx->nrsgs, DMA_TO_DEVICE); ++} ++ ++int rk2_hash_run(struct crypto_engine *engine, void *breq) ++{ ++ struct ahash_request *areq = container_of(breq, struct ahash_request, base); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct rk2_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct ahash_alg *alg = crypto_ahash_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); ++ struct scatterlist *sgs = areq->src; ++ struct rk2_crypto_dev *rkc = rctx->dev; ++ struct rk2_crypto_lli *dd = &rkc->tl[0]; ++ int ddi = 0; ++ int err = 0; ++ unsigned int len = areq->nbytes; ++ unsigned int todo; ++ u32 v; ++ int i; ++ ++ err = rk2_hash_prepare(engine, breq); ++ ++ err = pm_runtime_resume_and_get(rkc->dev); ++ if (err) ++ return err; ++ ++ dev_dbg(rkc->dev, "%s %s len=%d\n", __func__, ++ crypto_tfm_alg_name(areq->base.tfm), areq->nbytes); ++ ++ algt->stat_req++; ++ rkc->nreq++; ++ ++ rctx->mode = algt->rk2_mode; ++ rctx->mode |= 0xffff0000; ++ rctx->mode |= RK2_CRYPTO_ENABLE | RK2_CRYPTO_HW_PAD; ++ writel(rctx->mode, rkc->reg + RK2_CRYPTO_HASH_CTL); ++ ++ while (sgs && len > 0) { ++ dd = &rkc->tl[ddi]; ++ ++ todo = min(sg_dma_len(sgs), len); ++ dd->src_addr = sg_dma_address(sgs); ++ dd->src_len = todo; ++ dd->dst_addr = 0; ++ dd->dst_len = 0; ++ dd->dma_ctrl = ddi << 24; ++ dd->iv = 0; ++ dd->next = rkc->t_phy + sizeof(struct rk2_crypto_lli) * (ddi + 1); ++ ++ if (ddi == 0) ++ dd->user = RK2_LLI_CIPHER_START | RK2_LLI_STRING_FIRST; ++ else ++ dd->user = 0; ++ ++ len -= todo; ++ dd->dma_ctrl |= RK2_LLI_DMA_CTRL_SRC_INT; ++ if (len == 0) { ++ dd->user |= RK2_LLI_STRING_LAST; ++ dd->dma_ctrl |= RK2_LLI_DMA_CTRL_LAST; ++ } ++ dev_dbg(rkc->dev, "HASH SG %d sglen=%d user=%x dma=%x mode=%x len=%d todo=%d phy=%llx\n", ++ ddi, sgs->length, dd->user, dd->dma_ctrl, rctx->mode, len, todo, rkc->t_phy); ++ ++ sgs = sg_next(sgs); ++ ddi++; ++ } ++ dd->next = 1; ++ writel(RK2_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK2_CRYPTO_DMA_INT_EN); ++ ++ writel(rkc->t_phy, rkc->reg + RK2_CRYPTO_DMA_LLI_ADDR); ++ ++ reinit_completion(&rkc->complete); ++ rkc->status = 0; ++ ++ writel(RK2_CRYPTO_DMA_CTL_START | RK2_CRYPTO_DMA_CTL_START << 16, rkc->reg + RK2_CRYPTO_DMA_CTL); ++ ++ wait_for_completion_interruptible_timeout(&rkc->complete, ++ msecs_to_jiffies(2000)); ++ if (!rkc->status) { ++ dev_err(rkc->dev, "DMA timeout\n"); ++ err = -EFAULT; ++ goto theend; ++ } ++ ++ readl_poll_timeout_atomic(rkc->reg + RK2_CRYPTO_HASH_VALID, v, v == 1, ++ 10, 1000); ++ ++ for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) { ++ v = readl(rkc->reg + RK2_CRYPTO_HASH_DOUT_0 + i * 4); ++ put_unaligned_le32(be32_to_cpu(v), areq->result + i * 4); ++ } ++ ++theend: ++ pm_runtime_put_autosuspend(rkc->dev); ++ ++ rk2_hash_unprepare(engine, breq); ++ ++ local_bh_disable(); ++ crypto_finalize_hash_request(engine, breq, err); ++ local_bh_enable(); ++ ++ return 0; ++} ++ ++int rk2_hash_init_tfm(struct crypto_ahash *tfm) ++{ ++ struct rk2_ahash_ctx *tctx = crypto_ahash_ctx(tfm); ++ const char *alg_name = crypto_ahash_alg_name(tfm); ++ struct ahash_alg *alg = crypto_ahash_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.hash.base); ++ ++ /* for fallback */ ++ tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0, ++ CRYPTO_ALG_NEED_FALLBACK); ++ if (IS_ERR(tctx->fallback_tfm)) { ++ dev_err(algt->dev->dev, "Could not load fallback driver.\n"); ++ return PTR_ERR(tctx->fallback_tfm); ++ } ++ ++ crypto_ahash_set_reqsize(tfm, ++ sizeof(struct rk2_ahash_rctx) + ++ crypto_ahash_reqsize(tctx->fallback_tfm)); ++ return 0; ++} ++ ++void rk2_hash_exit_tfm(struct crypto_ahash *tfm) ++{ ++ struct rk2_ahash_ctx *tctx = crypto_ahash_ctx(tfm); ++ ++ crypto_free_ahash(tctx->fallback_tfm); ++} +diff --git a/drivers/crypto/rockchip/rk2_crypto_skcipher.c b/drivers/crypto/rockchip/rk2_crypto_skcipher.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/crypto/rockchip/rk2_crypto_skcipher.c +@@ -0,0 +1,576 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * hardware cryptographic offloader for RK3568/RK3588 SoC ++ * ++ * Copyright (c) 2022-2023 Corentin Labbe ++ */ ++#include ++#include "rk2_crypto.h" ++ ++static void rk2_print(struct rk2_crypto_dev *rkc) ++{ ++ u32 v; ++ ++ v = readl(rkc->reg + RK2_CRYPTO_DMA_ST); ++ dev_info(rkc->dev, "DMA_ST %x\n", v); ++ switch (v) { ++ case 0: ++ dev_info(rkc->dev, "DMA_ST: DMA IDLE\n"); ++ break; ++ case 1: ++ dev_info(rkc->dev, "DMA_ST: DMA BUSY\n"); ++ break; ++ default: ++ dev_err(rkc->dev, "DMA_ST: invalid value\n"); ++ } ++ ++ v = readl(rkc->reg + RK2_CRYPTO_DMA_STATE); ++ dev_info(rkc->dev, "DMA_STATE %x\n", v); ++ ++ switch (v & 0x3) { ++ case 0: ++ dev_info(rkc->dev, "DMA_STATE: DMA DST IDLE\n"); ++ break; ++ case 1: ++ dev_info(rkc->dev, "DMA_STATE: DMA DST LOAD\n"); ++ break; ++ case 2: ++ dev_info(rkc->dev, "DMA_STATE: DMA DST WORK\n"); ++ break; ++ default: ++ dev_err(rkc->dev, "DMA DST invalid\n"); ++ break; ++ } ++ switch (v & 0xC) { ++ case 0: ++ dev_info(rkc->dev, "DMA_STATE: DMA SRC IDLE\n"); ++ break; ++ case 1: ++ dev_info(rkc->dev, "DMA_STATE: DMA SRC LOAD\n"); ++ break; ++ case 2: ++ dev_info(rkc->dev, "DMA_STATE: DMA SRC WORK\n"); ++ break; ++ default: ++ dev_err(rkc->dev, "DMA_STATE: DMA SRC invalid\n"); ++ break; ++ } ++ switch (v & 0x30) { ++ case 0: ++ dev_info(rkc->dev, "DMA_STATE: DMA LLI IDLE\n"); ++ break; ++ case 1: ++ dev_info(rkc->dev, "DMA_STATE: DMA LLI LOAD\n"); ++ break; ++ case 2: ++ dev_info(rkc->dev, "DMA LLI WORK\n"); ++ break; ++ default: ++ dev_err(rkc->dev, "DMA LLI invalid\n"); ++ break; ++ } ++ ++ v = readl(rkc->reg + RK2_CRYPTO_DMA_LLI_RADDR); ++ dev_info(rkc->dev, "DMA_LLI_RADDR %x\n", v); ++ v = readl(rkc->reg + RK2_CRYPTO_DMA_SRC_RADDR); ++ dev_info(rkc->dev, "DMA_SRC_RADDR %x\n", v); ++ v = readl(rkc->reg + RK2_CRYPTO_DMA_DST_WADDR); ++ dev_info(rkc->dev, "DMA_LLI_WADDR %x\n", v); ++ v = readl(rkc->reg + RK2_CRYPTO_DMA_ITEM_ID); ++ dev_info(rkc->dev, "DMA_LLI_ITEMID %x\n", v); ++ ++ v = readl(rkc->reg + RK2_CRYPTO_CIPHER_ST); ++ dev_info(rkc->dev, "CIPHER_ST %x\n", v); ++ if (v & BIT(0)) ++ dev_info(rkc->dev, "CIPHER_ST: BLOCK CIPHER BUSY\n"); ++ else ++ dev_info(rkc->dev, "CIPHER_ST: BLOCK CIPHER IDLE\n"); ++ if (v & BIT(2)) ++ dev_info(rkc->dev, "CIPHER_ST: HASH BUSY\n"); ++ else ++ dev_info(rkc->dev, "CIPHER_ST: HASH IDLE\n"); ++ if (v & BIT(2)) ++ dev_info(rkc->dev, "CIPHER_ST: OTP KEY VALID\n"); ++ else ++ dev_info(rkc->dev, "CIPHER_ST: OTP KEY INVALID\n"); ++ ++ v = readl(rkc->reg + RK2_CRYPTO_CIPHER_STATE); ++ dev_info(rkc->dev, "CIPHER_STATE %x\n", v); ++ switch (v & 0x3) { ++ case 0: ++ dev_info(rkc->dev, "serial: IDLE state\n"); ++ break; ++ case 1: ++ dev_info(rkc->dev, "serial: PRE state\n"); ++ break; ++ case 2: ++ dev_info(rkc->dev, "serial: BULK state\n"); ++ break; ++ default: ++ dev_info(rkc->dev, "serial: reserved state\n"); ++ break; ++ } ++ switch (v & 0xC) { ++ case 0: ++ dev_info(rkc->dev, "mac_state: IDLE state\n"); ++ break; ++ case 1: ++ dev_info(rkc->dev, "mac_state: PRE state\n"); ++ break; ++ case 2: ++ dev_info(rkc->dev, "mac_state: BULK state\n"); ++ break; ++ default: ++ dev_info(rkc->dev, "mac_state: reserved state\n"); ++ break; ++ } ++ switch (v & 0x30) { ++ case 0: ++ dev_info(rkc->dev, "parallel_state: IDLE state\n"); ++ break; ++ case 1: ++ dev_info(rkc->dev, "parallel_state: PRE state\n"); ++ break; ++ case 2: ++ dev_info(rkc->dev, "parallel_state: BULK state\n"); ++ break; ++ default: ++ dev_info(rkc->dev, "parallel_state: reserved state\n"); ++ break; ++ } ++ switch (v & 0xC0) { ++ case 0: ++ dev_info(rkc->dev, "ccm_state: IDLE state\n"); ++ break; ++ case 1: ++ dev_info(rkc->dev, "ccm_state: PRE state\n"); ++ break; ++ case 2: ++ dev_info(rkc->dev, "ccm_state: NA state\n"); ++ break; ++ default: ++ dev_info(rkc->dev, "ccm_state: reserved state\n"); ++ break; ++ } ++ switch (v & 0xF00) { ++ case 0: ++ dev_info(rkc->dev, "gcm_state: IDLE state\n"); ++ break; ++ case 1: ++ dev_info(rkc->dev, "gcm_state: PRE state\n"); ++ break; ++ case 2: ++ dev_info(rkc->dev, "gcm_state: NA state\n"); ++ break; ++ case 3: ++ dev_info(rkc->dev, "gcm_state: PC state\n"); ++ break; ++ } ++ switch (v & 0xC00) { ++ case 0x1: ++ dev_info(rkc->dev, "hash_state: IDLE state\n"); ++ break; ++ case 0x2: ++ dev_info(rkc->dev, "hash_state: IPAD state\n"); ++ break; ++ case 0x4: ++ dev_info(rkc->dev, "hash_state: TEXT state\n"); ++ break; ++ case 0x8: ++ dev_info(rkc->dev, "hash_state: OPAD state\n"); ++ break; ++ case 0x10: ++ dev_info(rkc->dev, "hash_state: OPAD EXT state\n"); ++ break; ++ default: ++ dev_info(rkc->dev, "hash_state: invalid state\n"); ++ break; ++ } ++ ++ v = readl(rkc->reg + RK2_CRYPTO_DMA_INT_ST); ++ dev_info(rkc->dev, "RK2_CRYPTO_DMA_INT_ST %x\n", v); ++} ++ ++static int rk2_cipher_need_fallback(struct skcipher_request *req) ++{ ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); ++ struct scatterlist *sgs, *sgd; ++ unsigned int stodo, dtodo, len; ++ unsigned int bs = crypto_skcipher_blocksize(tfm); ++ ++ if (!req->cryptlen) ++ return true; ++ ++ if (algt->is_xts) { ++ if (sg_nents_for_len(req->src, req->cryptlen) > 1) ++ return true; ++ if (sg_nents_for_len(req->dst, req->cryptlen) > 1) ++ return true; ++ } ++ ++ len = req->cryptlen; ++ sgs = req->src; ++ sgd = req->dst; ++ while (sgs && sgd) { ++ if (!IS_ALIGNED(sgs->offset, sizeof(u32))) { ++ algt->stat_fb_align++; ++ return true; ++ } ++ if (!IS_ALIGNED(sgd->offset, sizeof(u32))) { ++ algt->stat_fb_align++; ++ return true; ++ } ++ stodo = min(len, sgs->length); ++ if (stodo % bs) { ++ algt->stat_fb_len++; ++ return true; ++ } ++ dtodo = min(len, sgd->length); ++ if (dtodo % bs) { ++ algt->stat_fb_len++; ++ return true; ++ } ++ if (stodo != dtodo) { ++ algt->stat_fb_sgdiff++; ++ return true; ++ } ++ len -= stodo; ++ sgs = sg_next(sgs); ++ sgd = sg_next(sgd); ++ } ++ return false; ++} ++ ++static int rk2_cipher_fallback(struct skcipher_request *areq) ++{ ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); ++ struct rk2_cipher_ctx *op = crypto_skcipher_ctx(tfm); ++ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(areq); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); ++ int err; ++ ++ algt->stat_fb++; ++ ++ skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm); ++ skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags, ++ areq->base.complete, areq->base.data); ++ skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst, ++ areq->cryptlen, areq->iv); ++ if (rctx->mode & RK2_CRYPTO_DEC) ++ err = crypto_skcipher_decrypt(&rctx->fallback_req); ++ else ++ err = crypto_skcipher_encrypt(&rctx->fallback_req); ++ return err; ++} ++ ++static int rk2_cipher_handle_req(struct skcipher_request *req) ++{ ++ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req); ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk2_crypto_dev *rkc; ++ struct crypto_engine *engine; ++ ++ if (ctx->keylen == AES_KEYSIZE_192 * 2) ++ return rk2_cipher_fallback(req); ++ ++ if (rk2_cipher_need_fallback(req)) ++ return rk2_cipher_fallback(req); ++ ++ rkc = get_rk2_crypto(); ++ ++ engine = rkc->engine; ++ rctx->dev = rkc; ++ ++ return crypto_transfer_skcipher_request_to_engine(engine, req); ++} ++ ++int rk2_aes_xts_setkey(struct crypto_skcipher *cipher, const u8 *key, ++ unsigned int keylen) ++{ ++ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); ++ struct rk2_cipher_ctx *ctx = crypto_tfm_ctx(tfm); ++ int err; ++ ++ err = xts_verify_key(cipher, key, keylen); ++ if (err) ++ return err; ++ ++ ctx->keylen = keylen; ++ memcpy(ctx->key, key, keylen); ++ ++ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); ++} ++ ++int rk2_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, ++ unsigned int keylen) ++{ ++ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); ++ struct rk2_cipher_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && ++ keylen != AES_KEYSIZE_256) ++ return -EINVAL; ++ ctx->keylen = keylen; ++ memcpy(ctx->key, key, keylen); ++ ++ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); ++} ++ ++int rk2_skcipher_encrypt(struct skcipher_request *req) ++{ ++ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req); ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); ++ ++ rctx->mode = algt->rk2_mode; ++ return rk2_cipher_handle_req(req); ++} ++ ++int rk2_skcipher_decrypt(struct skcipher_request *req) ++{ ++ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(req); ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); ++ ++ rctx->mode = algt->rk2_mode | RK2_CRYPTO_DEC; ++ return rk2_cipher_handle_req(req); ++} ++ ++int rk2_cipher_run(struct crypto_engine *engine, void *async_req) ++{ ++ struct skcipher_request *areq = container_of(async_req, struct skcipher_request, base); ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); ++ struct rk2_cipher_rctx *rctx = skcipher_request_ctx(areq); ++ struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct scatterlist *sgs, *sgd; ++ int err = 0; ++ int ivsize = crypto_skcipher_ivsize(tfm); ++ unsigned int len = areq->cryptlen; ++ unsigned int todo; ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); ++ struct rk2_crypto_dev *rkc = rctx->dev; ++ struct rk2_crypto_lli *dd = &rkc->tl[0]; ++ u32 m, v; ++ u32 *rkey = (u32 *)ctx->key; ++ u32 *riv = (u32 *)areq->iv; ++ int i; ++ unsigned int offset; ++ ++ algt->stat_req++; ++ rkc->nreq++; ++ ++ m = rctx->mode | RK2_CRYPTO_ENABLE; ++ if (algt->is_xts) { ++ switch (ctx->keylen) { ++ case AES_KEYSIZE_128 * 2: ++ m |= RK2_CRYPTO_AES_128BIT_key; ++ break; ++ case AES_KEYSIZE_256 * 2: ++ m |= RK2_CRYPTO_AES_256BIT_key; ++ break; ++ default: ++ dev_err(rkc->dev, "Invalid key length %u\n", ctx->keylen); ++ return -EINVAL; ++ } ++ } else { ++ switch (ctx->keylen) { ++ case AES_KEYSIZE_128: ++ m |= RK2_CRYPTO_AES_128BIT_key; ++ break; ++ case AES_KEYSIZE_192: ++ m |= RK2_CRYPTO_AES_192BIT_key; ++ break; ++ case AES_KEYSIZE_256: ++ m |= RK2_CRYPTO_AES_256BIT_key; ++ break; ++ default: ++ dev_err(rkc->dev, "Invalid key length %u\n", ctx->keylen); ++ return -EINVAL; ++ } ++ } ++ ++ err = pm_runtime_resume_and_get(rkc->dev); ++ if (err) ++ return err; ++ ++ /* the upper bits are a write enable mask, so we need to write 1 to all ++ * upper 16 bits to allow write to the 16 lower bits ++ */ ++ m |= 0xffff0000; ++ ++ dev_dbg(rkc->dev, "%s %s len=%u keylen=%u mode=%x\n", __func__, ++ crypto_tfm_alg_name(areq->base.tfm), ++ areq->cryptlen, ctx->keylen, m); ++ sgs = areq->src; ++ sgd = areq->dst; ++ ++ while (sgs && sgd && len) { ++ ivsize = crypto_skcipher_ivsize(tfm); ++ if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) { ++ if (rctx->mode & RK2_CRYPTO_DEC) { ++ offset = sgs->length - ivsize; ++ scatterwalk_map_and_copy(rctx->backup_iv, sgs, ++ offset, ivsize, 0); ++ } ++ } ++ ++ dev_dbg(rkc->dev, "SG len=%u mode=%x ivsize=%u\n", sgs->length, m, ivsize); ++ ++ if (sgs == sgd) { ++ err = dma_map_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL); ++ if (err != 1) { ++ dev_err(rkc->dev, "Invalid sg number %d\n", err); ++ err = -EINVAL; ++ goto theend; ++ } ++ } else { ++ err = dma_map_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); ++ if (err != 1) { ++ dev_err(rkc->dev, "Invalid sg number %d\n", err); ++ err = -EINVAL; ++ goto theend; ++ } ++ err = dma_map_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE); ++ if (err != 1) { ++ dev_err(rkc->dev, "Invalid sg number %d\n", err); ++ err = -EINVAL; ++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); ++ goto theend; ++ } ++ } ++ err = 0; ++ writel(m, rkc->reg + RK2_CRYPTO_BC_CTL); ++ ++ if (algt->is_xts) { ++ for (i = 0; i < ctx->keylen / 8; i++) { ++ v = cpu_to_be32(rkey[i]); ++ writel(v, rkc->reg + RK2_CRYPTO_KEY0 + i * 4); ++ } ++ for (i = 0; i < (ctx->keylen / 8); i++) { ++ v = cpu_to_be32(rkey[i + ctx->keylen / 8]); ++ writel(v, rkc->reg + RK2_CRYPTO_CH4_KEY0 + i * 4); ++ } ++ } else { ++ for (i = 0; i < ctx->keylen / 4; i++) { ++ v = cpu_to_be32(rkey[i]); ++ writel(v, rkc->reg + RK2_CRYPTO_KEY0 + i * 4); ++ } ++ } ++ ++ if (ivsize) { ++ for (i = 0; i < ivsize / 4; i++) ++ writel(cpu_to_be32(riv[i]), ++ rkc->reg + RK2_CRYPTO_CH0_IV_0 + i * 4); ++ writel(ivsize, rkc->reg + RK2_CRYPTO_CH0_IV_LEN); ++ } ++ if (!sgs->length) { ++ sgs = sg_next(sgs); ++ sgd = sg_next(sgd); ++ continue; ++ } ++ ++ /* The hw support multiple descriptor, so why this driver use ++ * only one descriptor ? ++ * Using one descriptor per SG seems the way to do and it works ++ * but only when doing encryption. ++ * With decryption it always fail on second descriptor. ++ * Probably the HW dont know how to use IV. ++ */ ++ todo = min(sg_dma_len(sgs), len); ++ len -= todo; ++ dd->src_addr = sg_dma_address(sgs); ++ dd->src_len = todo; ++ dd->dst_addr = sg_dma_address(sgd); ++ dd->dst_len = todo; ++ dd->iv = 0; ++ dd->next = 1; ++ ++ dd->user = RK2_LLI_CIPHER_START | RK2_LLI_STRING_FIRST | RK2_LLI_STRING_LAST; ++ dd->dma_ctrl |= RK2_LLI_DMA_CTRL_DST_INT | RK2_LLI_DMA_CTRL_LAST; ++ ++ writel(RK2_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK2_CRYPTO_DMA_INT_EN); ++ ++ /*writel(0x00030000, rkc->reg + RK2_CRYPTO_FIFO_CTL);*/ ++ writel(rkc->t_phy, rkc->reg + RK2_CRYPTO_DMA_LLI_ADDR); ++ ++ reinit_completion(&rkc->complete); ++ rkc->status = 0; ++ ++ writel(RK2_CRYPTO_DMA_CTL_START | 1 << 16, rkc->reg + RK2_CRYPTO_DMA_CTL); ++ ++ wait_for_completion_interruptible_timeout(&rkc->complete, ++ msecs_to_jiffies(10000)); ++ if (sgs == sgd) { ++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL); ++ } else { ++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); ++ dma_unmap_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE); ++ } ++ ++ if (!rkc->status) { ++ dev_err(rkc->dev, "DMA timeout\n"); ++ rk2_print(rkc); ++ err = -EFAULT; ++ goto theend; ++ } ++ if (areq->iv && ivsize > 0) { ++ offset = sgd->length - ivsize; ++ if (rctx->mode & RK2_CRYPTO_DEC) { ++ memcpy(areq->iv, rctx->backup_iv, ivsize); ++ memzero_explicit(rctx->backup_iv, ivsize); ++ } else { ++ scatterwalk_map_and_copy(areq->iv, sgd, offset, ++ ivsize, 0); ++ } ++ } ++ sgs = sg_next(sgs); ++ sgd = sg_next(sgd); ++ } ++theend: ++ writel(0xffff0000, rkc->reg + RK2_CRYPTO_BC_CTL); ++ pm_runtime_put_autosuspend(rkc->dev); ++ ++ local_bh_disable(); ++ crypto_finalize_skcipher_request(engine, areq, err); ++ local_bh_enable(); ++ return 0; ++} ++ ++int rk2_cipher_tfm_init(struct crypto_skcipher *tfm) ++{ ++ struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ const char *name = crypto_tfm_alg_name(&tfm->base); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk2_crypto_template *algt = container_of(alg, struct rk2_crypto_template, alg.skcipher.base); ++ ++ ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); ++ if (IS_ERR(ctx->fallback_tfm)) { ++ dev_err(algt->dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n", ++ name, PTR_ERR(ctx->fallback_tfm)); ++ return PTR_ERR(ctx->fallback_tfm); ++ } ++ ++ dev_info(algt->dev->dev, "Fallback for %s is %s\n", ++ crypto_tfm_alg_driver_name(&tfm->base), ++ crypto_tfm_alg_driver_name(crypto_skcipher_tfm(ctx->fallback_tfm))); ++ ++ tfm->reqsize = sizeof(struct rk2_cipher_rctx) + ++ crypto_skcipher_reqsize(ctx->fallback_tfm); ++ ++ return 0; ++} ++ ++void rk2_cipher_tfm_exit(struct crypto_skcipher *tfm) ++{ ++ struct rk2_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ ++ memzero_explicit(ctx->key, ctx->keylen); ++ crypto_free_skcipher(ctx->fallback_tfm); ++} +-- +Armbian + diff --git a/kernel.patches/0025-RK3588-Add-HW-RNG-Support.patch b/kernel.patches/0025-RK3588-Add-HW-RNG-Support.patch new file mode 100644 index 0000000..92a0d75 --- /dev/null +++ b/kernel.patches/0025-RK3588-Add-HW-RNG-Support.patch @@ -0,0 +1,663 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Thu, 16 Nov 2023 17:49:42 +0300 +Subject: hwrng: rockchip: Add support for Rockchip HW RNG + +--- + drivers/char/hw_random/Kconfig | 13 + + drivers/char/hw_random/Makefile | 1 + + drivers/char/hw_random/rockchip-rng.c | 574 ++++++++++ + 3 files changed, 588 insertions(+) + +diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig +index 111111111111..222222222222 100644 +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -538,6 +538,19 @@ config HW_RANDOM_XIPHERA + To compile this driver as a module, choose M here: the + module will be called xiphera-trng. + ++config HW_RANDOM_ROCKCHIP ++ tristate "Rockchip Random Number Generator support" ++ depends on ARCH_ROCKCHIP ++ default HW_RANDOM ++ help ++ This driver provides kernel-side support for the Random Number ++ Generator hardware found on Rockchip cpus. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called rockchip-rng. ++ ++ If unsure, say Y. ++ + config HW_RANDOM_ARM_SMCCC_TRNG + tristate "Arm SMCCC TRNG firmware interface support" + depends on HAVE_ARM_SMCCC_DISCOVERY +diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/char/hw_random/Makefile ++++ b/drivers/char/hw_random/Makefile +@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o + obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o + obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o + obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o ++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o + obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o + obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o + obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o +diff --git a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/char/hw_random/rockchip-rng.c +@@ -0,0 +1,574 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * rockchip-rng.c Random Number Generator driver for the Rockchip ++ * ++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. ++ * Author: Lin Jinhan ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define _SBF(s, v) ((v) << (s)) ++#define HIWORD_UPDATE(val, mask, shift) \ ++ ((val) << (shift) | (mask) << ((shift) + 16)) ++ ++#define ROCKCHIP_AUTOSUSPEND_DELAY 100 ++#define ROCKCHIP_POLL_PERIOD_US 100 ++#define ROCKCHIP_POLL_TIMEOUT_US 50000 ++#define RK_MAX_RNG_BYTE (32) ++ ++/* start of CRYPTO V1 register define */ ++#define CRYPTO_V1_CTRL 0x0008 ++#define CRYPTO_V1_RNG_START BIT(8) ++#define CRYPTO_V1_RNG_FLUSH BIT(9) ++ ++#define CRYPTO_V1_TRNG_CTRL 0x0200 ++#define CRYPTO_V1_OSC_ENABLE BIT(16) ++#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) ++ ++#define CRYPTO_V1_TRNG_DOUT_0 0x0204 ++/* end of CRYPTO V1 register define */ ++ ++/* start of CRYPTO V2 register define */ ++#define CRYPTO_V2_RNG_DEFAULT_OFFSET 0x0400 ++#define CRYPTO_V2_RNG_CTL 0x0 ++#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) ++#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) ++#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) ++#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) ++#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) ++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) ++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) ++#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) ++#define CRYPTO_V2_RNG_ENABLE BIT(1) ++#define CRYPTO_V2_RNG_START BIT(0) ++#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0004 ++#define CRYPTO_V2_RNG_DOUT_0 0x0010 ++/* end of CRYPTO V2 register define */ ++ ++/* start of TRNG_V1 register define */ ++/* TRNG is no longer subordinate to the Crypto module */ ++#define TRNG_V1_CTRL 0x0000 ++#define TRNG_V1_CTRL_NOP _SBF(0, 0x00) ++#define TRNG_V1_CTRL_RAND _SBF(0, 0x01) ++#define TRNG_V1_CTRL_SEED _SBF(0, 0x02) ++ ++#define TRNG_V1_STAT 0x0004 ++#define TRNG_V1_STAT_SEEDED BIT(9) ++#define TRNG_V1_STAT_GENERATING BIT(30) ++#define TRNG_V1_STAT_RESEEDING BIT(31) ++ ++#define TRNG_V1_MODE 0x0008 ++#define TRNG_V1_MODE_128_BIT _SBF(3, 0x00) ++#define TRNG_V1_MODE_256_BIT _SBF(3, 0x01) ++ ++#define TRNG_V1_IE 0x0010 ++#define TRNG_V1_IE_GLBL_EN BIT(31) ++#define TRNG_V1_IE_SEED_DONE_EN BIT(1) ++#define TRNG_V1_IE_RAND_RDY_EN BIT(0) ++ ++#define TRNG_V1_ISTAT 0x0014 ++#define TRNG_V1_ISTAT_RAND_RDY BIT(0) ++ ++/* RAND0 ~ RAND7 */ ++#define TRNG_V1_RAND0 0x0020 ++#define TRNG_V1_RAND7 0x003C ++ ++#define TRNG_V1_AUTO_RQSTS 0x0060 ++ ++#define TRNG_V1_VERSION 0x00F0 ++#define TRNG_v1_VERSION_CODE 0x46bc ++/* end of TRNG_V1 register define */ ++ ++/* start of RKRNG register define */ ++#define RKRNG_CTRL 0x0010 ++#define RKRNG_CTRL_INST_REQ BIT(0) ++#define RKRNG_CTRL_RESEED_REQ BIT(1) ++#define RKRNG_CTRL_TEST_REQ BIT(2) ++#define RKRNG_CTRL_SW_DRNG_REQ BIT(3) ++#define RKRNG_CTRL_SW_TRNG_REQ BIT(4) ++ ++#define RKRNG_STATE 0x0014 ++#define RKRNG_STATE_INST_ACK BIT(0) ++#define RKRNG_STATE_RESEED_ACK BIT(1) ++#define RKRNG_STATE_TEST_ACK BIT(2) ++#define RKRNG_STATE_SW_DRNG_ACK BIT(3) ++#define RKRNG_STATE_SW_TRNG_ACK BIT(4) ++ ++/* DRNG_DATA_0 ~ DNG_DATA_7 */ ++#define RKRNG_DRNG_DATA_0 0x0070 ++#define RKRNG_DRNG_DATA_7 0x008C ++ ++/* end of RKRNG register define */ ++ ++struct rk_rng_soc_data { ++ u32 default_offset; ++ ++ int (*rk_rng_init)(struct hwrng *rng); ++ int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait); ++}; ++ ++struct rk_rng { ++ struct device *dev; ++ struct hwrng rng; ++ void __iomem *mem; ++ struct rk_rng_soc_data *soc_data; ++ int clk_num; ++ struct clk_bulk_data *clk_bulks; ++}; ++ ++static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset) ++{ ++ __raw_writel(val, rng->mem + offset); ++} ++ ++static u32 rk_rng_readl(struct rk_rng *rng, u32 offset) ++{ ++ return __raw_readl(rng->mem + offset); ++} ++ ++static int rk_rng_init(struct hwrng *rng) ++{ ++ int ret; ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n"); ++ ++ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); ++ if (ret < 0) { ++ dev_err(rk_rng->dev, "failed to enable clks %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void rk_rng_cleanup(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n"); ++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); ++} ++ ++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ int ret; ++ int read_len = 0; ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ if (!rk_rng->soc_data->rk_rng_read) ++ return -EFAULT; ++ ++ ret = pm_runtime_get_sync(rk_rng->dev); ++ if (ret < 0) { ++ pm_runtime_put_noidle(rk_rng->dev); ++ return ret; ++ } ++ ++ ret = 0; ++ while (max > ret) { ++ read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret, ++ max - ret, wait); ++ if (read_len < 0) { ++ ret = read_len; ++ break; ++ } ++ ret += read_len; ++ } ++ ++ pm_runtime_mark_last_busy(rk_rng->dev); ++ pm_runtime_put_sync_autosuspend(rk_rng->dev); ++ ++ return ret; ++} ++ ++static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf, ++ size_t size) ++{ ++ u32 i; ++ ++ for (i = 0; i < size; i += 4) ++ *(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i)); ++} ++ ++static int crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ int ret = 0; ++ u32 reg_ctrl = 0; ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ /* enable osc_ring to get entropy, sample period is set as 100 */ ++ reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100); ++ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL); ++ ++ reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0); ++ ++ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL); ++ ++ ret = read_poll_timeout(rk_rng_readl, reg_ctrl, ++ !(reg_ctrl & CRYPTO_V1_RNG_START), ++ ROCKCHIP_POLL_PERIOD_US, ++ ROCKCHIP_POLL_TIMEOUT_US, false, ++ rk_rng, CRYPTO_V1_CTRL); ++ ++ if (ret < 0) ++ goto out; ++ ++ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); ++ ++ rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret); ++ ++out: ++ /* close TRNG */ ++ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0), ++ CRYPTO_V1_CTRL); ++ ++ return ret; ++} ++ ++static int crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ int ret = 0; ++ u32 reg_ctrl = 0; ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ /* enable osc_ring to get entropy, sample period is set as 100 */ ++ rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT); ++ ++ reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN; ++ reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; ++ reg_ctrl |= CRYPTO_V2_RNG_ENABLE; ++ reg_ctrl |= CRYPTO_V2_RNG_START; ++ ++ rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), ++ CRYPTO_V2_RNG_CTL); ++ ++ ret = read_poll_timeout(rk_rng_readl, reg_ctrl, ++ !(reg_ctrl & CRYPTO_V2_RNG_START), ++ ROCKCHIP_POLL_PERIOD_US, ++ ROCKCHIP_POLL_TIMEOUT_US, false, ++ rk_rng, CRYPTO_V2_RNG_CTL); ++ if (ret < 0) ++ goto out; ++ ++ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); ++ ++ rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret); ++ ++out: ++ /* close TRNG */ ++ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL); ++ ++ return ret; ++} ++ ++static int trng_v1_init(struct hwrng *rng) ++{ ++ int ret; ++ uint32_t auto_reseed_cnt = 1000; ++ uint32_t reg_ctrl, status, version; ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ version = rk_rng_readl(rk_rng, TRNG_V1_VERSION); ++ if (version != TRNG_v1_VERSION_CODE) { ++ dev_err(rk_rng->dev, ++ "wrong trng version, expected = %08x, actual = %08x\n", ++ TRNG_V1_VERSION, version); ++ ret = -EFAULT; ++ goto exit; ++ } ++ ++ status = rk_rng_readl(rk_rng, TRNG_V1_STAT); ++ ++ /* TRNG should wait RAND_RDY triggered if it is busy or not seeded */ ++ if (!(status & TRNG_V1_STAT_SEEDED) || ++ (status & TRNG_V1_STAT_GENERATING) || ++ (status & TRNG_V1_STAT_RESEEDING)) { ++ uint32_t mask = TRNG_V1_STAT_SEEDED | ++ TRNG_V1_STAT_GENERATING | ++ TRNG_V1_STAT_RESEEDING; ++ ++ udelay(10); ++ ++ /* wait for GENERATING and RESEEDING flag to clear */ ++ read_poll_timeout(rk_rng_readl, reg_ctrl, ++ (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED, ++ ROCKCHIP_POLL_PERIOD_US, ++ ROCKCHIP_POLL_TIMEOUT_US, false, ++ rk_rng, TRNG_V1_STAT); ++ } ++ ++ /* clear ISTAT flag because trng may auto reseeding when power on */ ++ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); ++ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); ++ ++ /* auto reseed after (auto_reseed_cnt * 16) byte rand generate */ ++ rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS); ++ ++ ret = 0; ++exit: ++ ++ return ret; ++} ++ ++static int trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ int ret = 0; ++ u32 reg_ctrl = 0; ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ /* clear ISTAT anyway */ ++ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); ++ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); ++ ++ /* generate 256bit random */ ++ rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE); ++ rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL); ++ ++ /* ++ * Generate2 56 bit random data will cost 1024 clock cycles. ++ * Estimated at 150M RNG module frequency, it takes 6.7 microseconds. ++ */ ++ udelay(10); ++ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); ++ if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) { ++ /* wait RAND_RDY triggered */ ++ ret = read_poll_timeout(rk_rng_readl, reg_ctrl, ++ (reg_ctrl & TRNG_V1_ISTAT_RAND_RDY), ++ ROCKCHIP_POLL_PERIOD_US, ++ ROCKCHIP_POLL_TIMEOUT_US, false, ++ rk_rng, TRNG_V1_ISTAT); ++ if (ret < 0) ++ goto out; ++ } ++ ++ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); ++ ++ rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret); ++ ++ /* clear all status flag */ ++ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); ++out: ++ /* close TRNG */ ++ rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL); ++ ++ return ret; ++} ++ ++static int rkrng_init(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg = 0; ++ ++ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL); ++ ++ reg = rk_rng_readl(rk_rng, RKRNG_STATE); ++ rk_rng_writel(rk_rng, reg, RKRNG_STATE); ++ ++ return 0; ++} ++ ++static int rkrng_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg_ctrl = 0; ++ int ret; ++ ++ reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ; ++ ++ rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL); ++ ++ ret = readl_poll_timeout(rk_rng->mem + RKRNG_STATE, reg_ctrl, ++ (reg_ctrl & RKRNG_STATE_SW_DRNG_ACK), ++ ROCKCHIP_POLL_PERIOD_US, ++ ROCKCHIP_POLL_TIMEOUT_US); ++ ++ if (ret) ++ goto exit; ++ ++ rk_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE); ++ ++ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); ++ ++ rk_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, ret); ++ ++exit: ++ /* close TRNG */ ++ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL); ++ ++ return ret; ++} ++ ++static const struct rk_rng_soc_data crypto_v1_soc_data = { ++ .default_offset = 0, ++ ++ .rk_rng_read = crypto_v1_read, ++}; ++ ++static const struct rk_rng_soc_data crypto_v2_soc_data = { ++ .default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET, ++ ++ .rk_rng_read = crypto_v2_read, ++}; ++ ++static const struct rk_rng_soc_data trng_v1_soc_data = { ++ .default_offset = 0, ++ ++ .rk_rng_init = trng_v1_init, ++ .rk_rng_read = trng_v1_read, ++}; ++ ++static const struct rk_rng_soc_data rkrng_soc_data = { ++ .default_offset = 0, ++ ++ .rk_rng_init = rkrng_init, ++ .rk_rng_read = rkrng_read, ++}; ++ ++static const struct of_device_id rk_rng_dt_match[] = { ++ { ++ .compatible = "rockchip,cryptov1-rng", ++ .data = (void *)&crypto_v1_soc_data, ++ }, ++ { ++ .compatible = "rockchip,cryptov2-rng", ++ .data = (void *)&crypto_v2_soc_data, ++ }, ++ { ++ .compatible = "rockchip,trngv1", ++ .data = (void *)&trng_v1_soc_data, ++ }, ++ { ++ .compatible = "rockchip,rkrng", ++ .data = (void *)&rkrng_soc_data, ++ }, ++ { }, ++}; ++ ++MODULE_DEVICE_TABLE(of, rk_rng_dt_match); ++ ++static int rk_rng_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct rk_rng *rk_rng; ++ struct device_node *np = pdev->dev.of_node; ++ const struct of_device_id *match; ++ resource_size_t map_size; ++ ++ dev_dbg(&pdev->dev, "probing...\n"); ++ rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL); ++ if (!rk_rng) ++ return -ENOMEM; ++ ++ match = of_match_node(rk_rng_dt_match, np); ++ rk_rng->soc_data = (struct rk_rng_soc_data *)match->data; ++ ++ rk_rng->dev = &pdev->dev; ++ rk_rng->rng.name = "rockchip"; ++#ifndef CONFIG_PM ++ rk_rng->rng.init = rk_rng_init; ++ rk_rng->rng.cleanup = rk_rng_cleanup, ++#endif ++ rk_rng->rng.read = rk_rng_read; ++ rk_rng->rng.quality = 999; ++ ++ rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size); ++ if (IS_ERR(rk_rng->mem)) ++ return PTR_ERR(rk_rng->mem); ++ ++ /* compatible with crypto v2 module */ ++ /* ++ * With old dtsi configurations, the RNG base was equal to the crypto ++ * base, so both drivers could not be enabled at the same time. ++ * RNG base = CRYPTO base + RNG offset ++ * (Since RK356X, RNG module is no longer belongs to CRYPTO module) ++ * ++ * With new dtsi configurations, CRYPTO regs is divided into two parts ++ * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base. ++ * RNG driver and CRYPTO driver could be enabled at the same time. ++ */ ++ if (map_size > rk_rng->soc_data->default_offset) ++ rk_rng->mem += rk_rng->soc_data->default_offset; ++ ++ rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks); ++ if (rk_rng->clk_num < 0) { ++ dev_err(&pdev->dev, "failed to get clks property\n"); ++ return -ENODEV; ++ } ++ ++ platform_set_drvdata(pdev, rk_rng); ++ ++ pm_runtime_set_autosuspend_delay(&pdev->dev, ++ ROCKCHIP_AUTOSUSPEND_DELAY); ++ pm_runtime_use_autosuspend(&pdev->dev); ++ pm_runtime_enable(&pdev->dev); ++ ++ ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng); ++ if (ret) { ++ pm_runtime_dont_use_autosuspend(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ } ++ ++ /* for some platform need hardware operation when probe */ ++ if (rk_rng->soc_data->rk_rng_init) { ++ pm_runtime_get_sync(rk_rng->dev); ++ ++ ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng); ++ ++ pm_runtime_mark_last_busy(rk_rng->dev); ++ pm_runtime_put_sync_autosuspend(rk_rng->dev); ++ } ++ ++ return ret; ++} ++ ++#ifdef CONFIG_PM ++static int rk_rng_runtime_suspend(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ rk_rng_cleanup(&rk_rng->rng); ++ ++ return 0; ++} ++ ++static int rk_rng_runtime_resume(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ return rk_rng_init(&rk_rng->rng); ++} ++ ++static const struct dev_pm_ops rk_rng_pm_ops = { ++ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, ++ rk_rng_runtime_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++}; ++ ++#endif ++ ++static struct platform_driver rk_rng_driver = { ++ .driver = { ++ .name = "rockchip-rng", ++#ifdef CONFIG_PM ++ .pm = &rk_rng_pm_ops, ++#endif ++ .of_match_table = rk_rng_dt_match, ++ }, ++ .probe = rk_rng_probe, ++}; ++ ++module_platform_driver(rk_rng_driver); ++ ++MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver"); ++MODULE_AUTHOR("Lin Jinhan "); ++MODULE_LICENSE("GPL v2"); +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Thu, 16 Nov 2023 17:52:35 +0300 +Subject: arm64: dts: Add HW RNG support to RK3588S + +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1935,6 +1935,16 @@ crypto: crypto@fe370000 { + status = "okay"; + }; + ++ rng: rng@fe378000 { ++ compatible = "rockchip,trngv1"; ++ reg = <0x0 0xfe378000 0x0 0x200>; ++ interrupts = ; ++ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; ++ clock-names = "hclk_trng"; ++ resets = <&scmi_reset SRST_H_TRNG_NS>; ++ reset-names = "reset"; ++ }; ++ + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; +-- +Armbian + diff --git a/kernel.patches/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch b/kernel.patches/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch new file mode 100644 index 0000000..78b7d8b --- /dev/null +++ b/kernel.patches/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch @@ -0,0 +1,311 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 13 Jun 2024 15:48:42 +0200 +Subject: media: dt-bindings: rk3568-vepu: Add RK3588 VEPU121 + +From: Emmanuel Gil Peyrot + +This encoder-only device is present four times on this SoC, and should +support everything the rk3568 vepu supports (so JPEG, H.264 and VP8 +encoding). No fallback compatible has been added, since the operating +systems might already support RK3568 VEPU and want to avoid registering +four of them separately considering they can be used as a cluster. + +Signed-off-by: Emmanuel Gil Peyrot +Signed-off-by: Sebastian Reichel +--- + Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml +index 111111111111..222222222222 100644 +--- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml ++++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml +@@ -17,6 +17,7 @@ properties: + compatible: + enum: + - rockchip,rk3568-vepu ++ - rockchip,rk3588-vepu121 + + reg: + maxItems: 1 +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 13 Jun 2024 15:48:44 +0200 +Subject: media: hantro: Disable multicore support + +Avoid exposing equal Hantro video codecs to userspace. Equal video +codecs allow scheduling work between the cores. For that kernel support +is required, which does not yet exist. Until that is implemented avoid +exposing each core separately to userspace so that multicore can be +added in the future without breaking userspace ABI. + +This was written with Rockchip RK3588 in mind (which has 4 Hantro H1 +cores), but applies to all SoCs. + +Signed-off-by: Sebastian Reichel +--- + drivers/media/platform/verisilicon/hantro_drv.c | 37 ++++++++++ + 1 file changed, 37 insertions(+) + +diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/verisilicon/hantro_drv.c ++++ b/drivers/media/platform/verisilicon/hantro_drv.c +@@ -992,6 +992,39 @@ static const struct media_device_ops hantro_m2m_media_ops = { + .req_queue = v4l2_m2m_request_queue, + }; + ++/* ++ * Some SoCs, like RK3588 have multiple identical Hantro cores, but the ++ * kernel is currently missing support for multi-core handling. Exposing ++ * separate devices for each core to userspace is bad, since that does ++ * not allow scheduling tasks properly (and creates ABI). With this workaround ++ * the driver will only probe for the first core and early exit for the other ++ * cores. Once the driver gains multi-core support, the same technique ++ * for detecting the main core can be used to cluster all cores together. ++ */ ++static int hantro_disable_multicore(struct hantro_dev *vpu) ++{ ++ const char *compatible; ++ struct device_node *node; ++ int ret; ++ ++ /* Intentionally ignores the fallback strings */ ++ ret = of_property_read_string(vpu->dev->of_node, "compatible", &compatible); ++ if (ret) ++ return ret; ++ ++ /* first compatible node found from the root node is considered the main core */ ++ node = of_find_compatible_node(NULL, NULL, compatible); ++ if (!node) ++ return -EINVAL; /* broken DT? */ ++ ++ if (vpu->dev->of_node != node) { ++ dev_info(vpu->dev, "missing multi-core support, ignoring this instance\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ + static int hantro_probe(struct platform_device *pdev) + { + const struct of_device_id *match; +@@ -1011,6 +1044,10 @@ static int hantro_probe(struct platform_device *pdev) + match = of_match_node(of_hantro_match, pdev->dev.of_node); + vpu->variant = match->data; + ++ ret = hantro_disable_multicore(vpu); ++ if (ret) ++ return ret; ++ + /* + * Support for nxp,imx8mq-vpu is kept for backwards compatibility + * but it's deprecated. Please update your DTS file to use +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 13 Jun 2024 15:48:45 +0200 +Subject: media: hantro: Add RK3588 VEPU121 + +RK3588 handling is exactly the same as RK3568. This is not +handled using fallback compatibles to avoid exposing multiple +video devices on kernels not having the multicore disable +patch. + +Signed-off-by: Sebastian Reichel +--- + drivers/media/platform/verisilicon/hantro_drv.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/verisilicon/hantro_drv.c ++++ b/drivers/media/platform/verisilicon/hantro_drv.c +@@ -722,6 +722,7 @@ static const struct of_device_id of_hantro_match[] = { + { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, + { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, }, + { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, ++ { .compatible = "rockchip,rk3588-vepu121", .data = &rk3568_vepu_variant, }, + { .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, }, + #endif + #ifdef CONFIG_VIDEO_HANTRO_IMX8M +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 13 Jun 2024 15:48:46 +0200 +Subject: arm64: dts: rockchip: Add VEPU121 to RK3588 + +From: Emmanuel Gil Peyrot + +RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP, +but can be used as a cluster (i.e. sharing work between the cores). +These cores are called VEPU121 in the TRM. The TRM describes one more +VEPU121, but that is combined with a Hantro H1. That one will be handled +using the VPU binding instead. + +Signed-off-by: Emmanuel Gil Peyrot +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 ++++++++++ + 1 file changed, 80 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1282,6 +1282,86 @@ power-domain@RK3588_PD_SDMMC { + }; + }; + ++ vepu121_0: video-codec@fdba0000 { ++ compatible = "rockchip,rk3588-vepu121"; ++ reg = <0x0 0xfdba0000 0x0 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vepu121_0_mmu>; ++ power-domains = <&power RK3588_PD_VDPU>; ++ }; ++ ++ vepu121_0_mmu: iommu@fdba0800 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdba0800 0x0 0x40>; ++ interrupts = ; ++ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3588_PD_VDPU>; ++ #iommu-cells = <0>; ++ }; ++ ++ vepu121_1: video-codec@fdba4000 { ++ compatible = "rockchip,rk3588-vepu121"; ++ reg = <0x0 0xfdba4000 0x0 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vepu121_1_mmu>; ++ power-domains = <&power RK3588_PD_VDPU>; ++ }; ++ ++ vepu121_1_mmu: iommu@fdba4800 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdba4800 0x0 0x40>; ++ interrupts = ; ++ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3588_PD_VDPU>; ++ #iommu-cells = <0>; ++ }; ++ ++ vepu121_2: video-codec@fdba8000 { ++ compatible = "rockchip,rk3588-vepu121"; ++ reg = <0x0 0xfdba8000 0x0 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vepu121_2_mmu>; ++ power-domains = <&power RK3588_PD_VDPU>; ++ }; ++ ++ vepu121_2_mmu: iommu@fdba8800 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdba8800 0x0 0x40>; ++ interrupts = ; ++ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3588_PD_VDPU>; ++ #iommu-cells = <0>; ++ }; ++ ++ vepu121_3: video-codec@fdbac000 { ++ compatible = "rockchip,rk3588-vepu121"; ++ reg = <0x0 0xfdbac000 0x0 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vepu121_3_mmu>; ++ power-domains = <&power RK3588_PD_VDPU>; ++ }; ++ ++ vepu121_3_mmu: iommu@fdbac800 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdbac800 0x0 0x40>; ++ interrupts = ; ++ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3588_PD_VDPU>; ++ #iommu-cells = <0>; ++ }; ++ + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 13 Jun 2024 15:48:47 +0200 +Subject: arm64: dts: rockchip: Add VPU121 support for RK3588 + +From: Jianfeng Liu + +Enable Hantro G1 video decoder in RK3588's devicetree. + +Tested with FFmpeg v4l2_request code taken from [1] +with MPEG2, H.264 and VP8 samples. + +[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch + +Signed-off-by: Jianfeng Liu +Tested-by: Hugh Cole-Baker +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1282,6 +1282,28 @@ power-domain@RK3588_PD_SDMMC { + }; + }; + ++ vpu121: video-codec@fdb50000 { ++ compatible = "rockchip,rk3588-vpu121", "rockchip,rk3399-vpu"; ++ reg = <0x0 0xfdb50000 0x0 0x800>; ++ interrupts = , ++ ; ++ interrupt-names = "vepu", "vdpu"; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vpu121_mmu>; ++ power-domains = <&power RK3588_PD_VDPU>; ++ }; ++ ++ vpu121_mmu: iommu@fdb50800 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdb50800 0x0 0x40>; ++ interrupts = ; ++ clock-names = "aclk", "iface"; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ power-domains = <&power RK3588_PD_VDPU>; ++ #iommu-cells = <0>; ++ }; ++ + vepu121_0: video-codec@fdba0000 { + compatible = "rockchip,rk3588-vepu121"; + reg = <0x0 0xfdba0000 0x0 0x800>; +-- +Armbian + diff --git a/kernel.patches/0027-RK3588-Add-rkvdec2-Support-v3.patch b/kernel.patches/0027-RK3588-Add-rkvdec2-Support-v3.patch new file mode 100644 index 0000000..8f1f4ce --- /dev/null +++ b/kernel.patches/0027-RK3588-Add-rkvdec2-Support-v3.patch @@ -0,0 +1,3746 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Thu, 20 Jun 2024 10:19:43 -0400 +Subject: media: rockchip: Move H264 CABAC table to header file + +The table will be shared with the rkvdec2 driver in following commits. + +Signed-off-by: Detlev Casanova +--- + drivers/staging/media/rkvdec/rkvdec-h264-cabac.h | 509 ++++++++++ + drivers/staging/media/rkvdec/rkvdec-h264.c | 500 +-------- + 2 files changed, 510 insertions(+), 499 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-h264-cabac.h b/drivers/staging/media/rkvdec/rkvdec-h264-cabac.h +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/staging/media/rkvdec/rkvdec-h264-cabac.h +@@ -0,0 +1,509 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++/* ++ * Define the H264 CABAC table common to rkvdec and rkvdec2 drivers. ++ */ ++ ++#ifndef RKVDEC_H264_CABAC_H_ ++#define RKVDEC_H264_CABAC_H_ ++ ++#define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n, \ ++ idc2_m, idc2_n, intra_m, intra_n) \ ++ [0][(ctxidx)] = {idc0_m, idc0_n}, \ ++ [1][(ctxidx)] = {idc1_m, idc1_n}, \ ++ [2][(ctxidx)] = {idc2_m, idc2_n}, \ ++ [3][(ctxidx)] = {intra_m, intra_n} ++ ++/* ++ * Constant CABAC table. ++ * Built from the tables described in section '9.3.1.1 Initialisation process ++ * for context variables' of the H264 spec. ++ */ ++static const s8 rkvdec_h264_cabac_table[4][464][2] = { ++ /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */ ++ CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15), ++ CABAC_ENTRY(1, 2, 54, 2, 54, 2, 54, 2, 54), ++ CABAC_ENTRY(2, 3, 74, 3, 74, 3, 74, 3, 74), ++ CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15), ++ CABAC_ENTRY(4, 2, 54, 2, 54, 2, 54, 2, 54), ++ CABAC_ENTRY(5, 3, 74, 3, 74, 3, 74, 3, 74), ++ CABAC_ENTRY(6, -28, 127, -28, 127, -28, 127, -28, 127), ++ CABAC_ENTRY(7, -23, 104, -23, 104, -23, 104, -23, 104), ++ CABAC_ENTRY(8, -6, 53, -6, 53, -6, 53, -6, 53), ++ CABAC_ENTRY(9, -1, 54, -1, 54, -1, 54, -1, 54), ++ CABAC_ENTRY(10, 7, 51, 7, 51, 7, 51, 7, 51), ++ ++ /* Table 9-13 – Values of variables m and n for ctxIdx from 11 to 23 */ ++ CABAC_ENTRY(11, 23, 33, 22, 25, 29, 16, 0, 0), ++ CABAC_ENTRY(12, 23, 2, 34, 0, 25, 0, 0, 0), ++ CABAC_ENTRY(13, 21, 0, 16, 0, 14, 0, 0, 0), ++ CABAC_ENTRY(14, 1, 9, -2, 9, -10, 51, 0, 0), ++ CABAC_ENTRY(15, 0, 49, 4, 41, -3, 62, 0, 0), ++ CABAC_ENTRY(16, -37, 118, -29, 118, -27, 99, 0, 0), ++ CABAC_ENTRY(17, 5, 57, 2, 65, 26, 16, 0, 0), ++ CABAC_ENTRY(18, -13, 78, -6, 71, -4, 85, 0, 0), ++ CABAC_ENTRY(19, -11, 65, -13, 79, -24, 102, 0, 0), ++ CABAC_ENTRY(20, 1, 62, 5, 52, 5, 57, 0, 0), ++ CABAC_ENTRY(21, 12, 49, 9, 50, 6, 57, 0, 0), ++ CABAC_ENTRY(22, -4, 73, -3, 70, -17, 73, 0, 0), ++ CABAC_ENTRY(23, 17, 50, 10, 54, 14, 57, 0, 0), ++ ++ /* Table 9-14 – Values of variables m and n for ctxIdx from 24 to 39 */ ++ CABAC_ENTRY(24, 18, 64, 26, 34, 20, 40, 0, 0), ++ CABAC_ENTRY(25, 9, 43, 19, 22, 20, 10, 0, 0), ++ CABAC_ENTRY(26, 29, 0, 40, 0, 29, 0, 0, 0), ++ CABAC_ENTRY(27, 26, 67, 57, 2, 54, 0, 0, 0), ++ CABAC_ENTRY(28, 16, 90, 41, 36, 37, 42, 0, 0), ++ CABAC_ENTRY(29, 9, 104, 26, 69, 12, 97, 0, 0), ++ CABAC_ENTRY(30, -46, 127, -45, 127, -32, 127, 0, 0), ++ CABAC_ENTRY(31, -20, 104, -15, 101, -22, 117, 0, 0), ++ CABAC_ENTRY(32, 1, 67, -4, 76, -2, 74, 0, 0), ++ CABAC_ENTRY(33, -13, 78, -6, 71, -4, 85, 0, 0), ++ CABAC_ENTRY(34, -11, 65, -13, 79, -24, 102, 0, 0), ++ CABAC_ENTRY(35, 1, 62, 5, 52, 5, 57, 0, 0), ++ CABAC_ENTRY(36, -6, 86, 6, 69, -6, 93, 0, 0), ++ CABAC_ENTRY(37, -17, 95, -13, 90, -14, 88, 0, 0), ++ CABAC_ENTRY(38, -6, 61, 0, 52, -6, 44, 0, 0), ++ CABAC_ENTRY(39, 9, 45, 8, 43, 4, 55, 0, 0), ++ ++ /* Table 9-15 – Values of variables m and n for ctxIdx from 40 to 53 */ ++ CABAC_ENTRY(40, -3, 69, -2, 69, -11, 89, 0, 0), ++ CABAC_ENTRY(41, -6, 81, -5, 82, -15, 103, 0, 0), ++ CABAC_ENTRY(42, -11, 96, -10, 96, -21, 116, 0, 0), ++ CABAC_ENTRY(43, 6, 55, 2, 59, 19, 57, 0, 0), ++ CABAC_ENTRY(44, 7, 67, 2, 75, 20, 58, 0, 0), ++ CABAC_ENTRY(45, -5, 86, -3, 87, 4, 84, 0, 0), ++ CABAC_ENTRY(46, 2, 88, -3, 100, 6, 96, 0, 0), ++ CABAC_ENTRY(47, 0, 58, 1, 56, 1, 63, 0, 0), ++ CABAC_ENTRY(48, -3, 76, -3, 74, -5, 85, 0, 0), ++ CABAC_ENTRY(49, -10, 94, -6, 85, -13, 106, 0, 0), ++ CABAC_ENTRY(50, 5, 54, 0, 59, 5, 63, 0, 0), ++ CABAC_ENTRY(51, 4, 69, -3, 81, 6, 75, 0, 0), ++ CABAC_ENTRY(52, -3, 81, -7, 86, -3, 90, 0, 0), ++ CABAC_ENTRY(53, 0, 88, -5, 95, -1, 101, 0, 0), ++ ++ /* Table 9-16 – Values of variables m and n for ctxIdx from 54 to 59 */ ++ CABAC_ENTRY(54, -7, 67, -1, 66, 3, 55, 0, 0), ++ CABAC_ENTRY(55, -5, 74, -1, 77, -4, 79, 0, 0), ++ CABAC_ENTRY(56, -4, 74, 1, 70, -2, 75, 0, 0), ++ CABAC_ENTRY(57, -5, 80, -2, 86, -12, 97, 0, 0), ++ CABAC_ENTRY(58, -7, 72, -5, 72, -7, 50, 0, 0), ++ CABAC_ENTRY(59, 1, 58, 0, 61, 1, 60, 0, 0), ++ ++ /* Table 9-17 – Values of variables m and n for ctxIdx from 60 to 69 */ ++ CABAC_ENTRY(60, 0, 41, 0, 41, 0, 41, 0, 41), ++ CABAC_ENTRY(61, 0, 63, 0, 63, 0, 63, 0, 63), ++ CABAC_ENTRY(62, 0, 63, 0, 63, 0, 63, 0, 63), ++ CABAC_ENTRY(63, 0, 63, 0, 63, 0, 63, 0, 63), ++ CABAC_ENTRY(64, -9, 83, -9, 83, -9, 83, -9, 83), ++ CABAC_ENTRY(65, 4, 86, 4, 86, 4, 86, 4, 86), ++ CABAC_ENTRY(66, 0, 97, 0, 97, 0, 97, 0, 97), ++ CABAC_ENTRY(67, -7, 72, -7, 72, -7, 72, -7, 72), ++ CABAC_ENTRY(68, 13, 41, 13, 41, 13, 41, 13, 41), ++ CABAC_ENTRY(69, 3, 62, 3, 62, 3, 62, 3, 62), ++ ++ /* Table 9-18 – Values of variables m and n for ctxIdx from 70 to 104 */ ++ CABAC_ENTRY(70, 0, 45, 13, 15, 7, 34, 0, 11), ++ CABAC_ENTRY(71, -4, 78, 7, 51, -9, 88, 1, 55), ++ CABAC_ENTRY(72, -3, 96, 2, 80, -20, 127, 0, 69), ++ CABAC_ENTRY(73, -27, 126, -39, 127, -36, 127, -17, 127), ++ CABAC_ENTRY(74, -28, 98, -18, 91, -17, 91, -13, 102), ++ CABAC_ENTRY(75, -25, 101, -17, 96, -14, 95, 0, 82), ++ CABAC_ENTRY(76, -23, 67, -26, 81, -25, 84, -7, 74), ++ CABAC_ENTRY(77, -28, 82, -35, 98, -25, 86, -21, 107), ++ CABAC_ENTRY(78, -20, 94, -24, 102, -12, 89, -27, 127), ++ CABAC_ENTRY(79, -16, 83, -23, 97, -17, 91, -31, 127), ++ CABAC_ENTRY(80, -22, 110, -27, 119, -31, 127, -24, 127), ++ CABAC_ENTRY(81, -21, 91, -24, 99, -14, 76, -18, 95), ++ CABAC_ENTRY(82, -18, 102, -21, 110, -18, 103, -27, 127), ++ CABAC_ENTRY(83, -13, 93, -18, 102, -13, 90, -21, 114), ++ CABAC_ENTRY(84, -29, 127, -36, 127, -37, 127, -30, 127), ++ CABAC_ENTRY(85, -7, 92, 0, 80, 11, 80, -17, 123), ++ CABAC_ENTRY(86, -5, 89, -5, 89, 5, 76, -12, 115), ++ CABAC_ENTRY(87, -7, 96, -7, 94, 2, 84, -16, 122), ++ CABAC_ENTRY(88, -13, 108, -4, 92, 5, 78, -11, 115), ++ CABAC_ENTRY(89, -3, 46, 0, 39, -6, 55, -12, 63), ++ CABAC_ENTRY(90, -1, 65, 0, 65, 4, 61, -2, 68), ++ CABAC_ENTRY(91, -1, 57, -15, 84, -14, 83, -15, 84), ++ CABAC_ENTRY(92, -9, 93, -35, 127, -37, 127, -13, 104), ++ CABAC_ENTRY(93, -3, 74, -2, 73, -5, 79, -3, 70), ++ CABAC_ENTRY(94, -9, 92, -12, 104, -11, 104, -8, 93), ++ CABAC_ENTRY(95, -8, 87, -9, 91, -11, 91, -10, 90), ++ CABAC_ENTRY(96, -23, 126, -31, 127, -30, 127, -30, 127), ++ CABAC_ENTRY(97, 5, 54, 3, 55, 0, 65, -1, 74), ++ CABAC_ENTRY(98, 6, 60, 7, 56, -2, 79, -6, 97), ++ CABAC_ENTRY(99, 6, 59, 7, 55, 0, 72, -7, 91), ++ CABAC_ENTRY(100, 6, 69, 8, 61, -4, 92, -20, 127), ++ CABAC_ENTRY(101, -1, 48, -3, 53, -6, 56, -4, 56), ++ CABAC_ENTRY(102, 0, 68, 0, 68, 3, 68, -5, 82), ++ CABAC_ENTRY(103, -4, 69, -7, 74, -8, 71, -7, 76), ++ CABAC_ENTRY(104, -8, 88, -9, 88, -13, 98, -22, 125), ++ ++ /* Table 9-19 – Values of variables m and n for ctxIdx from 105 to 165 */ ++ CABAC_ENTRY(105, -2, 85, -13, 103, -4, 86, -7, 93), ++ CABAC_ENTRY(106, -6, 78, -13, 91, -12, 88, -11, 87), ++ CABAC_ENTRY(107, -1, 75, -9, 89, -5, 82, -3, 77), ++ CABAC_ENTRY(108, -7, 77, -14, 92, -3, 72, -5, 71), ++ CABAC_ENTRY(109, 2, 54, -8, 76, -4, 67, -4, 63), ++ CABAC_ENTRY(110, 5, 50, -12, 87, -8, 72, -4, 68), ++ CABAC_ENTRY(111, -3, 68, -23, 110, -16, 89, -12, 84), ++ CABAC_ENTRY(112, 1, 50, -24, 105, -9, 69, -7, 62), ++ CABAC_ENTRY(113, 6, 42, -10, 78, -1, 59, -7, 65), ++ CABAC_ENTRY(114, -4, 81, -20, 112, 5, 66, 8, 61), ++ CABAC_ENTRY(115, 1, 63, -17, 99, 4, 57, 5, 56), ++ CABAC_ENTRY(116, -4, 70, -78, 127, -4, 71, -2, 66), ++ CABAC_ENTRY(117, 0, 67, -70, 127, -2, 71, 1, 64), ++ CABAC_ENTRY(118, 2, 57, -50, 127, 2, 58, 0, 61), ++ CABAC_ENTRY(119, -2, 76, -46, 127, -1, 74, -2, 78), ++ CABAC_ENTRY(120, 11, 35, -4, 66, -4, 44, 1, 50), ++ CABAC_ENTRY(121, 4, 64, -5, 78, -1, 69, 7, 52), ++ CABAC_ENTRY(122, 1, 61, -4, 71, 0, 62, 10, 35), ++ CABAC_ENTRY(123, 11, 35, -8, 72, -7, 51, 0, 44), ++ CABAC_ENTRY(124, 18, 25, 2, 59, -4, 47, 11, 38), ++ CABAC_ENTRY(125, 12, 24, -1, 55, -6, 42, 1, 45), ++ CABAC_ENTRY(126, 13, 29, -7, 70, -3, 41, 0, 46), ++ CABAC_ENTRY(127, 13, 36, -6, 75, -6, 53, 5, 44), ++ CABAC_ENTRY(128, -10, 93, -8, 89, 8, 76, 31, 17), ++ CABAC_ENTRY(129, -7, 73, -34, 119, -9, 78, 1, 51), ++ CABAC_ENTRY(130, -2, 73, -3, 75, -11, 83, 7, 50), ++ CABAC_ENTRY(131, 13, 46, 32, 20, 9, 52, 28, 19), ++ CABAC_ENTRY(132, 9, 49, 30, 22, 0, 67, 16, 33), ++ CABAC_ENTRY(133, -7, 100, -44, 127, -5, 90, 14, 62), ++ CABAC_ENTRY(134, 9, 53, 0, 54, 1, 67, -13, 108), ++ CABAC_ENTRY(135, 2, 53, -5, 61, -15, 72, -15, 100), ++ CABAC_ENTRY(136, 5, 53, 0, 58, -5, 75, -13, 101), ++ CABAC_ENTRY(137, -2, 61, -1, 60, -8, 80, -13, 91), ++ CABAC_ENTRY(138, 0, 56, -3, 61, -21, 83, -12, 94), ++ CABAC_ENTRY(139, 0, 56, -8, 67, -21, 64, -10, 88), ++ CABAC_ENTRY(140, -13, 63, -25, 84, -13, 31, -16, 84), ++ CABAC_ENTRY(141, -5, 60, -14, 74, -25, 64, -10, 86), ++ CABAC_ENTRY(142, -1, 62, -5, 65, -29, 94, -7, 83), ++ CABAC_ENTRY(143, 4, 57, 5, 52, 9, 75, -13, 87), ++ CABAC_ENTRY(144, -6, 69, 2, 57, 17, 63, -19, 94), ++ CABAC_ENTRY(145, 4, 57, 0, 61, -8, 74, 1, 70), ++ CABAC_ENTRY(146, 14, 39, -9, 69, -5, 35, 0, 72), ++ CABAC_ENTRY(147, 4, 51, -11, 70, -2, 27, -5, 74), ++ CABAC_ENTRY(148, 13, 68, 18, 55, 13, 91, 18, 59), ++ CABAC_ENTRY(149, 3, 64, -4, 71, 3, 65, -8, 102), ++ CABAC_ENTRY(150, 1, 61, 0, 58, -7, 69, -15, 100), ++ CABAC_ENTRY(151, 9, 63, 7, 61, 8, 77, 0, 95), ++ CABAC_ENTRY(152, 7, 50, 9, 41, -10, 66, -4, 75), ++ CABAC_ENTRY(153, 16, 39, 18, 25, 3, 62, 2, 72), ++ CABAC_ENTRY(154, 5, 44, 9, 32, -3, 68, -11, 75), ++ CABAC_ENTRY(155, 4, 52, 5, 43, -20, 81, -3, 71), ++ CABAC_ENTRY(156, 11, 48, 9, 47, 0, 30, 15, 46), ++ CABAC_ENTRY(157, -5, 60, 0, 44, 1, 7, -13, 69), ++ CABAC_ENTRY(158, -1, 59, 0, 51, -3, 23, 0, 62), ++ CABAC_ENTRY(159, 0, 59, 2, 46, -21, 74, 0, 65), ++ CABAC_ENTRY(160, 22, 33, 19, 38, 16, 66, 21, 37), ++ CABAC_ENTRY(161, 5, 44, -4, 66, -23, 124, -15, 72), ++ CABAC_ENTRY(162, 14, 43, 15, 38, 17, 37, 9, 57), ++ CABAC_ENTRY(163, -1, 78, 12, 42, 44, -18, 16, 54), ++ CABAC_ENTRY(164, 0, 60, 9, 34, 50, -34, 0, 62), ++ CABAC_ENTRY(165, 9, 69, 0, 89, -22, 127, 12, 72), ++ ++ /* Table 9-20 – Values of variables m and n for ctxIdx from 166 to 226 */ ++ CABAC_ENTRY(166, 11, 28, 4, 45, 4, 39, 24, 0), ++ CABAC_ENTRY(167, 2, 40, 10, 28, 0, 42, 15, 9), ++ CABAC_ENTRY(168, 3, 44, 10, 31, 7, 34, 8, 25), ++ CABAC_ENTRY(169, 0, 49, 33, -11, 11, 29, 13, 18), ++ CABAC_ENTRY(170, 0, 46, 52, -43, 8, 31, 15, 9), ++ CABAC_ENTRY(171, 2, 44, 18, 15, 6, 37, 13, 19), ++ CABAC_ENTRY(172, 2, 51, 28, 0, 7, 42, 10, 37), ++ CABAC_ENTRY(173, 0, 47, 35, -22, 3, 40, 12, 18), ++ CABAC_ENTRY(174, 4, 39, 38, -25, 8, 33, 6, 29), ++ CABAC_ENTRY(175, 2, 62, 34, 0, 13, 43, 20, 33), ++ CABAC_ENTRY(176, 6, 46, 39, -18, 13, 36, 15, 30), ++ CABAC_ENTRY(177, 0, 54, 32, -12, 4, 47, 4, 45), ++ CABAC_ENTRY(178, 3, 54, 102, -94, 3, 55, 1, 58), ++ CABAC_ENTRY(179, 2, 58, 0, 0, 2, 58, 0, 62), ++ CABAC_ENTRY(180, 4, 63, 56, -15, 6, 60, 7, 61), ++ CABAC_ENTRY(181, 6, 51, 33, -4, 8, 44, 12, 38), ++ CABAC_ENTRY(182, 6, 57, 29, 10, 11, 44, 11, 45), ++ CABAC_ENTRY(183, 7, 53, 37, -5, 14, 42, 15, 39), ++ CABAC_ENTRY(184, 6, 52, 51, -29, 7, 48, 11, 42), ++ CABAC_ENTRY(185, 6, 55, 39, -9, 4, 56, 13, 44), ++ CABAC_ENTRY(186, 11, 45, 52, -34, 4, 52, 16, 45), ++ CABAC_ENTRY(187, 14, 36, 69, -58, 13, 37, 12, 41), ++ CABAC_ENTRY(188, 8, 53, 67, -63, 9, 49, 10, 49), ++ CABAC_ENTRY(189, -1, 82, 44, -5, 19, 58, 30, 34), ++ CABAC_ENTRY(190, 7, 55, 32, 7, 10, 48, 18, 42), ++ CABAC_ENTRY(191, -3, 78, 55, -29, 12, 45, 10, 55), ++ CABAC_ENTRY(192, 15, 46, 32, 1, 0, 69, 17, 51), ++ CABAC_ENTRY(193, 22, 31, 0, 0, 20, 33, 17, 46), ++ CABAC_ENTRY(194, -1, 84, 27, 36, 8, 63, 0, 89), ++ CABAC_ENTRY(195, 25, 7, 33, -25, 35, -18, 26, -19), ++ CABAC_ENTRY(196, 30, -7, 34, -30, 33, -25, 22, -17), ++ CABAC_ENTRY(197, 28, 3, 36, -28, 28, -3, 26, -17), ++ CABAC_ENTRY(198, 28, 4, 38, -28, 24, 10, 30, -25), ++ CABAC_ENTRY(199, 32, 0, 38, -27, 27, 0, 28, -20), ++ CABAC_ENTRY(200, 34, -1, 34, -18, 34, -14, 33, -23), ++ CABAC_ENTRY(201, 30, 6, 35, -16, 52, -44, 37, -27), ++ CABAC_ENTRY(202, 30, 6, 34, -14, 39, -24, 33, -23), ++ CABAC_ENTRY(203, 32, 9, 32, -8, 19, 17, 40, -28), ++ CABAC_ENTRY(204, 31, 19, 37, -6, 31, 25, 38, -17), ++ CABAC_ENTRY(205, 26, 27, 35, 0, 36, 29, 33, -11), ++ CABAC_ENTRY(206, 26, 30, 30, 10, 24, 33, 40, -15), ++ CABAC_ENTRY(207, 37, 20, 28, 18, 34, 15, 41, -6), ++ CABAC_ENTRY(208, 28, 34, 26, 25, 30, 20, 38, 1), ++ CABAC_ENTRY(209, 17, 70, 29, 41, 22, 73, 41, 17), ++ CABAC_ENTRY(210, 1, 67, 0, 75, 20, 34, 30, -6), ++ CABAC_ENTRY(211, 5, 59, 2, 72, 19, 31, 27, 3), ++ CABAC_ENTRY(212, 9, 67, 8, 77, 27, 44, 26, 22), ++ CABAC_ENTRY(213, 16, 30, 14, 35, 19, 16, 37, -16), ++ CABAC_ENTRY(214, 18, 32, 18, 31, 15, 36, 35, -4), ++ CABAC_ENTRY(215, 18, 35, 17, 35, 15, 36, 38, -8), ++ CABAC_ENTRY(216, 22, 29, 21, 30, 21, 28, 38, -3), ++ CABAC_ENTRY(217, 24, 31, 17, 45, 25, 21, 37, 3), ++ CABAC_ENTRY(218, 23, 38, 20, 42, 30, 20, 38, 5), ++ CABAC_ENTRY(219, 18, 43, 18, 45, 31, 12, 42, 0), ++ CABAC_ENTRY(220, 20, 41, 27, 26, 27, 16, 35, 16), ++ CABAC_ENTRY(221, 11, 63, 16, 54, 24, 42, 39, 22), ++ CABAC_ENTRY(222, 9, 59, 7, 66, 0, 93, 14, 48), ++ CABAC_ENTRY(223, 9, 64, 16, 56, 14, 56, 27, 37), ++ CABAC_ENTRY(224, -1, 94, 11, 73, 15, 57, 21, 60), ++ CABAC_ENTRY(225, -2, 89, 10, 67, 26, 38, 12, 68), ++ CABAC_ENTRY(226, -9, 108, -10, 116, -24, 127, 2, 97), ++ ++ /* Table 9-21 – Values of variables m and n for ctxIdx from 227 to 275 */ ++ CABAC_ENTRY(227, -6, 76, -23, 112, -24, 115, -3, 71), ++ CABAC_ENTRY(228, -2, 44, -15, 71, -22, 82, -6, 42), ++ CABAC_ENTRY(229, 0, 45, -7, 61, -9, 62, -5, 50), ++ CABAC_ENTRY(230, 0, 52, 0, 53, 0, 53, -3, 54), ++ CABAC_ENTRY(231, -3, 64, -5, 66, 0, 59, -2, 62), ++ CABAC_ENTRY(232, -2, 59, -11, 77, -14, 85, 0, 58), ++ CABAC_ENTRY(233, -4, 70, -9, 80, -13, 89, 1, 63), ++ CABAC_ENTRY(234, -4, 75, -9, 84, -13, 94, -2, 72), ++ CABAC_ENTRY(235, -8, 82, -10, 87, -11, 92, -1, 74), ++ CABAC_ENTRY(236, -17, 102, -34, 127, -29, 127, -9, 91), ++ CABAC_ENTRY(237, -9, 77, -21, 101, -21, 100, -5, 67), ++ CABAC_ENTRY(238, 3, 24, -3, 39, -14, 57, -5, 27), ++ CABAC_ENTRY(239, 0, 42, -5, 53, -12, 67, -3, 39), ++ CABAC_ENTRY(240, 0, 48, -7, 61, -11, 71, -2, 44), ++ CABAC_ENTRY(241, 0, 55, -11, 75, -10, 77, 0, 46), ++ CABAC_ENTRY(242, -6, 59, -15, 77, -21, 85, -16, 64), ++ CABAC_ENTRY(243, -7, 71, -17, 91, -16, 88, -8, 68), ++ CABAC_ENTRY(244, -12, 83, -25, 107, -23, 104, -10, 78), ++ CABAC_ENTRY(245, -11, 87, -25, 111, -15, 98, -6, 77), ++ CABAC_ENTRY(246, -30, 119, -28, 122, -37, 127, -10, 86), ++ CABAC_ENTRY(247, 1, 58, -11, 76, -10, 82, -12, 92), ++ CABAC_ENTRY(248, -3, 29, -10, 44, -8, 48, -15, 55), ++ CABAC_ENTRY(249, -1, 36, -10, 52, -8, 61, -10, 60), ++ CABAC_ENTRY(250, 1, 38, -10, 57, -8, 66, -6, 62), ++ CABAC_ENTRY(251, 2, 43, -9, 58, -7, 70, -4, 65), ++ CABAC_ENTRY(252, -6, 55, -16, 72, -14, 75, -12, 73), ++ CABAC_ENTRY(253, 0, 58, -7, 69, -10, 79, -8, 76), ++ CABAC_ENTRY(254, 0, 64, -4, 69, -9, 83, -7, 80), ++ CABAC_ENTRY(255, -3, 74, -5, 74, -12, 92, -9, 88), ++ CABAC_ENTRY(256, -10, 90, -9, 86, -18, 108, -17, 110), ++ CABAC_ENTRY(257, 0, 70, 2, 66, -4, 79, -11, 97), ++ CABAC_ENTRY(258, -4, 29, -9, 34, -22, 69, -20, 84), ++ CABAC_ENTRY(259, 5, 31, 1, 32, -16, 75, -11, 79), ++ CABAC_ENTRY(260, 7, 42, 11, 31, -2, 58, -6, 73), ++ CABAC_ENTRY(261, 1, 59, 5, 52, 1, 58, -4, 74), ++ CABAC_ENTRY(262, -2, 58, -2, 55, -13, 78, -13, 86), ++ CABAC_ENTRY(263, -3, 72, -2, 67, -9, 83, -13, 96), ++ CABAC_ENTRY(264, -3, 81, 0, 73, -4, 81, -11, 97), ++ CABAC_ENTRY(265, -11, 97, -8, 89, -13, 99, -19, 117), ++ CABAC_ENTRY(266, 0, 58, 3, 52, -13, 81, -8, 78), ++ CABAC_ENTRY(267, 8, 5, 7, 4, -6, 38, -5, 33), ++ CABAC_ENTRY(268, 10, 14, 10, 8, -13, 62, -4, 48), ++ CABAC_ENTRY(269, 14, 18, 17, 8, -6, 58, -2, 53), ++ CABAC_ENTRY(270, 13, 27, 16, 19, -2, 59, -3, 62), ++ CABAC_ENTRY(271, 2, 40, 3, 37, -16, 73, -13, 71), ++ CABAC_ENTRY(272, 0, 58, -1, 61, -10, 76, -10, 79), ++ CABAC_ENTRY(273, -3, 70, -5, 73, -13, 86, -12, 86), ++ CABAC_ENTRY(274, -6, 79, -1, 70, -9, 83, -13, 90), ++ CABAC_ENTRY(275, -8, 85, -4, 78, -10, 87, -14, 97), ++ ++ /* Table 9-22 – Values of variables m and n for ctxIdx from 277 to 337 */ ++ CABAC_ENTRY(277, -13, 106, -21, 126, -22, 127, -6, 93), ++ CABAC_ENTRY(278, -16, 106, -23, 124, -25, 127, -6, 84), ++ CABAC_ENTRY(279, -10, 87, -20, 110, -25, 120, -8, 79), ++ CABAC_ENTRY(280, -21, 114, -26, 126, -27, 127, 0, 66), ++ CABAC_ENTRY(281, -18, 110, -25, 124, -19, 114, -1, 71), ++ CABAC_ENTRY(282, -14, 98, -17, 105, -23, 117, 0, 62), ++ CABAC_ENTRY(283, -22, 110, -27, 121, -25, 118, -2, 60), ++ CABAC_ENTRY(284, -21, 106, -27, 117, -26, 117, -2, 59), ++ CABAC_ENTRY(285, -18, 103, -17, 102, -24, 113, -5, 75), ++ CABAC_ENTRY(286, -21, 107, -26, 117, -28, 118, -3, 62), ++ CABAC_ENTRY(287, -23, 108, -27, 116, -31, 120, -4, 58), ++ CABAC_ENTRY(288, -26, 112, -33, 122, -37, 124, -9, 66), ++ CABAC_ENTRY(289, -10, 96, -10, 95, -10, 94, -1, 79), ++ CABAC_ENTRY(290, -12, 95, -14, 100, -15, 102, 0, 71), ++ CABAC_ENTRY(291, -5, 91, -8, 95, -10, 99, 3, 68), ++ CABAC_ENTRY(292, -9, 93, -17, 111, -13, 106, 10, 44), ++ CABAC_ENTRY(293, -22, 94, -28, 114, -50, 127, -7, 62), ++ CABAC_ENTRY(294, -5, 86, -6, 89, -5, 92, 15, 36), ++ CABAC_ENTRY(295, 9, 67, -2, 80, 17, 57, 14, 40), ++ CABAC_ENTRY(296, -4, 80, -4, 82, -5, 86, 16, 27), ++ CABAC_ENTRY(297, -10, 85, -9, 85, -13, 94, 12, 29), ++ CABAC_ENTRY(298, -1, 70, -8, 81, -12, 91, 1, 44), ++ CABAC_ENTRY(299, 7, 60, -1, 72, -2, 77, 20, 36), ++ CABAC_ENTRY(300, 9, 58, 5, 64, 0, 71, 18, 32), ++ CABAC_ENTRY(301, 5, 61, 1, 67, -1, 73, 5, 42), ++ CABAC_ENTRY(302, 12, 50, 9, 56, 4, 64, 1, 48), ++ CABAC_ENTRY(303, 15, 50, 0, 69, -7, 81, 10, 62), ++ CABAC_ENTRY(304, 18, 49, 1, 69, 5, 64, 17, 46), ++ CABAC_ENTRY(305, 17, 54, 7, 69, 15, 57, 9, 64), ++ CABAC_ENTRY(306, 10, 41, -7, 69, 1, 67, -12, 104), ++ CABAC_ENTRY(307, 7, 46, -6, 67, 0, 68, -11, 97), ++ CABAC_ENTRY(308, -1, 51, -16, 77, -10, 67, -16, 96), ++ CABAC_ENTRY(309, 7, 49, -2, 64, 1, 68, -7, 88), ++ CABAC_ENTRY(310, 8, 52, 2, 61, 0, 77, -8, 85), ++ CABAC_ENTRY(311, 9, 41, -6, 67, 2, 64, -7, 85), ++ CABAC_ENTRY(312, 6, 47, -3, 64, 0, 68, -9, 85), ++ CABAC_ENTRY(313, 2, 55, 2, 57, -5, 78, -13, 88), ++ CABAC_ENTRY(314, 13, 41, -3, 65, 7, 55, 4, 66), ++ CABAC_ENTRY(315, 10, 44, -3, 66, 5, 59, -3, 77), ++ CABAC_ENTRY(316, 6, 50, 0, 62, 2, 65, -3, 76), ++ CABAC_ENTRY(317, 5, 53, 9, 51, 14, 54, -6, 76), ++ CABAC_ENTRY(318, 13, 49, -1, 66, 15, 44, 10, 58), ++ CABAC_ENTRY(319, 4, 63, -2, 71, 5, 60, -1, 76), ++ CABAC_ENTRY(320, 6, 64, -2, 75, 2, 70, -1, 83), ++ CABAC_ENTRY(321, -2, 69, -1, 70, -2, 76, -7, 99), ++ CABAC_ENTRY(322, -2, 59, -9, 72, -18, 86, -14, 95), ++ CABAC_ENTRY(323, 6, 70, 14, 60, 12, 70, 2, 95), ++ CABAC_ENTRY(324, 10, 44, 16, 37, 5, 64, 0, 76), ++ CABAC_ENTRY(325, 9, 31, 0, 47, -12, 70, -5, 74), ++ CABAC_ENTRY(326, 12, 43, 18, 35, 11, 55, 0, 70), ++ CABAC_ENTRY(327, 3, 53, 11, 37, 5, 56, -11, 75), ++ CABAC_ENTRY(328, 14, 34, 12, 41, 0, 69, 1, 68), ++ CABAC_ENTRY(329, 10, 38, 10, 41, 2, 65, 0, 65), ++ CABAC_ENTRY(330, -3, 52, 2, 48, -6, 74, -14, 73), ++ CABAC_ENTRY(331, 13, 40, 12, 41, 5, 54, 3, 62), ++ CABAC_ENTRY(332, 17, 32, 13, 41, 7, 54, 4, 62), ++ CABAC_ENTRY(333, 7, 44, 0, 59, -6, 76, -1, 68), ++ CABAC_ENTRY(334, 7, 38, 3, 50, -11, 82, -13, 75), ++ CABAC_ENTRY(335, 13, 50, 19, 40, -2, 77, 11, 55), ++ CABAC_ENTRY(336, 10, 57, 3, 66, -2, 77, 5, 64), ++ CABAC_ENTRY(337, 26, 43, 18, 50, 25, 42, 12, 70), ++ ++ /* Table 9-23 – Values of variables m and n for ctxIdx from 338 to 398 */ ++ CABAC_ENTRY(338, 14, 11, 19, -6, 17, -13, 15, 6), ++ CABAC_ENTRY(339, 11, 14, 18, -6, 16, -9, 6, 19), ++ CABAC_ENTRY(340, 9, 11, 14, 0, 17, -12, 7, 16), ++ CABAC_ENTRY(341, 18, 11, 26, -12, 27, -21, 12, 14), ++ CABAC_ENTRY(342, 21, 9, 31, -16, 37, -30, 18, 13), ++ CABAC_ENTRY(343, 23, -2, 33, -25, 41, -40, 13, 11), ++ CABAC_ENTRY(344, 32, -15, 33, -22, 42, -41, 13, 15), ++ CABAC_ENTRY(345, 32, -15, 37, -28, 48, -47, 15, 16), ++ CABAC_ENTRY(346, 34, -21, 39, -30, 39, -32, 12, 23), ++ CABAC_ENTRY(347, 39, -23, 42, -30, 46, -40, 13, 23), ++ CABAC_ENTRY(348, 42, -33, 47, -42, 52, -51, 15, 20), ++ CABAC_ENTRY(349, 41, -31, 45, -36, 46, -41, 14, 26), ++ CABAC_ENTRY(350, 46, -28, 49, -34, 52, -39, 14, 44), ++ CABAC_ENTRY(351, 38, -12, 41, -17, 43, -19, 17, 40), ++ CABAC_ENTRY(352, 21, 29, 32, 9, 32, 11, 17, 47), ++ CABAC_ENTRY(353, 45, -24, 69, -71, 61, -55, 24, 17), ++ CABAC_ENTRY(354, 53, -45, 63, -63, 56, -46, 21, 21), ++ CABAC_ENTRY(355, 48, -26, 66, -64, 62, -50, 25, 22), ++ CABAC_ENTRY(356, 65, -43, 77, -74, 81, -67, 31, 27), ++ CABAC_ENTRY(357, 43, -19, 54, -39, 45, -20, 22, 29), ++ CABAC_ENTRY(358, 39, -10, 52, -35, 35, -2, 19, 35), ++ CABAC_ENTRY(359, 30, 9, 41, -10, 28, 15, 14, 50), ++ CABAC_ENTRY(360, 18, 26, 36, 0, 34, 1, 10, 57), ++ CABAC_ENTRY(361, 20, 27, 40, -1, 39, 1, 7, 63), ++ CABAC_ENTRY(362, 0, 57, 30, 14, 30, 17, -2, 77), ++ CABAC_ENTRY(363, -14, 82, 28, 26, 20, 38, -4, 82), ++ CABAC_ENTRY(364, -5, 75, 23, 37, 18, 45, -3, 94), ++ CABAC_ENTRY(365, -19, 97, 12, 55, 15, 54, 9, 69), ++ CABAC_ENTRY(366, -35, 125, 11, 65, 0, 79, -12, 109), ++ CABAC_ENTRY(367, 27, 0, 37, -33, 36, -16, 36, -35), ++ CABAC_ENTRY(368, 28, 0, 39, -36, 37, -14, 36, -34), ++ CABAC_ENTRY(369, 31, -4, 40, -37, 37, -17, 32, -26), ++ CABAC_ENTRY(370, 27, 6, 38, -30, 32, 1, 37, -30), ++ CABAC_ENTRY(371, 34, 8, 46, -33, 34, 15, 44, -32), ++ CABAC_ENTRY(372, 30, 10, 42, -30, 29, 15, 34, -18), ++ CABAC_ENTRY(373, 24, 22, 40, -24, 24, 25, 34, -15), ++ CABAC_ENTRY(374, 33, 19, 49, -29, 34, 22, 40, -15), ++ CABAC_ENTRY(375, 22, 32, 38, -12, 31, 16, 33, -7), ++ CABAC_ENTRY(376, 26, 31, 40, -10, 35, 18, 35, -5), ++ CABAC_ENTRY(377, 21, 41, 38, -3, 31, 28, 33, 0), ++ CABAC_ENTRY(378, 26, 44, 46, -5, 33, 41, 38, 2), ++ CABAC_ENTRY(379, 23, 47, 31, 20, 36, 28, 33, 13), ++ CABAC_ENTRY(380, 16, 65, 29, 30, 27, 47, 23, 35), ++ CABAC_ENTRY(381, 14, 71, 25, 44, 21, 62, 13, 58), ++ CABAC_ENTRY(382, 8, 60, 12, 48, 18, 31, 29, -3), ++ CABAC_ENTRY(383, 6, 63, 11, 49, 19, 26, 26, 0), ++ CABAC_ENTRY(384, 17, 65, 26, 45, 36, 24, 22, 30), ++ CABAC_ENTRY(385, 21, 24, 22, 22, 24, 23, 31, -7), ++ CABAC_ENTRY(386, 23, 20, 23, 22, 27, 16, 35, -15), ++ CABAC_ENTRY(387, 26, 23, 27, 21, 24, 30, 34, -3), ++ CABAC_ENTRY(388, 27, 32, 33, 20, 31, 29, 34, 3), ++ CABAC_ENTRY(389, 28, 23, 26, 28, 22, 41, 36, -1), ++ CABAC_ENTRY(390, 28, 24, 30, 24, 22, 42, 34, 5), ++ CABAC_ENTRY(391, 23, 40, 27, 34, 16, 60, 32, 11), ++ CABAC_ENTRY(392, 24, 32, 18, 42, 15, 52, 35, 5), ++ CABAC_ENTRY(393, 28, 29, 25, 39, 14, 60, 34, 12), ++ CABAC_ENTRY(394, 23, 42, 18, 50, 3, 78, 39, 11), ++ CABAC_ENTRY(395, 19, 57, 12, 70, -16, 123, 30, 29), ++ CABAC_ENTRY(396, 22, 53, 21, 54, 21, 53, 34, 26), ++ CABAC_ENTRY(397, 22, 61, 14, 71, 22, 56, 29, 39), ++ CABAC_ENTRY(398, 11, 86, 11, 83, 25, 61, 19, 66), ++ ++ /* Values of variables m and n for ctxIdx from 399 to 463 (not documented) */ ++ CABAC_ENTRY(399, 12, 40, 25, 32, 21, 33, 31, 21), ++ CABAC_ENTRY(400, 11, 51, 21, 49, 19, 50, 31, 31), ++ CABAC_ENTRY(401, 14, 59, 21, 54, 17, 61, 25, 50), ++ CABAC_ENTRY(402, -4, 79, -5, 85, -3, 78, -17, 120), ++ CABAC_ENTRY(403, -7, 71, -6, 81, -8, 74, -20, 112), ++ CABAC_ENTRY(404, -5, 69, -10, 77, -9, 72, -18, 114), ++ CABAC_ENTRY(405, -9, 70, -7, 81, -10, 72, -11, 85), ++ CABAC_ENTRY(406, -8, 66, -17, 80, -18, 75, -15, 92), ++ CABAC_ENTRY(407, -10, 68, -18, 73, -12, 71, -14, 89), ++ CABAC_ENTRY(408, -19, 73, -4, 74, -11, 63, -26, 71), ++ CABAC_ENTRY(409, -12, 69, -10, 83, -5, 70, -15, 81), ++ CABAC_ENTRY(410, -16, 70, -9, 71, -17, 75, -14, 80), ++ CABAC_ENTRY(411, -15, 67, -9, 67, -14, 72, 0, 68), ++ CABAC_ENTRY(412, -20, 62, -1, 61, -16, 67, -14, 70), ++ CABAC_ENTRY(413, -19, 70, -8, 66, -8, 53, -24, 56), ++ CABAC_ENTRY(414, -16, 66, -14, 66, -14, 59, -23, 68), ++ CABAC_ENTRY(415, -22, 65, 0, 59, -9, 52, -24, 50), ++ CABAC_ENTRY(416, -20, 63, 2, 59, -11, 68, -11, 74), ++ CABAC_ENTRY(417, 9, -2, 17, -10, 9, -2, 23, -13), ++ CABAC_ENTRY(418, 26, -9, 32, -13, 30, -10, 26, -13), ++ CABAC_ENTRY(419, 33, -9, 42, -9, 31, -4, 40, -15), ++ CABAC_ENTRY(420, 39, -7, 49, -5, 33, -1, 49, -14), ++ CABAC_ENTRY(421, 41, -2, 53, 0, 33, 7, 44, 3), ++ CABAC_ENTRY(422, 45, 3, 64, 3, 31, 12, 45, 6), ++ CABAC_ENTRY(423, 49, 9, 68, 10, 37, 23, 44, 34), ++ CABAC_ENTRY(424, 45, 27, 66, 27, 31, 38, 33, 54), ++ CABAC_ENTRY(425, 36, 59, 47, 57, 20, 64, 19, 82), ++ CABAC_ENTRY(426, -6, 66, -5, 71, -9, 71, -3, 75), ++ CABAC_ENTRY(427, -7, 35, 0, 24, -7, 37, -1, 23), ++ CABAC_ENTRY(428, -7, 42, -1, 36, -8, 44, 1, 34), ++ CABAC_ENTRY(429, -8, 45, -2, 42, -11, 49, 1, 43), ++ CABAC_ENTRY(430, -5, 48, -2, 52, -10, 56, 0, 54), ++ CABAC_ENTRY(431, -12, 56, -9, 57, -12, 59, -2, 55), ++ CABAC_ENTRY(432, -6, 60, -6, 63, -8, 63, 0, 61), ++ CABAC_ENTRY(433, -5, 62, -4, 65, -9, 67, 1, 64), ++ CABAC_ENTRY(434, -8, 66, -4, 67, -6, 68, 0, 68), ++ CABAC_ENTRY(435, -8, 76, -7, 82, -10, 79, -9, 92), ++ CABAC_ENTRY(436, -5, 85, -3, 81, -3, 78, -14, 106), ++ CABAC_ENTRY(437, -6, 81, -3, 76, -8, 74, -13, 97), ++ CABAC_ENTRY(438, -10, 77, -7, 72, -9, 72, -15, 90), ++ CABAC_ENTRY(439, -7, 81, -6, 78, -10, 72, -12, 90), ++ CABAC_ENTRY(440, -17, 80, -12, 72, -18, 75, -18, 88), ++ CABAC_ENTRY(441, -18, 73, -14, 68, -12, 71, -10, 73), ++ CABAC_ENTRY(442, -4, 74, -3, 70, -11, 63, -9, 79), ++ CABAC_ENTRY(443, -10, 83, -6, 76, -5, 70, -14, 86), ++ CABAC_ENTRY(444, -9, 71, -5, 66, -17, 75, -10, 73), ++ CABAC_ENTRY(445, -9, 67, -5, 62, -14, 72, -10, 70), ++ CABAC_ENTRY(446, -1, 61, 0, 57, -16, 67, -10, 69), ++ CABAC_ENTRY(447, -8, 66, -4, 61, -8, 53, -5, 66), ++ CABAC_ENTRY(448, -14, 66, -9, 60, -14, 59, -9, 64), ++ CABAC_ENTRY(449, 0, 59, 1, 54, -9, 52, -5, 58), ++ CABAC_ENTRY(450, 2, 59, 2, 58, -11, 68, 2, 59), ++ CABAC_ENTRY(451, 21, -13, 17, -10, 9, -2, 21, -10), ++ CABAC_ENTRY(452, 33, -14, 32, -13, 30, -10, 24, -11), ++ CABAC_ENTRY(453, 39, -7, 42, -9, 31, -4, 28, -8), ++ CABAC_ENTRY(454, 46, -2, 49, -5, 33, -1, 28, -1), ++ CABAC_ENTRY(455, 51, 2, 53, 0, 33, 7, 29, 3), ++ CABAC_ENTRY(456, 60, 6, 64, 3, 31, 12, 29, 9), ++ CABAC_ENTRY(457, 61, 17, 68, 10, 37, 23, 35, 20), ++ CABAC_ENTRY(458, 55, 34, 66, 27, 31, 38, 29, 36), ++ CABAC_ENTRY(459, 42, 62, 47, 57, 20, 64, 14, 67), ++}; ++ ++#endif /* RKVDEC_H264_CABAC_H_ */ +diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c +index 111111111111..222222222222 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-h264.c ++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c +@@ -14,6 +14,7 @@ + + #include "rkvdec.h" + #include "rkvdec-regs.h" ++#include "rkvdec-h264-cabac.h" + + /* Size with u32 units. */ + #define RKV_CABAC_INIT_BUFFER_SIZE (3680 + 128) +@@ -117,505 +118,6 @@ struct rkvdec_h264_ctx { + struct rkvdec_h264_reflists reflists; + }; + +-#define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n, \ +- idc2_m, idc2_n, intra_m, intra_n) \ +- [0][(ctxidx)] = {idc0_m, idc0_n}, \ +- [1][(ctxidx)] = {idc1_m, idc1_n}, \ +- [2][(ctxidx)] = {idc2_m, idc2_n}, \ +- [3][(ctxidx)] = {intra_m, intra_n} +- +-/* +- * Constant CABAC table. +- * Built from the tables described in section '9.3.1.1 Initialisation process +- * for context variables' of the H264 spec. +- */ +-static const s8 rkvdec_h264_cabac_table[4][464][2] = { +- /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */ +- CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15), +- CABAC_ENTRY(1, 2, 54, 2, 54, 2, 54, 2, 54), +- CABAC_ENTRY(2, 3, 74, 3, 74, 3, 74, 3, 74), +- CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15), +- CABAC_ENTRY(4, 2, 54, 2, 54, 2, 54, 2, 54), +- CABAC_ENTRY(5, 3, 74, 3, 74, 3, 74, 3, 74), +- CABAC_ENTRY(6, -28, 127, -28, 127, -28, 127, -28, 127), +- CABAC_ENTRY(7, -23, 104, -23, 104, -23, 104, -23, 104), +- CABAC_ENTRY(8, -6, 53, -6, 53, -6, 53, -6, 53), +- CABAC_ENTRY(9, -1, 54, -1, 54, -1, 54, -1, 54), +- CABAC_ENTRY(10, 7, 51, 7, 51, 7, 51, 7, 51), +- +- /* Table 9-13 – Values of variables m and n for ctxIdx from 11 to 23 */ +- CABAC_ENTRY(11, 23, 33, 22, 25, 29, 16, 0, 0), +- CABAC_ENTRY(12, 23, 2, 34, 0, 25, 0, 0, 0), +- CABAC_ENTRY(13, 21, 0, 16, 0, 14, 0, 0, 0), +- CABAC_ENTRY(14, 1, 9, -2, 9, -10, 51, 0, 0), +- CABAC_ENTRY(15, 0, 49, 4, 41, -3, 62, 0, 0), +- CABAC_ENTRY(16, -37, 118, -29, 118, -27, 99, 0, 0), +- CABAC_ENTRY(17, 5, 57, 2, 65, 26, 16, 0, 0), +- CABAC_ENTRY(18, -13, 78, -6, 71, -4, 85, 0, 0), +- CABAC_ENTRY(19, -11, 65, -13, 79, -24, 102, 0, 0), +- CABAC_ENTRY(20, 1, 62, 5, 52, 5, 57, 0, 0), +- CABAC_ENTRY(21, 12, 49, 9, 50, 6, 57, 0, 0), +- CABAC_ENTRY(22, -4, 73, -3, 70, -17, 73, 0, 0), +- CABAC_ENTRY(23, 17, 50, 10, 54, 14, 57, 0, 0), +- +- /* Table 9-14 – Values of variables m and n for ctxIdx from 24 to 39 */ +- CABAC_ENTRY(24, 18, 64, 26, 34, 20, 40, 0, 0), +- CABAC_ENTRY(25, 9, 43, 19, 22, 20, 10, 0, 0), +- CABAC_ENTRY(26, 29, 0, 40, 0, 29, 0, 0, 0), +- CABAC_ENTRY(27, 26, 67, 57, 2, 54, 0, 0, 0), +- CABAC_ENTRY(28, 16, 90, 41, 36, 37, 42, 0, 0), +- CABAC_ENTRY(29, 9, 104, 26, 69, 12, 97, 0, 0), +- CABAC_ENTRY(30, -46, 127, -45, 127, -32, 127, 0, 0), +- CABAC_ENTRY(31, -20, 104, -15, 101, -22, 117, 0, 0), +- CABAC_ENTRY(32, 1, 67, -4, 76, -2, 74, 0, 0), +- CABAC_ENTRY(33, -13, 78, -6, 71, -4, 85, 0, 0), +- CABAC_ENTRY(34, -11, 65, -13, 79, -24, 102, 0, 0), +- CABAC_ENTRY(35, 1, 62, 5, 52, 5, 57, 0, 0), +- CABAC_ENTRY(36, -6, 86, 6, 69, -6, 93, 0, 0), +- CABAC_ENTRY(37, -17, 95, -13, 90, -14, 88, 0, 0), +- CABAC_ENTRY(38, -6, 61, 0, 52, -6, 44, 0, 0), +- CABAC_ENTRY(39, 9, 45, 8, 43, 4, 55, 0, 0), +- +- /* Table 9-15 – Values of variables m and n for ctxIdx from 40 to 53 */ +- CABAC_ENTRY(40, -3, 69, -2, 69, -11, 89, 0, 0), +- CABAC_ENTRY(41, -6, 81, -5, 82, -15, 103, 0, 0), +- CABAC_ENTRY(42, -11, 96, -10, 96, -21, 116, 0, 0), +- CABAC_ENTRY(43, 6, 55, 2, 59, 19, 57, 0, 0), +- CABAC_ENTRY(44, 7, 67, 2, 75, 20, 58, 0, 0), +- CABAC_ENTRY(45, -5, 86, -3, 87, 4, 84, 0, 0), +- CABAC_ENTRY(46, 2, 88, -3, 100, 6, 96, 0, 0), +- CABAC_ENTRY(47, 0, 58, 1, 56, 1, 63, 0, 0), +- CABAC_ENTRY(48, -3, 76, -3, 74, -5, 85, 0, 0), +- CABAC_ENTRY(49, -10, 94, -6, 85, -13, 106, 0, 0), +- CABAC_ENTRY(50, 5, 54, 0, 59, 5, 63, 0, 0), +- CABAC_ENTRY(51, 4, 69, -3, 81, 6, 75, 0, 0), +- CABAC_ENTRY(52, -3, 81, -7, 86, -3, 90, 0, 0), +- CABAC_ENTRY(53, 0, 88, -5, 95, -1, 101, 0, 0), +- +- /* Table 9-16 – Values of variables m and n for ctxIdx from 54 to 59 */ +- CABAC_ENTRY(54, -7, 67, -1, 66, 3, 55, 0, 0), +- CABAC_ENTRY(55, -5, 74, -1, 77, -4, 79, 0, 0), +- CABAC_ENTRY(56, -4, 74, 1, 70, -2, 75, 0, 0), +- CABAC_ENTRY(57, -5, 80, -2, 86, -12, 97, 0, 0), +- CABAC_ENTRY(58, -7, 72, -5, 72, -7, 50, 0, 0), +- CABAC_ENTRY(59, 1, 58, 0, 61, 1, 60, 0, 0), +- +- /* Table 9-17 – Values of variables m and n for ctxIdx from 60 to 69 */ +- CABAC_ENTRY(60, 0, 41, 0, 41, 0, 41, 0, 41), +- CABAC_ENTRY(61, 0, 63, 0, 63, 0, 63, 0, 63), +- CABAC_ENTRY(62, 0, 63, 0, 63, 0, 63, 0, 63), +- CABAC_ENTRY(63, 0, 63, 0, 63, 0, 63, 0, 63), +- CABAC_ENTRY(64, -9, 83, -9, 83, -9, 83, -9, 83), +- CABAC_ENTRY(65, 4, 86, 4, 86, 4, 86, 4, 86), +- CABAC_ENTRY(66, 0, 97, 0, 97, 0, 97, 0, 97), +- CABAC_ENTRY(67, -7, 72, -7, 72, -7, 72, -7, 72), +- CABAC_ENTRY(68, 13, 41, 13, 41, 13, 41, 13, 41), +- CABAC_ENTRY(69, 3, 62, 3, 62, 3, 62, 3, 62), +- +- /* Table 9-18 – Values of variables m and n for ctxIdx from 70 to 104 */ +- CABAC_ENTRY(70, 0, 45, 13, 15, 7, 34, 0, 11), +- CABAC_ENTRY(71, -4, 78, 7, 51, -9, 88, 1, 55), +- CABAC_ENTRY(72, -3, 96, 2, 80, -20, 127, 0, 69), +- CABAC_ENTRY(73, -27, 126, -39, 127, -36, 127, -17, 127), +- CABAC_ENTRY(74, -28, 98, -18, 91, -17, 91, -13, 102), +- CABAC_ENTRY(75, -25, 101, -17, 96, -14, 95, 0, 82), +- CABAC_ENTRY(76, -23, 67, -26, 81, -25, 84, -7, 74), +- CABAC_ENTRY(77, -28, 82, -35, 98, -25, 86, -21, 107), +- CABAC_ENTRY(78, -20, 94, -24, 102, -12, 89, -27, 127), +- CABAC_ENTRY(79, -16, 83, -23, 97, -17, 91, -31, 127), +- CABAC_ENTRY(80, -22, 110, -27, 119, -31, 127, -24, 127), +- CABAC_ENTRY(81, -21, 91, -24, 99, -14, 76, -18, 95), +- CABAC_ENTRY(82, -18, 102, -21, 110, -18, 103, -27, 127), +- CABAC_ENTRY(83, -13, 93, -18, 102, -13, 90, -21, 114), +- CABAC_ENTRY(84, -29, 127, -36, 127, -37, 127, -30, 127), +- CABAC_ENTRY(85, -7, 92, 0, 80, 11, 80, -17, 123), +- CABAC_ENTRY(86, -5, 89, -5, 89, 5, 76, -12, 115), +- CABAC_ENTRY(87, -7, 96, -7, 94, 2, 84, -16, 122), +- CABAC_ENTRY(88, -13, 108, -4, 92, 5, 78, -11, 115), +- CABAC_ENTRY(89, -3, 46, 0, 39, -6, 55, -12, 63), +- CABAC_ENTRY(90, -1, 65, 0, 65, 4, 61, -2, 68), +- CABAC_ENTRY(91, -1, 57, -15, 84, -14, 83, -15, 84), +- CABAC_ENTRY(92, -9, 93, -35, 127, -37, 127, -13, 104), +- CABAC_ENTRY(93, -3, 74, -2, 73, -5, 79, -3, 70), +- CABAC_ENTRY(94, -9, 92, -12, 104, -11, 104, -8, 93), +- CABAC_ENTRY(95, -8, 87, -9, 91, -11, 91, -10, 90), +- CABAC_ENTRY(96, -23, 126, -31, 127, -30, 127, -30, 127), +- CABAC_ENTRY(97, 5, 54, 3, 55, 0, 65, -1, 74), +- CABAC_ENTRY(98, 6, 60, 7, 56, -2, 79, -6, 97), +- CABAC_ENTRY(99, 6, 59, 7, 55, 0, 72, -7, 91), +- CABAC_ENTRY(100, 6, 69, 8, 61, -4, 92, -20, 127), +- CABAC_ENTRY(101, -1, 48, -3, 53, -6, 56, -4, 56), +- CABAC_ENTRY(102, 0, 68, 0, 68, 3, 68, -5, 82), +- CABAC_ENTRY(103, -4, 69, -7, 74, -8, 71, -7, 76), +- CABAC_ENTRY(104, -8, 88, -9, 88, -13, 98, -22, 125), +- +- /* Table 9-19 – Values of variables m and n for ctxIdx from 105 to 165 */ +- CABAC_ENTRY(105, -2, 85, -13, 103, -4, 86, -7, 93), +- CABAC_ENTRY(106, -6, 78, -13, 91, -12, 88, -11, 87), +- CABAC_ENTRY(107, -1, 75, -9, 89, -5, 82, -3, 77), +- CABAC_ENTRY(108, -7, 77, -14, 92, -3, 72, -5, 71), +- CABAC_ENTRY(109, 2, 54, -8, 76, -4, 67, -4, 63), +- CABAC_ENTRY(110, 5, 50, -12, 87, -8, 72, -4, 68), +- CABAC_ENTRY(111, -3, 68, -23, 110, -16, 89, -12, 84), +- CABAC_ENTRY(112, 1, 50, -24, 105, -9, 69, -7, 62), +- CABAC_ENTRY(113, 6, 42, -10, 78, -1, 59, -7, 65), +- CABAC_ENTRY(114, -4, 81, -20, 112, 5, 66, 8, 61), +- CABAC_ENTRY(115, 1, 63, -17, 99, 4, 57, 5, 56), +- CABAC_ENTRY(116, -4, 70, -78, 127, -4, 71, -2, 66), +- CABAC_ENTRY(117, 0, 67, -70, 127, -2, 71, 1, 64), +- CABAC_ENTRY(118, 2, 57, -50, 127, 2, 58, 0, 61), +- CABAC_ENTRY(119, -2, 76, -46, 127, -1, 74, -2, 78), +- CABAC_ENTRY(120, 11, 35, -4, 66, -4, 44, 1, 50), +- CABAC_ENTRY(121, 4, 64, -5, 78, -1, 69, 7, 52), +- CABAC_ENTRY(122, 1, 61, -4, 71, 0, 62, 10, 35), +- CABAC_ENTRY(123, 11, 35, -8, 72, -7, 51, 0, 44), +- CABAC_ENTRY(124, 18, 25, 2, 59, -4, 47, 11, 38), +- CABAC_ENTRY(125, 12, 24, -1, 55, -6, 42, 1, 45), +- CABAC_ENTRY(126, 13, 29, -7, 70, -3, 41, 0, 46), +- CABAC_ENTRY(127, 13, 36, -6, 75, -6, 53, 5, 44), +- CABAC_ENTRY(128, -10, 93, -8, 89, 8, 76, 31, 17), +- CABAC_ENTRY(129, -7, 73, -34, 119, -9, 78, 1, 51), +- CABAC_ENTRY(130, -2, 73, -3, 75, -11, 83, 7, 50), +- CABAC_ENTRY(131, 13, 46, 32, 20, 9, 52, 28, 19), +- CABAC_ENTRY(132, 9, 49, 30, 22, 0, 67, 16, 33), +- CABAC_ENTRY(133, -7, 100, -44, 127, -5, 90, 14, 62), +- CABAC_ENTRY(134, 9, 53, 0, 54, 1, 67, -13, 108), +- CABAC_ENTRY(135, 2, 53, -5, 61, -15, 72, -15, 100), +- CABAC_ENTRY(136, 5, 53, 0, 58, -5, 75, -13, 101), +- CABAC_ENTRY(137, -2, 61, -1, 60, -8, 80, -13, 91), +- CABAC_ENTRY(138, 0, 56, -3, 61, -21, 83, -12, 94), +- CABAC_ENTRY(139, 0, 56, -8, 67, -21, 64, -10, 88), +- CABAC_ENTRY(140, -13, 63, -25, 84, -13, 31, -16, 84), +- CABAC_ENTRY(141, -5, 60, -14, 74, -25, 64, -10, 86), +- CABAC_ENTRY(142, -1, 62, -5, 65, -29, 94, -7, 83), +- CABAC_ENTRY(143, 4, 57, 5, 52, 9, 75, -13, 87), +- CABAC_ENTRY(144, -6, 69, 2, 57, 17, 63, -19, 94), +- CABAC_ENTRY(145, 4, 57, 0, 61, -8, 74, 1, 70), +- CABAC_ENTRY(146, 14, 39, -9, 69, -5, 35, 0, 72), +- CABAC_ENTRY(147, 4, 51, -11, 70, -2, 27, -5, 74), +- CABAC_ENTRY(148, 13, 68, 18, 55, 13, 91, 18, 59), +- CABAC_ENTRY(149, 3, 64, -4, 71, 3, 65, -8, 102), +- CABAC_ENTRY(150, 1, 61, 0, 58, -7, 69, -15, 100), +- CABAC_ENTRY(151, 9, 63, 7, 61, 8, 77, 0, 95), +- CABAC_ENTRY(152, 7, 50, 9, 41, -10, 66, -4, 75), +- CABAC_ENTRY(153, 16, 39, 18, 25, 3, 62, 2, 72), +- CABAC_ENTRY(154, 5, 44, 9, 32, -3, 68, -11, 75), +- CABAC_ENTRY(155, 4, 52, 5, 43, -20, 81, -3, 71), +- CABAC_ENTRY(156, 11, 48, 9, 47, 0, 30, 15, 46), +- CABAC_ENTRY(157, -5, 60, 0, 44, 1, 7, -13, 69), +- CABAC_ENTRY(158, -1, 59, 0, 51, -3, 23, 0, 62), +- CABAC_ENTRY(159, 0, 59, 2, 46, -21, 74, 0, 65), +- CABAC_ENTRY(160, 22, 33, 19, 38, 16, 66, 21, 37), +- CABAC_ENTRY(161, 5, 44, -4, 66, -23, 124, -15, 72), +- CABAC_ENTRY(162, 14, 43, 15, 38, 17, 37, 9, 57), +- CABAC_ENTRY(163, -1, 78, 12, 42, 44, -18, 16, 54), +- CABAC_ENTRY(164, 0, 60, 9, 34, 50, -34, 0, 62), +- CABAC_ENTRY(165, 9, 69, 0, 89, -22, 127, 12, 72), +- +- /* Table 9-20 – Values of variables m and n for ctxIdx from 166 to 226 */ +- CABAC_ENTRY(166, 11, 28, 4, 45, 4, 39, 24, 0), +- CABAC_ENTRY(167, 2, 40, 10, 28, 0, 42, 15, 9), +- CABAC_ENTRY(168, 3, 44, 10, 31, 7, 34, 8, 25), +- CABAC_ENTRY(169, 0, 49, 33, -11, 11, 29, 13, 18), +- CABAC_ENTRY(170, 0, 46, 52, -43, 8, 31, 15, 9), +- CABAC_ENTRY(171, 2, 44, 18, 15, 6, 37, 13, 19), +- CABAC_ENTRY(172, 2, 51, 28, 0, 7, 42, 10, 37), +- CABAC_ENTRY(173, 0, 47, 35, -22, 3, 40, 12, 18), +- CABAC_ENTRY(174, 4, 39, 38, -25, 8, 33, 6, 29), +- CABAC_ENTRY(175, 2, 62, 34, 0, 13, 43, 20, 33), +- CABAC_ENTRY(176, 6, 46, 39, -18, 13, 36, 15, 30), +- CABAC_ENTRY(177, 0, 54, 32, -12, 4, 47, 4, 45), +- CABAC_ENTRY(178, 3, 54, 102, -94, 3, 55, 1, 58), +- CABAC_ENTRY(179, 2, 58, 0, 0, 2, 58, 0, 62), +- CABAC_ENTRY(180, 4, 63, 56, -15, 6, 60, 7, 61), +- CABAC_ENTRY(181, 6, 51, 33, -4, 8, 44, 12, 38), +- CABAC_ENTRY(182, 6, 57, 29, 10, 11, 44, 11, 45), +- CABAC_ENTRY(183, 7, 53, 37, -5, 14, 42, 15, 39), +- CABAC_ENTRY(184, 6, 52, 51, -29, 7, 48, 11, 42), +- CABAC_ENTRY(185, 6, 55, 39, -9, 4, 56, 13, 44), +- CABAC_ENTRY(186, 11, 45, 52, -34, 4, 52, 16, 45), +- CABAC_ENTRY(187, 14, 36, 69, -58, 13, 37, 12, 41), +- CABAC_ENTRY(188, 8, 53, 67, -63, 9, 49, 10, 49), +- CABAC_ENTRY(189, -1, 82, 44, -5, 19, 58, 30, 34), +- CABAC_ENTRY(190, 7, 55, 32, 7, 10, 48, 18, 42), +- CABAC_ENTRY(191, -3, 78, 55, -29, 12, 45, 10, 55), +- CABAC_ENTRY(192, 15, 46, 32, 1, 0, 69, 17, 51), +- CABAC_ENTRY(193, 22, 31, 0, 0, 20, 33, 17, 46), +- CABAC_ENTRY(194, -1, 84, 27, 36, 8, 63, 0, 89), +- CABAC_ENTRY(195, 25, 7, 33, -25, 35, -18, 26, -19), +- CABAC_ENTRY(196, 30, -7, 34, -30, 33, -25, 22, -17), +- CABAC_ENTRY(197, 28, 3, 36, -28, 28, -3, 26, -17), +- CABAC_ENTRY(198, 28, 4, 38, -28, 24, 10, 30, -25), +- CABAC_ENTRY(199, 32, 0, 38, -27, 27, 0, 28, -20), +- CABAC_ENTRY(200, 34, -1, 34, -18, 34, -14, 33, -23), +- CABAC_ENTRY(201, 30, 6, 35, -16, 52, -44, 37, -27), +- CABAC_ENTRY(202, 30, 6, 34, -14, 39, -24, 33, -23), +- CABAC_ENTRY(203, 32, 9, 32, -8, 19, 17, 40, -28), +- CABAC_ENTRY(204, 31, 19, 37, -6, 31, 25, 38, -17), +- CABAC_ENTRY(205, 26, 27, 35, 0, 36, 29, 33, -11), +- CABAC_ENTRY(206, 26, 30, 30, 10, 24, 33, 40, -15), +- CABAC_ENTRY(207, 37, 20, 28, 18, 34, 15, 41, -6), +- CABAC_ENTRY(208, 28, 34, 26, 25, 30, 20, 38, 1), +- CABAC_ENTRY(209, 17, 70, 29, 41, 22, 73, 41, 17), +- CABAC_ENTRY(210, 1, 67, 0, 75, 20, 34, 30, -6), +- CABAC_ENTRY(211, 5, 59, 2, 72, 19, 31, 27, 3), +- CABAC_ENTRY(212, 9, 67, 8, 77, 27, 44, 26, 22), +- CABAC_ENTRY(213, 16, 30, 14, 35, 19, 16, 37, -16), +- CABAC_ENTRY(214, 18, 32, 18, 31, 15, 36, 35, -4), +- CABAC_ENTRY(215, 18, 35, 17, 35, 15, 36, 38, -8), +- CABAC_ENTRY(216, 22, 29, 21, 30, 21, 28, 38, -3), +- CABAC_ENTRY(217, 24, 31, 17, 45, 25, 21, 37, 3), +- CABAC_ENTRY(218, 23, 38, 20, 42, 30, 20, 38, 5), +- CABAC_ENTRY(219, 18, 43, 18, 45, 31, 12, 42, 0), +- CABAC_ENTRY(220, 20, 41, 27, 26, 27, 16, 35, 16), +- CABAC_ENTRY(221, 11, 63, 16, 54, 24, 42, 39, 22), +- CABAC_ENTRY(222, 9, 59, 7, 66, 0, 93, 14, 48), +- CABAC_ENTRY(223, 9, 64, 16, 56, 14, 56, 27, 37), +- CABAC_ENTRY(224, -1, 94, 11, 73, 15, 57, 21, 60), +- CABAC_ENTRY(225, -2, 89, 10, 67, 26, 38, 12, 68), +- CABAC_ENTRY(226, -9, 108, -10, 116, -24, 127, 2, 97), +- +- /* Table 9-21 – Values of variables m and n for ctxIdx from 227 to 275 */ +- CABAC_ENTRY(227, -6, 76, -23, 112, -24, 115, -3, 71), +- CABAC_ENTRY(228, -2, 44, -15, 71, -22, 82, -6, 42), +- CABAC_ENTRY(229, 0, 45, -7, 61, -9, 62, -5, 50), +- CABAC_ENTRY(230, 0, 52, 0, 53, 0, 53, -3, 54), +- CABAC_ENTRY(231, -3, 64, -5, 66, 0, 59, -2, 62), +- CABAC_ENTRY(232, -2, 59, -11, 77, -14, 85, 0, 58), +- CABAC_ENTRY(233, -4, 70, -9, 80, -13, 89, 1, 63), +- CABAC_ENTRY(234, -4, 75, -9, 84, -13, 94, -2, 72), +- CABAC_ENTRY(235, -8, 82, -10, 87, -11, 92, -1, 74), +- CABAC_ENTRY(236, -17, 102, -34, 127, -29, 127, -9, 91), +- CABAC_ENTRY(237, -9, 77, -21, 101, -21, 100, -5, 67), +- CABAC_ENTRY(238, 3, 24, -3, 39, -14, 57, -5, 27), +- CABAC_ENTRY(239, 0, 42, -5, 53, -12, 67, -3, 39), +- CABAC_ENTRY(240, 0, 48, -7, 61, -11, 71, -2, 44), +- CABAC_ENTRY(241, 0, 55, -11, 75, -10, 77, 0, 46), +- CABAC_ENTRY(242, -6, 59, -15, 77, -21, 85, -16, 64), +- CABAC_ENTRY(243, -7, 71, -17, 91, -16, 88, -8, 68), +- CABAC_ENTRY(244, -12, 83, -25, 107, -23, 104, -10, 78), +- CABAC_ENTRY(245, -11, 87, -25, 111, -15, 98, -6, 77), +- CABAC_ENTRY(246, -30, 119, -28, 122, -37, 127, -10, 86), +- CABAC_ENTRY(247, 1, 58, -11, 76, -10, 82, -12, 92), +- CABAC_ENTRY(248, -3, 29, -10, 44, -8, 48, -15, 55), +- CABAC_ENTRY(249, -1, 36, -10, 52, -8, 61, -10, 60), +- CABAC_ENTRY(250, 1, 38, -10, 57, -8, 66, -6, 62), +- CABAC_ENTRY(251, 2, 43, -9, 58, -7, 70, -4, 65), +- CABAC_ENTRY(252, -6, 55, -16, 72, -14, 75, -12, 73), +- CABAC_ENTRY(253, 0, 58, -7, 69, -10, 79, -8, 76), +- CABAC_ENTRY(254, 0, 64, -4, 69, -9, 83, -7, 80), +- CABAC_ENTRY(255, -3, 74, -5, 74, -12, 92, -9, 88), +- CABAC_ENTRY(256, -10, 90, -9, 86, -18, 108, -17, 110), +- CABAC_ENTRY(257, 0, 70, 2, 66, -4, 79, -11, 97), +- CABAC_ENTRY(258, -4, 29, -9, 34, -22, 69, -20, 84), +- CABAC_ENTRY(259, 5, 31, 1, 32, -16, 75, -11, 79), +- CABAC_ENTRY(260, 7, 42, 11, 31, -2, 58, -6, 73), +- CABAC_ENTRY(261, 1, 59, 5, 52, 1, 58, -4, 74), +- CABAC_ENTRY(262, -2, 58, -2, 55, -13, 78, -13, 86), +- CABAC_ENTRY(263, -3, 72, -2, 67, -9, 83, -13, 96), +- CABAC_ENTRY(264, -3, 81, 0, 73, -4, 81, -11, 97), +- CABAC_ENTRY(265, -11, 97, -8, 89, -13, 99, -19, 117), +- CABAC_ENTRY(266, 0, 58, 3, 52, -13, 81, -8, 78), +- CABAC_ENTRY(267, 8, 5, 7, 4, -6, 38, -5, 33), +- CABAC_ENTRY(268, 10, 14, 10, 8, -13, 62, -4, 48), +- CABAC_ENTRY(269, 14, 18, 17, 8, -6, 58, -2, 53), +- CABAC_ENTRY(270, 13, 27, 16, 19, -2, 59, -3, 62), +- CABAC_ENTRY(271, 2, 40, 3, 37, -16, 73, -13, 71), +- CABAC_ENTRY(272, 0, 58, -1, 61, -10, 76, -10, 79), +- CABAC_ENTRY(273, -3, 70, -5, 73, -13, 86, -12, 86), +- CABAC_ENTRY(274, -6, 79, -1, 70, -9, 83, -13, 90), +- CABAC_ENTRY(275, -8, 85, -4, 78, -10, 87, -14, 97), +- +- /* Table 9-22 – Values of variables m and n for ctxIdx from 277 to 337 */ +- CABAC_ENTRY(277, -13, 106, -21, 126, -22, 127, -6, 93), +- CABAC_ENTRY(278, -16, 106, -23, 124, -25, 127, -6, 84), +- CABAC_ENTRY(279, -10, 87, -20, 110, -25, 120, -8, 79), +- CABAC_ENTRY(280, -21, 114, -26, 126, -27, 127, 0, 66), +- CABAC_ENTRY(281, -18, 110, -25, 124, -19, 114, -1, 71), +- CABAC_ENTRY(282, -14, 98, -17, 105, -23, 117, 0, 62), +- CABAC_ENTRY(283, -22, 110, -27, 121, -25, 118, -2, 60), +- CABAC_ENTRY(284, -21, 106, -27, 117, -26, 117, -2, 59), +- CABAC_ENTRY(285, -18, 103, -17, 102, -24, 113, -5, 75), +- CABAC_ENTRY(286, -21, 107, -26, 117, -28, 118, -3, 62), +- CABAC_ENTRY(287, -23, 108, -27, 116, -31, 120, -4, 58), +- CABAC_ENTRY(288, -26, 112, -33, 122, -37, 124, -9, 66), +- CABAC_ENTRY(289, -10, 96, -10, 95, -10, 94, -1, 79), +- CABAC_ENTRY(290, -12, 95, -14, 100, -15, 102, 0, 71), +- CABAC_ENTRY(291, -5, 91, -8, 95, -10, 99, 3, 68), +- CABAC_ENTRY(292, -9, 93, -17, 111, -13, 106, 10, 44), +- CABAC_ENTRY(293, -22, 94, -28, 114, -50, 127, -7, 62), +- CABAC_ENTRY(294, -5, 86, -6, 89, -5, 92, 15, 36), +- CABAC_ENTRY(295, 9, 67, -2, 80, 17, 57, 14, 40), +- CABAC_ENTRY(296, -4, 80, -4, 82, -5, 86, 16, 27), +- CABAC_ENTRY(297, -10, 85, -9, 85, -13, 94, 12, 29), +- CABAC_ENTRY(298, -1, 70, -8, 81, -12, 91, 1, 44), +- CABAC_ENTRY(299, 7, 60, -1, 72, -2, 77, 20, 36), +- CABAC_ENTRY(300, 9, 58, 5, 64, 0, 71, 18, 32), +- CABAC_ENTRY(301, 5, 61, 1, 67, -1, 73, 5, 42), +- CABAC_ENTRY(302, 12, 50, 9, 56, 4, 64, 1, 48), +- CABAC_ENTRY(303, 15, 50, 0, 69, -7, 81, 10, 62), +- CABAC_ENTRY(304, 18, 49, 1, 69, 5, 64, 17, 46), +- CABAC_ENTRY(305, 17, 54, 7, 69, 15, 57, 9, 64), +- CABAC_ENTRY(306, 10, 41, -7, 69, 1, 67, -12, 104), +- CABAC_ENTRY(307, 7, 46, -6, 67, 0, 68, -11, 97), +- CABAC_ENTRY(308, -1, 51, -16, 77, -10, 67, -16, 96), +- CABAC_ENTRY(309, 7, 49, -2, 64, 1, 68, -7, 88), +- CABAC_ENTRY(310, 8, 52, 2, 61, 0, 77, -8, 85), +- CABAC_ENTRY(311, 9, 41, -6, 67, 2, 64, -7, 85), +- CABAC_ENTRY(312, 6, 47, -3, 64, 0, 68, -9, 85), +- CABAC_ENTRY(313, 2, 55, 2, 57, -5, 78, -13, 88), +- CABAC_ENTRY(314, 13, 41, -3, 65, 7, 55, 4, 66), +- CABAC_ENTRY(315, 10, 44, -3, 66, 5, 59, -3, 77), +- CABAC_ENTRY(316, 6, 50, 0, 62, 2, 65, -3, 76), +- CABAC_ENTRY(317, 5, 53, 9, 51, 14, 54, -6, 76), +- CABAC_ENTRY(318, 13, 49, -1, 66, 15, 44, 10, 58), +- CABAC_ENTRY(319, 4, 63, -2, 71, 5, 60, -1, 76), +- CABAC_ENTRY(320, 6, 64, -2, 75, 2, 70, -1, 83), +- CABAC_ENTRY(321, -2, 69, -1, 70, -2, 76, -7, 99), +- CABAC_ENTRY(322, -2, 59, -9, 72, -18, 86, -14, 95), +- CABAC_ENTRY(323, 6, 70, 14, 60, 12, 70, 2, 95), +- CABAC_ENTRY(324, 10, 44, 16, 37, 5, 64, 0, 76), +- CABAC_ENTRY(325, 9, 31, 0, 47, -12, 70, -5, 74), +- CABAC_ENTRY(326, 12, 43, 18, 35, 11, 55, 0, 70), +- CABAC_ENTRY(327, 3, 53, 11, 37, 5, 56, -11, 75), +- CABAC_ENTRY(328, 14, 34, 12, 41, 0, 69, 1, 68), +- CABAC_ENTRY(329, 10, 38, 10, 41, 2, 65, 0, 65), +- CABAC_ENTRY(330, -3, 52, 2, 48, -6, 74, -14, 73), +- CABAC_ENTRY(331, 13, 40, 12, 41, 5, 54, 3, 62), +- CABAC_ENTRY(332, 17, 32, 13, 41, 7, 54, 4, 62), +- CABAC_ENTRY(333, 7, 44, 0, 59, -6, 76, -1, 68), +- CABAC_ENTRY(334, 7, 38, 3, 50, -11, 82, -13, 75), +- CABAC_ENTRY(335, 13, 50, 19, 40, -2, 77, 11, 55), +- CABAC_ENTRY(336, 10, 57, 3, 66, -2, 77, 5, 64), +- CABAC_ENTRY(337, 26, 43, 18, 50, 25, 42, 12, 70), +- +- /* Table 9-23 – Values of variables m and n for ctxIdx from 338 to 398 */ +- CABAC_ENTRY(338, 14, 11, 19, -6, 17, -13, 15, 6), +- CABAC_ENTRY(339, 11, 14, 18, -6, 16, -9, 6, 19), +- CABAC_ENTRY(340, 9, 11, 14, 0, 17, -12, 7, 16), +- CABAC_ENTRY(341, 18, 11, 26, -12, 27, -21, 12, 14), +- CABAC_ENTRY(342, 21, 9, 31, -16, 37, -30, 18, 13), +- CABAC_ENTRY(343, 23, -2, 33, -25, 41, -40, 13, 11), +- CABAC_ENTRY(344, 32, -15, 33, -22, 42, -41, 13, 15), +- CABAC_ENTRY(345, 32, -15, 37, -28, 48, -47, 15, 16), +- CABAC_ENTRY(346, 34, -21, 39, -30, 39, -32, 12, 23), +- CABAC_ENTRY(347, 39, -23, 42, -30, 46, -40, 13, 23), +- CABAC_ENTRY(348, 42, -33, 47, -42, 52, -51, 15, 20), +- CABAC_ENTRY(349, 41, -31, 45, -36, 46, -41, 14, 26), +- CABAC_ENTRY(350, 46, -28, 49, -34, 52, -39, 14, 44), +- CABAC_ENTRY(351, 38, -12, 41, -17, 43, -19, 17, 40), +- CABAC_ENTRY(352, 21, 29, 32, 9, 32, 11, 17, 47), +- CABAC_ENTRY(353, 45, -24, 69, -71, 61, -55, 24, 17), +- CABAC_ENTRY(354, 53, -45, 63, -63, 56, -46, 21, 21), +- CABAC_ENTRY(355, 48, -26, 66, -64, 62, -50, 25, 22), +- CABAC_ENTRY(356, 65, -43, 77, -74, 81, -67, 31, 27), +- CABAC_ENTRY(357, 43, -19, 54, -39, 45, -20, 22, 29), +- CABAC_ENTRY(358, 39, -10, 52, -35, 35, -2, 19, 35), +- CABAC_ENTRY(359, 30, 9, 41, -10, 28, 15, 14, 50), +- CABAC_ENTRY(360, 18, 26, 36, 0, 34, 1, 10, 57), +- CABAC_ENTRY(361, 20, 27, 40, -1, 39, 1, 7, 63), +- CABAC_ENTRY(362, 0, 57, 30, 14, 30, 17, -2, 77), +- CABAC_ENTRY(363, -14, 82, 28, 26, 20, 38, -4, 82), +- CABAC_ENTRY(364, -5, 75, 23, 37, 18, 45, -3, 94), +- CABAC_ENTRY(365, -19, 97, 12, 55, 15, 54, 9, 69), +- CABAC_ENTRY(366, -35, 125, 11, 65, 0, 79, -12, 109), +- CABAC_ENTRY(367, 27, 0, 37, -33, 36, -16, 36, -35), +- CABAC_ENTRY(368, 28, 0, 39, -36, 37, -14, 36, -34), +- CABAC_ENTRY(369, 31, -4, 40, -37, 37, -17, 32, -26), +- CABAC_ENTRY(370, 27, 6, 38, -30, 32, 1, 37, -30), +- CABAC_ENTRY(371, 34, 8, 46, -33, 34, 15, 44, -32), +- CABAC_ENTRY(372, 30, 10, 42, -30, 29, 15, 34, -18), +- CABAC_ENTRY(373, 24, 22, 40, -24, 24, 25, 34, -15), +- CABAC_ENTRY(374, 33, 19, 49, -29, 34, 22, 40, -15), +- CABAC_ENTRY(375, 22, 32, 38, -12, 31, 16, 33, -7), +- CABAC_ENTRY(376, 26, 31, 40, -10, 35, 18, 35, -5), +- CABAC_ENTRY(377, 21, 41, 38, -3, 31, 28, 33, 0), +- CABAC_ENTRY(378, 26, 44, 46, -5, 33, 41, 38, 2), +- CABAC_ENTRY(379, 23, 47, 31, 20, 36, 28, 33, 13), +- CABAC_ENTRY(380, 16, 65, 29, 30, 27, 47, 23, 35), +- CABAC_ENTRY(381, 14, 71, 25, 44, 21, 62, 13, 58), +- CABAC_ENTRY(382, 8, 60, 12, 48, 18, 31, 29, -3), +- CABAC_ENTRY(383, 6, 63, 11, 49, 19, 26, 26, 0), +- CABAC_ENTRY(384, 17, 65, 26, 45, 36, 24, 22, 30), +- CABAC_ENTRY(385, 21, 24, 22, 22, 24, 23, 31, -7), +- CABAC_ENTRY(386, 23, 20, 23, 22, 27, 16, 35, -15), +- CABAC_ENTRY(387, 26, 23, 27, 21, 24, 30, 34, -3), +- CABAC_ENTRY(388, 27, 32, 33, 20, 31, 29, 34, 3), +- CABAC_ENTRY(389, 28, 23, 26, 28, 22, 41, 36, -1), +- CABAC_ENTRY(390, 28, 24, 30, 24, 22, 42, 34, 5), +- CABAC_ENTRY(391, 23, 40, 27, 34, 16, 60, 32, 11), +- CABAC_ENTRY(392, 24, 32, 18, 42, 15, 52, 35, 5), +- CABAC_ENTRY(393, 28, 29, 25, 39, 14, 60, 34, 12), +- CABAC_ENTRY(394, 23, 42, 18, 50, 3, 78, 39, 11), +- CABAC_ENTRY(395, 19, 57, 12, 70, -16, 123, 30, 29), +- CABAC_ENTRY(396, 22, 53, 21, 54, 21, 53, 34, 26), +- CABAC_ENTRY(397, 22, 61, 14, 71, 22, 56, 29, 39), +- CABAC_ENTRY(398, 11, 86, 11, 83, 25, 61, 19, 66), +- +- /* Values of variables m and n for ctxIdx from 399 to 463 (not documented) */ +- CABAC_ENTRY(399, 12, 40, 25, 32, 21, 33, 31, 21), +- CABAC_ENTRY(400, 11, 51, 21, 49, 19, 50, 31, 31), +- CABAC_ENTRY(401, 14, 59, 21, 54, 17, 61, 25, 50), +- CABAC_ENTRY(402, -4, 79, -5, 85, -3, 78, -17, 120), +- CABAC_ENTRY(403, -7, 71, -6, 81, -8, 74, -20, 112), +- CABAC_ENTRY(404, -5, 69, -10, 77, -9, 72, -18, 114), +- CABAC_ENTRY(405, -9, 70, -7, 81, -10, 72, -11, 85), +- CABAC_ENTRY(406, -8, 66, -17, 80, -18, 75, -15, 92), +- CABAC_ENTRY(407, -10, 68, -18, 73, -12, 71, -14, 89), +- CABAC_ENTRY(408, -19, 73, -4, 74, -11, 63, -26, 71), +- CABAC_ENTRY(409, -12, 69, -10, 83, -5, 70, -15, 81), +- CABAC_ENTRY(410, -16, 70, -9, 71, -17, 75, -14, 80), +- CABAC_ENTRY(411, -15, 67, -9, 67, -14, 72, 0, 68), +- CABAC_ENTRY(412, -20, 62, -1, 61, -16, 67, -14, 70), +- CABAC_ENTRY(413, -19, 70, -8, 66, -8, 53, -24, 56), +- CABAC_ENTRY(414, -16, 66, -14, 66, -14, 59, -23, 68), +- CABAC_ENTRY(415, -22, 65, 0, 59, -9, 52, -24, 50), +- CABAC_ENTRY(416, -20, 63, 2, 59, -11, 68, -11, 74), +- CABAC_ENTRY(417, 9, -2, 17, -10, 9, -2, 23, -13), +- CABAC_ENTRY(418, 26, -9, 32, -13, 30, -10, 26, -13), +- CABAC_ENTRY(419, 33, -9, 42, -9, 31, -4, 40, -15), +- CABAC_ENTRY(420, 39, -7, 49, -5, 33, -1, 49, -14), +- CABAC_ENTRY(421, 41, -2, 53, 0, 33, 7, 44, 3), +- CABAC_ENTRY(422, 45, 3, 64, 3, 31, 12, 45, 6), +- CABAC_ENTRY(423, 49, 9, 68, 10, 37, 23, 44, 34), +- CABAC_ENTRY(424, 45, 27, 66, 27, 31, 38, 33, 54), +- CABAC_ENTRY(425, 36, 59, 47, 57, 20, 64, 19, 82), +- CABAC_ENTRY(426, -6, 66, -5, 71, -9, 71, -3, 75), +- CABAC_ENTRY(427, -7, 35, 0, 24, -7, 37, -1, 23), +- CABAC_ENTRY(428, -7, 42, -1, 36, -8, 44, 1, 34), +- CABAC_ENTRY(429, -8, 45, -2, 42, -11, 49, 1, 43), +- CABAC_ENTRY(430, -5, 48, -2, 52, -10, 56, 0, 54), +- CABAC_ENTRY(431, -12, 56, -9, 57, -12, 59, -2, 55), +- CABAC_ENTRY(432, -6, 60, -6, 63, -8, 63, 0, 61), +- CABAC_ENTRY(433, -5, 62, -4, 65, -9, 67, 1, 64), +- CABAC_ENTRY(434, -8, 66, -4, 67, -6, 68, 0, 68), +- CABAC_ENTRY(435, -8, 76, -7, 82, -10, 79, -9, 92), +- CABAC_ENTRY(436, -5, 85, -3, 81, -3, 78, -14, 106), +- CABAC_ENTRY(437, -6, 81, -3, 76, -8, 74, -13, 97), +- CABAC_ENTRY(438, -10, 77, -7, 72, -9, 72, -15, 90), +- CABAC_ENTRY(439, -7, 81, -6, 78, -10, 72, -12, 90), +- CABAC_ENTRY(440, -17, 80, -12, 72, -18, 75, -18, 88), +- CABAC_ENTRY(441, -18, 73, -14, 68, -12, 71, -10, 73), +- CABAC_ENTRY(442, -4, 74, -3, 70, -11, 63, -9, 79), +- CABAC_ENTRY(443, -10, 83, -6, 76, -5, 70, -14, 86), +- CABAC_ENTRY(444, -9, 71, -5, 66, -17, 75, -10, 73), +- CABAC_ENTRY(445, -9, 67, -5, 62, -14, 72, -10, 70), +- CABAC_ENTRY(446, -1, 61, 0, 57, -16, 67, -10, 69), +- CABAC_ENTRY(447, -8, 66, -4, 61, -8, 53, -5, 66), +- CABAC_ENTRY(448, -14, 66, -9, 60, -14, 59, -9, 64), +- CABAC_ENTRY(449, 0, 59, 1, 54, -9, 52, -5, 58), +- CABAC_ENTRY(450, 2, 59, 2, 58, -11, 68, 2, 59), +- CABAC_ENTRY(451, 21, -13, 17, -10, 9, -2, 21, -10), +- CABAC_ENTRY(452, 33, -14, 32, -13, 30, -10, 24, -11), +- CABAC_ENTRY(453, 39, -7, 42, -9, 31, -4, 28, -8), +- CABAC_ENTRY(454, 46, -2, 49, -5, 33, -1, 28, -1), +- CABAC_ENTRY(455, 51, 2, 53, 0, 33, 7, 29, 3), +- CABAC_ENTRY(456, 60, 6, 64, 3, 31, 12, 29, 9), +- CABAC_ENTRY(457, 61, 17, 68, 10, 37, 23, 35, 20), +- CABAC_ENTRY(458, 55, 34, 66, 27, 31, 38, 29, 36), +- CABAC_ENTRY(459, 42, 62, 47, 57, 20, 64, 14, 67), +-}; +- + static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) + { + u8 bit = field.offset % 32, word = field.offset / 32; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Thu, 20 Jun 2024 10:19:44 -0400 +Subject: media: rockchip: Introduce the rkvdec2 driver + +This driver supports the second generation of the Rockchip Video +decoder, also known as vdpu34x. +It is currently only used on the RK3588(s) SoC. + +There are 2 decoders on the RK3588 SoC that can work in pair to decode +8K video at 30 FPS but currently, only using one core at a time is +supported. + +Scheduling requests between the two cores will be implemented later. + +The core supports H264, HEVC, VP9 and AVS2 decoding but this driver +currently only supports H264. + +The driver is based on rkvdec and they may share some code in the +future. +The decision to make a different driver is mainly because rkvdec2 has +more features and can work with multiple cores. + +The registers are mapped in a struct in RAM using bitfields. It is IO +copied to the HW when all values are configured. +The decision to use such a struct instead of writing buffers one by one +is based on the following reasons: + - Rockchip cores are known to misbehave when registers are not written + in address order, + - Those cores also need the software to write all registers, even if + they are written their default values or are not related to the task + (this core will not start decoding some H264 frames if some VP9 + registers are not written to 0) + - In the future, to support multiple cores, the scheduler could be + optimized by storing the precomputed registers values and copy them + to the HW as soos as a core becomes available. + +This makes the code more readable and may bring performance improvements +in future features. + +Signed-off-by: Detlev Casanova +--- + drivers/staging/media/Kconfig | 1 + + drivers/staging/media/Makefile | 1 + + drivers/staging/media/rkvdec2/Kconfig | 15 + + drivers/staging/media/rkvdec2/Makefile | 3 + + drivers/staging/media/rkvdec2/TODO | 9 + + drivers/staging/media/rkvdec2/rkvdec2-h264.c | 739 ++++++ + drivers/staging/media/rkvdec2/rkvdec2-regs.h | 345 +++ + drivers/staging/media/rkvdec2/rkvdec2.c | 1253 ++++++++++ + drivers/staging/media/rkvdec2/rkvdec2.h | 130 + + 9 files changed, 2496 insertions(+) + +diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig +index 111111111111..222222222222 100644 +--- a/drivers/staging/media/Kconfig ++++ b/drivers/staging/media/Kconfig +@@ -35,6 +35,7 @@ source "drivers/staging/media/meson/vdec/Kconfig" + source "drivers/staging/media/omap4iss/Kconfig" + + source "drivers/staging/media/rkvdec/Kconfig" ++source "drivers/staging/media/rkvdec2/Kconfig" + + source "drivers/staging/media/starfive/Kconfig" + +diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/staging/media/Makefile ++++ b/drivers/staging/media/Makefile +@@ -6,6 +6,7 @@ obj-$(CONFIG_VIDEO_MAX96712) += max96712/ + obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/ + obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/ + obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rkvdec/ ++obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC2) += rkvdec2/ + obj-$(CONFIG_VIDEO_STARFIVE_CAMSS) += starfive/ + obj-$(CONFIG_VIDEO_SUNXI) += sunxi/ + obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/ +diff --git a/drivers/staging/media/rkvdec2/Kconfig b/drivers/staging/media/rkvdec2/Kconfig +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/staging/media/rkvdec2/Kconfig +@@ -0,0 +1,15 @@ ++# SPDX-License-Identifier: GPL-2.0 ++config VIDEO_ROCKCHIP_VDEC2 ++ tristate "Rockchip Video Decoder driver 2" ++ depends on ARCH_ROCKCHIP || COMPILE_TEST ++ depends on VIDEO_DEV ++ select MEDIA_CONTROLLER ++ select VIDEOBUF2_DMA_CONTIG ++ select VIDEOBUF2_VMALLOC ++ select V4L2_MEM2MEM_DEV ++ select V4L2_H264 ++ help ++ Support for the Rockchip Video Decoder 2 IP present on Rockchip SoCs, ++ which accelerates video decoding. ++ To compile this driver as a module, choose M here: the module ++ will be called rockchip-vdec2. +diff --git a/drivers/staging/media/rkvdec2/Makefile b/drivers/staging/media/rkvdec2/Makefile +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/staging/media/rkvdec2/Makefile +@@ -0,0 +1,3 @@ ++obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC2) += rockchip-vdec2.o ++ ++rockchip-vdec2-y += rkvdec2.o rkvdec2-h264.o +diff --git a/drivers/staging/media/rkvdec2/TODO b/drivers/staging/media/rkvdec2/TODO +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/staging/media/rkvdec2/TODO +@@ -0,0 +1,9 @@ ++* Support for 4:2:2 and 10 bits ++* Support for rockchip IOMMU ++* Support for HEVC and VP9 are planned for this driver. ++ ++ First, the h264 backend needs to be stabilized. ++ ++* Evaluate sharing code with rkvdec ++ ++ As rkvdec is still in staging, this driver stays there as well. +diff --git a/drivers/staging/media/rkvdec2/rkvdec2-h264.c b/drivers/staging/media/rkvdec2/rkvdec2-h264.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/staging/media/rkvdec2/rkvdec2-h264.c +@@ -0,0 +1,739 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Rockchip Video Decoder 2 H264 backend ++ * ++ * Copyright (C) 2024 Collabora, Ltd. ++ * Detlev Casanova ++ * ++ * Based on rkvdec driver by Boris Brezillon ++ */ ++ ++#include ++#include ++ ++#include "rkvdec2.h" ++#include "rkvdec2-regs.h" ++/* This header will move to a rockchip/common folder when de-staging */ ++#include "../rkvdec/rkvdec-h264-cabac.h" ++ ++#define RKVDEC_NUM_REFLIST 3 ++ ++struct rkvdec2_h264_scaling_list { ++ u8 scaling_list_4x4[6][16]; ++ u8 scaling_list_8x8[6][64]; ++ u8 padding[128]; ++}; ++ ++struct rkvdec2_sps { ++ u16 seq_parameter_set_id: 4; ++ u16 profile_idc: 8; ++ u16 constraint_set3_flag: 1; ++ u16 chroma_format_idc: 2; ++ u16 bit_depth_luma: 3; ++ u16 bit_depth_chroma: 3; ++ u16 qpprime_y_zero_transform_bypass_flag: 1; ++ u16 log2_max_frame_num_minus4: 4; ++ u16 max_num_ref_frames: 5; ++ u16 pic_order_cnt_type: 2; ++ u16 log2_max_pic_order_cnt_lsb_minus4: 4; ++ u16 delta_pic_order_always_zero_flag: 1; ++ u16 pic_width_in_mbs: 12; ++ u16 pic_height_in_mbs: 12; ++ u16 frame_mbs_only_flag: 1; ++ u16 mb_adaptive_frame_field_flag: 1; ++ u16 direct_8x8_inference_flag: 1; ++ u16 mvc_extension_enable: 1; ++ u16 num_views: 2; ++ ++ u16 reserved_bits: 12; ++ u16 reserved[11]; ++} __packed; ++ ++struct rkvdec2_pps { ++ u16 pic_parameter_set_id: 8; ++ u16 pps_seq_parameter_set_id: 5; ++ u16 entropy_coding_mode_flag: 1; ++ u16 bottom_field_pic_order_in_frame_present_flag: 1; ++ u16 num_ref_idx_l0_default_active_minus1: 5; ++ u16 num_ref_idx_l1_default_active_minus1: 5; ++ u16 weighted_pred_flag: 1; ++ u16 weighted_bipred_idc: 2; ++ u16 pic_init_qp_minus26: 7; ++ u16 pic_init_qs_minus26: 6; ++ u16 chroma_qp_index_offset: 5; ++ u16 deblocking_filter_control_present_flag: 1; ++ u16 constrained_intra_pred_flag: 1; ++ u16 redundant_pic_cnt_present: 1; ++ u16 transform_8x8_mode_flag: 1; ++ u16 second_chroma_qp_index_offset: 5; ++ u16 scaling_list_enable_flag: 1; ++ u32 scaling_list_address; ++ u16 is_longterm; ++ ++ u8 reserved[3]; ++} __packed; ++ ++struct rkvdec2_rps_entry { ++ u32 dpb_info0: 5; ++ u32 bottom_flag0: 1; ++ u32 view_index_off0: 1; ++ u32 dpb_info1: 5; ++ u32 bottom_flag1: 1; ++ u32 view_index_off1: 1; ++ u32 dpb_info2: 5; ++ u32 bottom_flag2: 1; ++ u32 view_index_off2: 1; ++ u32 dpb_info3: 5; ++ u32 bottom_flag3: 1; ++ u32 view_index_off3: 1; ++ u32 dpb_info4: 5; ++ u32 bottom_flag4: 1; ++ u32 view_index_off4: 1; ++ u32 dpb_info5: 5; ++ u32 bottom_flag5: 1; ++ u32 view_index_off5: 1; ++ u32 dpb_info6: 5; ++ u32 bottom_flag6: 1; ++ u32 view_index_off6: 1; ++ u32 dpb_info7: 5; ++ u32 bottom_flag7: 1; ++ u32 view_index_off7: 1; ++} __packed; ++ ++struct rkvdec2_rps { ++ u16 frame_num[16]; ++ u32 reserved0; ++ struct rkvdec2_rps_entry entries[12]; ++ u32 reserved1[66]; ++} __packed; ++ ++struct rkvdec2_sps_pps { ++ struct rkvdec2_sps sps; ++ struct rkvdec2_pps pps; ++} __packed; ++ ++/* Data structure describing auxiliary buffer format. */ ++struct rkvdec2_h264_priv_tbl { ++ u32 cabac_table[928]; ++ struct rkvdec2_h264_scaling_list scaling_list; ++ struct rkvdec2_sps_pps param_set[256]; ++ struct rkvdec2_rps rps; ++}; ++ ++struct rkvdec2_h264_reflists { ++ struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; ++ struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN]; ++ struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN]; ++}; ++ ++struct rkvdec2_h264_run { ++ struct rkvdec2_run base; ++ const struct v4l2_ctrl_h264_decode_params *decode_params; ++ const struct v4l2_ctrl_h264_sps *sps; ++ const struct v4l2_ctrl_h264_pps *pps; ++ const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; ++ struct vb2_buffer *ref_buf[V4L2_H264_NUM_DPB_ENTRIES]; ++}; ++ ++struct rkvdec2_h264_ctx { ++ struct rkvdec2_aux_buf priv_tbl; ++ struct rkvdec2_h264_reflists reflists; ++ struct rkvdec2_regs_h264 regs; ++}; ++ ++static void assemble_hw_pps(struct rkvdec2_ctx *ctx, ++ struct rkvdec2_h264_run *run) ++{ ++ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; ++ const struct v4l2_ctrl_h264_sps *sps = run->sps; ++ const struct v4l2_ctrl_h264_pps *pps = run->pps; ++ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; ++ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; ++ struct rkvdec2_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; ++ struct rkvdec2_sps_pps *hw_ps; ++ dma_addr_t scaling_list_address; ++ u32 scaling_distance; ++ u32 i; ++ ++ /* ++ * HW read the SPS/PPS information from PPS packet index by PPS id. ++ * offset from the base can be calculated by PPS_id * 32 (size per PPS ++ * packet unit). so the driver copy SPS/PPS information to the exact PPS ++ * packet unit for HW accessing. ++ */ ++ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; ++ memset(hw_ps, 0, sizeof(*hw_ps)); ++ ++ /* write sps */ ++ hw_ps->sps.seq_parameter_set_id = 0xf; ++ hw_ps->sps.profile_idc = 0xff; ++ hw_ps->sps.constraint_set3_flag = 1; ++ hw_ps->sps.chroma_format_idc = sps->chroma_format_idc; ++ hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8; ++ hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8; ++ hw_ps->sps.qpprime_y_zero_transform_bypass_flag = 0; ++ hw_ps->sps.log2_max_frame_num_minus4 = sps->log2_max_frame_num_minus4; ++ hw_ps->sps.max_num_ref_frames = sps->max_num_ref_frames; ++ hw_ps->sps.pic_order_cnt_type = sps->pic_order_cnt_type; ++ hw_ps->sps.log2_max_pic_order_cnt_lsb_minus4 = ++ sps->log2_max_pic_order_cnt_lsb_minus4; ++ hw_ps->sps.delta_pic_order_always_zero_flag = ++ !!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); ++ hw_ps->sps.mvc_extension_enable = 1; ++ hw_ps->sps.num_views = 1; ++ ++ /* ++ * Use the SPS values since they are already in macroblocks ++ * dimensions, height can be field height (halved) if ++ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY is not set and also it allows ++ * decoding smaller images into larger allocation which can be used ++ * to implementing SVC spatial layer support. ++ */ ++ hw_ps->sps.pic_width_in_mbs = sps->pic_width_in_mbs_minus1 + 1; ++ hw_ps->sps.pic_height_in_mbs = sps->pic_height_in_map_units_minus1 + 1; ++ hw_ps->sps.frame_mbs_only_flag = ++ !!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); ++ hw_ps->sps.mb_adaptive_frame_field_flag = ++ !!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); ++ hw_ps->sps.direct_8x8_inference_flag = ++ !!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); ++ ++ /* write pps */ ++ hw_ps->pps.pic_parameter_set_id = 0xff; ++ hw_ps->pps.pps_seq_parameter_set_id = 0x1f; ++ hw_ps->pps.entropy_coding_mode_flag = ++ !!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); ++ hw_ps->pps.bottom_field_pic_order_in_frame_present_flag = ++ !!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); ++ hw_ps->pps.num_ref_idx_l0_default_active_minus1 = ++ pps->num_ref_idx_l0_default_active_minus1; ++ hw_ps->pps.num_ref_idx_l1_default_active_minus1 = ++ pps->num_ref_idx_l1_default_active_minus1; ++ hw_ps->pps.weighted_pred_flag = ++ !!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED); ++ hw_ps->pps.weighted_bipred_idc = pps->weighted_bipred_idc; ++ hw_ps->pps.pic_init_qp_minus26 = pps->pic_init_qp_minus26; ++ hw_ps->pps.pic_init_qs_minus26 = pps->pic_init_qs_minus26; ++ hw_ps->pps.chroma_qp_index_offset = pps->chroma_qp_index_offset; ++ hw_ps->pps.deblocking_filter_control_present_flag = ++ !!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); ++ hw_ps->pps.constrained_intra_pred_flag = ++ !!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); ++ hw_ps->pps.redundant_pic_cnt_present = ++ !!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); ++ hw_ps->pps.transform_8x8_mode_flag = ++ !!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); ++ hw_ps->pps.second_chroma_qp_index_offset = pps->second_chroma_qp_index_offset; ++ hw_ps->pps.scaling_list_enable_flag = ++ !!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); ++ ++ /* ++ * To be on the safe side, program the scaling matrix address ++ * ++ * With this set here, ++ * RKVDEC_SWREG12_SENCODARY_EN:sw_scanlist_addr_valid_en ++ * can stay at 0 ++ */ ++ scaling_distance = offsetof(struct rkvdec2_h264_priv_tbl, scaling_list); ++ scaling_list_address = h264_ctx->priv_tbl.dma + scaling_distance; ++ hw_ps->pps.scaling_list_address = scaling_list_address; ++ ++ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { ++ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) ++ hw_ps->pps.is_longterm |= (1 << i); ++ } ++} ++ ++static void lookup_ref_buf_idx(struct rkvdec2_ctx *ctx, ++ struct rkvdec2_h264_run *run) ++{ ++ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; ++ u32 i; ++ ++ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { ++ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; ++ const struct v4l2_h264_dpb_entry *dpb = run->decode_params->dpb; ++ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; ++ struct vb2_buffer *buf = NULL; ++ ++ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) { ++ buf = vb2_find_buffer(cap_q, dpb[i].reference_ts); ++ if (!buf) { ++ dev_dbg(ctx->dev->dev, "No buffer for reference_ts %llu", ++ dpb[i].reference_ts); ++ } ++ } ++ ++ run->ref_buf[i] = buf; ++ } ++} ++ ++static void set_dpb_info(struct rkvdec2_rps_entry *entries, ++ u8 reflist, ++ u8 refnum, ++ u8 info, ++ bool bottom) ++{ ++ struct rkvdec2_rps_entry *entry = &entries[(reflist * 4) + refnum / 8]; ++ u8 idx = refnum % 8; ++ ++ switch (idx) { ++ case 0: ++ entry->dpb_info0 = info; ++ entry->bottom_flag0 = bottom; ++ break; ++ case 1: ++ entry->dpb_info1 = info; ++ entry->bottom_flag1 = bottom; ++ break; ++ case 2: ++ entry->dpb_info2 = info; ++ entry->bottom_flag2 = bottom; ++ break; ++ case 3: ++ entry->dpb_info3 = info; ++ entry->bottom_flag3 = bottom; ++ break; ++ case 4: ++ entry->dpb_info4 = info; ++ entry->bottom_flag4 = bottom; ++ break; ++ case 5: ++ entry->dpb_info5 = info; ++ entry->bottom_flag5 = bottom; ++ break; ++ case 6: ++ entry->dpb_info6 = info; ++ entry->bottom_flag6 = bottom; ++ break; ++ case 7: ++ entry->dpb_info7 = info; ++ entry->bottom_flag7 = bottom; ++ break; ++ } ++} ++ ++static void assemble_hw_rps(struct rkvdec2_ctx *ctx, ++ struct v4l2_h264_reflist_builder *builder, ++ struct rkvdec2_h264_run *run) ++{ ++ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; ++ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; ++ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; ++ struct rkvdec2_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; ++ ++ struct rkvdec2_rps *hw_rps = &priv_tbl->rps; ++ u32 i, j; ++ ++ memset(hw_rps, 0, sizeof(priv_tbl->rps)); ++ ++ /* ++ * Assign an invalid pic_num if DPB entry at that position is inactive. ++ * If we assign 0 in that position hardware will treat that as a real ++ * reference picture with pic_num 0, triggering output picture ++ * corruption. ++ */ ++ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { ++ if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) ++ continue; ++ ++ hw_rps->frame_num[i] = builder->refs[i].frame_num; ++ } ++ ++ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { ++ for (i = 0; i < builder->num_valid; i++) { ++ struct v4l2_h264_reference *ref; ++ bool dpb_valid; ++ bool bottom; ++ ++ switch (j) { ++ case 0: ++ ref = &h264_ctx->reflists.p[i]; ++ break; ++ case 1: ++ ref = &h264_ctx->reflists.b0[i]; ++ break; ++ case 2: ++ ref = &h264_ctx->reflists.b1[i]; ++ break; ++ } ++ ++ if (WARN_ON(ref->index >= ARRAY_SIZE(dec_params->dpb))) ++ continue; ++ ++ dpb_valid = !!(run->ref_buf[ref->index]); ++ bottom = ref->fields == V4L2_H264_BOTTOM_FIELD_REF; ++ ++ set_dpb_info(hw_rps->entries, j, i, ref->index | (dpb_valid << 4), bottom); ++ } ++ } ++} ++ ++static void assemble_hw_scaling_list(struct rkvdec2_ctx *ctx, ++ struct rkvdec2_h264_run *run) ++{ ++ const struct v4l2_ctrl_h264_scaling_matrix *scaling = run->scaling_matrix; ++ const struct v4l2_ctrl_h264_pps *pps = run->pps; ++ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; ++ struct rkvdec2_h264_priv_tbl *tbl = h264_ctx->priv_tbl.cpu; ++ ++ if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT)) ++ return; ++ ++ BUILD_BUG_ON(sizeof(tbl->scaling_list.scaling_list_4x4) != ++ sizeof(scaling->scaling_list_4x4)); ++ BUILD_BUG_ON(sizeof(tbl->scaling_list.scaling_list_8x8) != ++ sizeof(scaling->scaling_list_8x8)); ++ ++ memcpy(tbl->scaling_list.scaling_list_4x4, ++ scaling->scaling_list_4x4, ++ sizeof(scaling->scaling_list_4x4)); ++ ++ memcpy(tbl->scaling_list.scaling_list_8x8, ++ scaling->scaling_list_8x8, ++ sizeof(scaling->scaling_list_8x8)); ++} ++ ++static inline void rkvdec2_memcpy_toio(void __iomem *dst, void *src, size_t len) ++{ ++#ifdef CONFIG_ARM64 ++ __iowrite32_copy(dst, src, len); ++#elif defined(CONFIG_ARM) ++ memcpy_toio(dst, src, len); ++#endif ++} ++ ++static void rkvdec2_write_regs(struct rkvdec2_ctx *ctx) ++{ ++ struct rkvdec2_dev *rkvdec = ctx->dev; ++ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; ++ ++ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_COMMON_REGS, ++ &h264_ctx->regs.common, ++ sizeof(h264_ctx->regs.common)); ++ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_CODEC_PARAMS_REGS, ++ &h264_ctx->regs.h264_param, ++ sizeof(h264_ctx->regs.h264_param)); ++ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_COMMON_ADDR_REGS, ++ &h264_ctx->regs.common_addr, ++ sizeof(h264_ctx->regs.common_addr)); ++ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_CODEC_ADDR_REGS, ++ &h264_ctx->regs.h264_addr, ++ sizeof(h264_ctx->regs.h264_addr)); ++ rkvdec2_memcpy_toio(rkvdec->regs + OFFSET_POC_HIGHBIT_REGS, ++ &h264_ctx->regs.h264_highpoc, ++ sizeof(h264_ctx->regs.h264_highpoc)); ++} ++ ++static void config_registers(struct rkvdec2_ctx *ctx, ++ struct rkvdec2_h264_run *run) ++{ ++ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; ++ const struct v4l2_ctrl_h264_sps *sps = run->sps; ++ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; ++ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; ++ dma_addr_t priv_start_addr = h264_ctx->priv_tbl.dma; ++ const struct v4l2_pix_format_mplane *dst_fmt; ++ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; ++ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; ++ struct rkvdec2_regs_h264 *regs = &h264_ctx->regs; ++ const struct v4l2_format *f; ++ dma_addr_t rlc_addr; ++ dma_addr_t dst_addr; ++ u32 hor_virstride = 0; ++ u32 ver_virstride = 0; ++ u32 y_virstride = 0; ++ u32 offset; ++ u32 pixels; ++ u32 i; ++ ++ memset(regs, 0, sizeof(*regs)); ++ ++ /* Set H264 mode */ ++ regs->common.reg009.dec_mode = RKVDEC2_MODE_H264; ++ ++ /* Set config */ ++ regs->common.reg011.buf_empty_en = 1; ++ regs->common.reg011.dec_clkgate_e = 1; ++ regs->common.reg011.dec_timeout_e = 1; ++ regs->common.reg011.pix_range_detection_e = 1; ++ ++ /* Set IDR flag */ ++ regs->common.reg013.cur_pic_is_idr = ++ !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC); ++ ++ /* Set input stream length */ ++ regs->common.stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); ++ ++ /* Set max slice number */ ++ regs->common.reg017.slice_num = MAX_SLICE_NUMBER; ++ ++ /* Set strides */ ++ f = &ctx->decoded_fmt; ++ dst_fmt = &f->fmt.pix_mp; ++ hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8; ++ ver_virstride = round_up(dst_fmt->height, 16); ++ y_virstride = hor_virstride * ver_virstride; ++ pixels = dst_fmt->height * dst_fmt->width; ++ ++ regs->common.reg018.y_hor_virstride = hor_virstride / 16; ++ regs->common.reg019.uv_hor_virstride = hor_virstride / 16; ++ regs->common.reg020.y_virstride = y_virstride / 16; ++ ++ /* Activate block gating */ ++ regs->common.reg026.swreg_block_gating_e = 0xfffef; ++ regs->common.reg026.reg_cfg_gating_en = 1; ++ ++ /* Set timeout threshold */ ++ if (pixels < RKVDEC2_1080P_PIXELS) ++ regs->common.timeout_threshold = RKVDEC2_TIMEOUT_1080p; ++ else if (pixels < RKVDEC2_4K_PIXELS) ++ regs->common.timeout_threshold = RKVDEC2_TIMEOUT_4K; ++ else if (pixels < RKVDEC2_8K_PIXELS) ++ regs->common.timeout_threshold = RKVDEC2_TIMEOUT_8K; ++ ++ /* Set TOP and BOTTOM POCs */ ++ regs->h264_param.cur_top_poc = dec_params->top_field_order_cnt; ++ regs->h264_param.cur_bot_poc = dec_params->bottom_field_order_cnt; ++ ++ /* Set ref pic address & poc */ ++ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { ++ struct vb2_buffer *vb_buf = run->ref_buf[i]; ++ dma_addr_t buf_dma; ++ ++ /* ++ * If a DPB entry is unused or invalid, address of current destination ++ * buffer is returned. ++ */ ++ if (!vb_buf) ++ vb_buf = &dst_buf->vb2_buf; ++ ++ buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0); ++ ++ /* Set reference addresses */ ++ regs->h264_addr.ref_base[i] = buf_dma; ++ ++ /* Set COLMV addresses */ ++ regs->h264_addr.colmv_base[i] = buf_dma + ctx->colmv_offset; ++ ++ struct rkvdec2_h264_ref_info *ref_info = ++ ®s->h264_param.ref_info_regs[i / 4].ref_info[i % 4]; ++ ++ ref_info->ref_field = ++ !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD); ++ ref_info->ref_colmv_use_flag = ++ !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE); ++ ref_info->ref_topfield_used = ++ !!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF); ++ ref_info->ref_botfield_used = ++ !!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF); ++ ++ regs->h264_param.ref_pocs[i * 2] = ++ dpb[i].top_field_order_cnt; ++ regs->h264_param.ref_pocs[i * 2 + 1] = ++ dpb[i].bottom_field_order_cnt; ++ } ++ ++ /* Set rlc base address (input stream) */ ++ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); ++ regs->common_addr.rlc_base = rlc_addr; ++ regs->common_addr.rlcwrite_base = rlc_addr; ++ ++ /* Set output base address */ ++ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); ++ regs->common_addr.decout_base = dst_addr; ++ ++ /* Set colmv address */ ++ regs->common_addr.colmv_cur_base = dst_addr + ctx->colmv_offset; ++ ++ /* Set RCB addresses */ ++ for (i = 0; i < RKVDEC2_RCB_COUNT; i++) ++ regs->common_addr.rcb_base[i] = ctx->rcb_bufs[i].dma; ++ ++ /* Set hw pps address */ ++ offset = offsetof(struct rkvdec2_h264_priv_tbl, param_set); ++ regs->h264_addr.pps_base = priv_start_addr + offset; ++ ++ /* Set hw rps address */ ++ offset = offsetof(struct rkvdec2_h264_priv_tbl, rps); ++ regs->h264_addr.rps_base = priv_start_addr + offset; ++ ++ /* Set cabac table */ ++ offset = offsetof(struct rkvdec2_h264_priv_tbl, cabac_table); ++ regs->h264_addr.cabactbl_base = priv_start_addr + offset; ++ ++ rkvdec2_write_regs(ctx); ++} ++ ++#define RKVDEC_H264_MAX_DEPTH_IN_BYTES 2 ++ ++static int rkvdec2_h264_adjust_fmt(struct rkvdec2_ctx *ctx, ++ struct v4l2_format *f) ++{ ++ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; ++ ++ fmt->num_planes = 1; ++ if (!fmt->plane_fmt[0].sizeimage) ++ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * ++ RKVDEC_H264_MAX_DEPTH_IN_BYTES; ++ return 0; ++} ++ ++static int rkvdec2_h264_validate_sps(struct rkvdec2_ctx *ctx, ++ const struct v4l2_ctrl_h264_sps *sps) ++{ ++ unsigned int width, height; ++ ++ /* ++ * TODO: The hardware supports 10-bit and 4:2:2 profiles, ++ * but it's currently broken in the driver. ++ * Reject them for now, until it's fixed. ++ */ ++ if (sps->chroma_format_idc > 1) ++ /* Only 4:0:0 and 4:2:0 are supported */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) ++ /* Luma and chroma bit depth mismatch */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != 0) ++ /* Only 8-bit is supported */ ++ return -EINVAL; ++ ++ width = (sps->pic_width_in_mbs_minus1 + 1) * 16; ++ height = (sps->pic_height_in_map_units_minus1 + 1) * 16; ++ ++ /* ++ * When frame_mbs_only_flag is not set, this is field height, ++ * which is half the final height (see (7-8) in the ++ * specification) ++ */ ++ if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) ++ height *= 2; ++ ++ if (width > ctx->coded_fmt.fmt.pix_mp.width || ++ height > ctx->coded_fmt.fmt.pix_mp.height) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int rkvdec2_h264_start(struct rkvdec2_ctx *ctx) ++{ ++ struct rkvdec2_dev *rkvdec = ctx->dev; ++ struct rkvdec2_h264_priv_tbl *priv_tbl; ++ struct rkvdec2_h264_ctx *h264_ctx; ++ struct v4l2_ctrl *ctrl; ++ int ret; ++ ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_H264_SPS); ++ if (!ctrl) ++ return -EINVAL; ++ ++ ret = rkvdec2_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); ++ if (ret) ++ return ret; ++ ++ h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL); ++ if (!h264_ctx) ++ return -ENOMEM; ++ ++ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), ++ &h264_ctx->priv_tbl.dma, GFP_KERNEL); ++ if (!priv_tbl) { ++ ret = -ENOMEM; ++ goto err_free_ctx; ++ } ++ ++ h264_ctx->priv_tbl.size = sizeof(*priv_tbl); ++ h264_ctx->priv_tbl.cpu = priv_tbl; ++ memcpy(priv_tbl->cabac_table, rkvdec_h264_cabac_table, ++ sizeof(rkvdec_h264_cabac_table)); ++ ++ ctx->priv = h264_ctx; ++ return 0; ++ ++err_free_ctx: ++ kfree(h264_ctx); ++ return ret; ++} ++ ++static void rkvdec2_h264_stop(struct rkvdec2_ctx *ctx) ++{ ++ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; ++ struct rkvdec2_dev *rkvdec = ctx->dev; ++ ++ dma_free_coherent(rkvdec->dev, h264_ctx->priv_tbl.size, ++ h264_ctx->priv_tbl.cpu, h264_ctx->priv_tbl.dma); ++ kfree(h264_ctx); ++} ++ ++static void rkvdec2_h264_run_preamble(struct rkvdec2_ctx *ctx, ++ struct rkvdec2_h264_run *run) ++{ ++ struct v4l2_ctrl *ctrl; ++ ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_H264_DECODE_PARAMS); ++ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_H264_SPS); ++ run->sps = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_H264_PPS); ++ run->pps = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_H264_SCALING_MATRIX); ++ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; ++ ++ rkvdec2_run_preamble(ctx, &run->base); ++} ++ ++static int rkvdec2_h264_run(struct rkvdec2_ctx *ctx) ++{ ++ struct v4l2_h264_reflist_builder reflist_builder; ++ struct rkvdec2_dev *rkvdec = ctx->dev; ++ struct rkvdec2_h264_ctx *h264_ctx = ctx->priv; ++ struct rkvdec2_h264_run run; ++ ++ rkvdec2_h264_run_preamble(ctx, &run); ++ ++ /* Build the P/B{0,1} ref lists. */ ++ v4l2_h264_init_reflist_builder(&reflist_builder, run.decode_params, ++ run.sps, run.decode_params->dpb); ++ v4l2_h264_build_p_ref_list(&reflist_builder, h264_ctx->reflists.p); ++ v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0, ++ h264_ctx->reflists.b1); ++ ++ assemble_hw_scaling_list(ctx, &run); ++ assemble_hw_pps(ctx, &run); ++ lookup_ref_buf_idx(ctx, &run); ++ assemble_hw_rps(ctx, &reflist_builder, &run); ++ ++ config_registers(ctx, &run); ++ ++ rkvdec2_run_postamble(ctx, &run.base); ++ ++ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); ++ ++ /* Start decoding! */ ++ writel(RKVDEC2_REG_DEC_E_BIT, rkvdec->regs + RKVDEC2_REG_DEC_E); ++ ++ return 0; ++} ++ ++static int rkvdec2_h264_try_ctrl(struct rkvdec2_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) ++ return rkvdec2_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); ++ ++ return 0; ++} ++ ++const struct rkvdec2_coded_fmt_ops rkvdec2_h264_fmt_ops = { ++ .adjust_fmt = rkvdec2_h264_adjust_fmt, ++ .start = rkvdec2_h264_start, ++ .stop = rkvdec2_h264_stop, ++ .run = rkvdec2_h264_run, ++ .try_ctrl = rkvdec2_h264_try_ctrl, ++}; +diff --git a/drivers/staging/media/rkvdec2/rkvdec2-regs.h b/drivers/staging/media/rkvdec2/rkvdec2-regs.h +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/staging/media/rkvdec2/rkvdec2-regs.h +@@ -0,0 +1,345 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Rockchip Video Decoder 2 driver registers description ++ * ++ * Copyright (C) 2024 Collabora, Ltd. ++ * Detlev Casanova ++ */ ++ ++#ifndef _RKVDEC_REGS_H_ ++#define _RKVDEC_REGS_H_ ++ ++#define OFFSET_COMMON_REGS (8 * sizeof(u32)) ++#define OFFSET_CODEC_PARAMS_REGS (64 * sizeof(u32)) ++#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(u32)) ++#define OFFSET_CODEC_ADDR_REGS (160 * sizeof(u32)) ++#define OFFSET_POC_HIGHBIT_REGS (200 * sizeof(u32)) ++ ++#define RKVDEC2_MODE_HEVC 0 ++#define RKVDEC2_MODE_H264 1 ++#define RKVDEC2_MODE_VP9 2 ++#define RKVDEC2_MODE_AVS2 3 ++ ++#define MAX_SLICE_NUMBER 0x3fff ++ ++#define RKVDEC2_1080P_PIXELS (1920 * 1080) ++#define RKVDEC2_4K_PIXELS (4096 * 2304) ++#define RKVDEC2_8K_PIXELS (7680 * 4320) ++#define RKVDEC2_TIMEOUT_1080p (0xefffff) ++#define RKVDEC2_TIMEOUT_4K (0x2cfffff) ++#define RKVDEC2_TIMEOUT_8K (0x4ffffff) ++ ++#define RKVDEC2_REG_DEC_E 0x028 ++#define RKVDEC2_REG_DEC_E_BIT 1 ++ ++#define RKVDEC2_REG_IMPORTANT_EN 0x02c ++#define RKVDEC2_REG_DEC_IRQ_DISABLE BIT(4) ++ ++#define RKVDEC2_REG_STA_INT 0x380 ++#define STA_INT_DEC_RDY_STA BIT(2) ++ ++/* base: OFFSET_COMMON_REGS */ ++struct rkvdec2_regs_common { ++ struct rkvdec2_in_out { ++ u32 in_endian : 1; ++ u32 in_swap32_e : 1; ++ u32 in_swap64_e : 1; ++ u32 str_endian : 1; ++ u32 str_swap32_e : 1; ++ u32 str_swap64_e : 1; ++ u32 out_endian : 1; ++ u32 out_swap32_e : 1; ++ u32 out_cbcr_swap : 1; ++ u32 out_swap64_e : 1; ++ u32 reserved : 22; ++ } reg008; ++ ++ struct rkvdec2_dec_mode { ++ u32 dec_mode : 10; ++ u32 reserved : 22; ++ } reg009; ++ ++ struct rkvdec2_dec_e { ++ u32 dec_e : 1; ++ u32 reserved : 31; ++ } reg010; ++ ++ struct rkvdec2_important_en { ++ u32 reserved : 1; ++ u32 dec_clkgate_e : 1; ++ u32 dec_e_strmd_clkgate_dis : 1; ++ u32 reserved0 : 1; ++ ++ u32 dec_irq_dis : 1; ++ u32 dec_timeout_e : 1; ++ u32 buf_empty_en : 1; ++ u32 reserved1 : 3; ++ ++ u32 dec_e_rewrite_valid : 1; ++ u32 reserved2 : 9; ++ u32 softrst_en_p : 1; ++ u32 force_softreset_valid : 1; ++ u32 reserved3 : 2; ++ u32 pix_range_detection_e : 1; ++ u32 reserved4 : 7; ++ } reg011; ++ ++ struct rkvdec2_sencodary_en { ++ u32 wr_ddr_align_en : 1; ++ u32 colmv_compress_en : 1; ++ u32 fbc_e : 1; ++ u32 reserved0 : 1; ++ ++ u32 buspr_slot_disable : 1; ++ u32 error_info_en : 1; ++ u32 info_collect_en : 1; ++ u32 wait_reset_en : 1; ++ ++ u32 scanlist_addr_valid_en : 1; ++ u32 scale_down_en : 1; ++ u32 error_cfg_wr_disable : 1; ++ u32 reserved1 : 21; ++ } reg012; ++ ++ struct rkvdec2_en_mode_set { ++ u32 timeout_mode : 1; ++ u32 req_timeout_rst_sel : 1; ++ u32 reserved0 : 1; ++ u32 dec_commonirq_mode : 1; ++ u32 reserved1 : 2; ++ u32 stmerror_waitdecfifo_empty : 1; ++ u32 reserved2 : 2; ++ u32 h26x_streamd_error_mode : 1; ++ u32 reserved3 : 2; ++ u32 allow_not_wr_unref_bframe : 1; ++ u32 fbc_output_wr_disable : 1; ++ u32 reserved4 : 1; ++ u32 colmv_error_mode : 1; ++ ++ u32 reserved5 : 2; ++ u32 h26x_error_mode : 1; ++ u32 reserved6 : 2; ++ u32 ycacherd_prior : 1; ++ u32 reserved7 : 2; ++ u32 cur_pic_is_idr : 1; ++ u32 reserved8 : 1; ++ u32 right_auto_rst_disable : 1; ++ u32 frame_end_err_rst_flag : 1; ++ u32 rd_prior_mode : 1; ++ u32 rd_ctrl_prior_mode : 1; ++ u32 reserved9 : 1; ++ u32 filter_outbuf_mode : 1; ++ } reg013; ++ ++ struct rkvdec2_fbc_param_set { ++ u32 fbc_force_uncompress : 1; ++ ++ u32 reserved0 : 2; ++ u32 allow_16x8_cp_flag : 1; ++ u32 reserved1 : 2; ++ ++ u32 fbc_h264_exten_4or8_flag : 1; ++ u32 reserved2 : 25; ++ } reg014; ++ ++ struct rkvdec2_stream_param_set { ++ u32 rlc_mode_direct_write : 1; ++ u32 rlc_mode : 1; ++ u32 reserved0 : 3; ++ ++ u32 strm_start_bit : 7; ++ u32 reserved1 : 20; ++ } reg015; ++ ++ u32 stream_len; ++ ++ struct rkvdec2_slice_number { ++ u32 slice_num : 25; ++ u32 reserved : 7; ++ } reg017; ++ ++ struct rkvdec2_y_hor_stride { ++ u32 y_hor_virstride : 16; ++ u32 reserved : 16; ++ } reg018; ++ ++ struct rkvdec2_uv_hor_stride { ++ u32 uv_hor_virstride : 16; ++ u32 reserved : 16; ++ } reg019; ++ ++ struct rkvdec2_y_stride { ++ u32 y_virstride : 28; ++ u32 reserved : 4; ++ } reg020; ++ ++ struct rkvdec2_error_ctrl_set { ++ u32 inter_error_prc_mode : 1; ++ u32 error_intra_mode : 1; ++ u32 error_deb_en : 1; ++ u32 picidx_replace : 5; ++ u32 error_spread_e : 1; ++ u32 reserved0 : 3; ++ u32 error_inter_pred_cross_slice : 1; ++ u32 reserved1 : 11; ++ u32 roi_error_ctu_cal_en : 1; ++ u32 reserved2 : 7; ++ } reg021; ++ ++ struct rkvdec2_err_roi_ctu_offset_start { ++ u32 roi_x_ctu_offset_st : 12; ++ u32 reserved0 : 4; ++ u32 roi_y_ctu_offset_st : 12; ++ u32 reserved1 : 4; ++ } reg022; ++ ++ struct rkvdec2_err_roi_ctu_offset_end { ++ u32 roi_x_ctu_offset_end : 12; ++ u32 reserved0 : 4; ++ u32 roi_y_ctu_offset_end : 12; ++ u32 reserved1 : 4; ++ } reg023; ++ ++ struct rkvdec2_cabac_error_en_lowbits { ++ u32 cabac_err_en_lowbits : 32; ++ } reg024; ++ ++ struct rkvdec2_cabac_error_en_highbits { ++ u32 cabac_err_en_highbits : 30; ++ u32 reserved : 2; ++ } reg025; ++ ++ struct rkvdec2_block_gating_en { ++ u32 swreg_block_gating_e : 20; ++ u32 reserved : 11; ++ u32 reg_cfg_gating_en : 1; ++ } reg026; ++ ++ struct SW027_CORE_SAFE_PIXELS { ++ u32 core_safe_x_pixels : 16; ++ u32 core_safe_y_pixels : 16; ++ } reg027; ++ ++ struct rkvdec2_multiply_core_ctrl { ++ u32 swreg_vp9_wr_prob_idx : 3; ++ u32 reserved0 : 1; ++ u32 swreg_vp9_rd_prob_idx : 3; ++ u32 reserved1 : 1; ++ ++ u32 swreg_ref_req_advance_flag : 1; ++ u32 sw_colmv_req_advance_flag : 1; ++ u32 sw_poc_only_highbit_flag : 1; ++ u32 sw_poc_arb_flag : 1; ++ ++ u32 reserved2 : 4; ++ u32 sw_film_idx : 10; ++ u32 reserved3 : 2; ++ u32 sw_pu_req_mismatch_dis : 1; ++ u32 sw_colmv_req_mismatch_dis : 1; ++ u32 reserved4 : 2; ++ } reg028; ++ ++ struct SW029_SCALE_DOWN_CTRL { ++ u32 scale_down_hor_ratio : 2; ++ u32 reserved0 : 6; ++ u32 scale_down_vrz_ratio : 2; ++ u32 reserved1 : 22; ++ } reg029; ++ ++ struct SW032_Y_SCALE_DOWN_TILE8x8_HOR_STRIDE { ++ u32 y_scale_down_hor_stride : 20; ++ u32 reserved0 : 12; ++ } reg030; ++ ++ struct SW031_UV_SCALE_DOWN_TILE8x8_HOR_STRIDE { ++ u32 uv_scale_down_hor_stride : 20; ++ u32 reserved0 : 12; ++ } reg031; ++ ++ u32 timeout_threshold; ++} __packed; ++ ++/* base: OFFSET_COMMON_ADDR_REGS */ ++struct rkvdec2_regs_common_addr { ++ u32 rlc_base; ++ u32 rlcwrite_base; ++ u32 decout_base; ++ u32 colmv_cur_base; ++ u32 error_ref_base; ++ u32 rcb_base[10]; ++} __packed; ++ ++/* base: OFFSET_CODEC_PARAMS_REGS */ ++struct rkvdec2_regs_h264_params { ++ struct rkvdec2_h26x_set { ++ u32 h26x_frame_orslice : 1; ++ u32 h26x_rps_mode : 1; ++ u32 h26x_stream_mode : 1; ++ u32 h26x_stream_lastpacket : 1; ++ u32 h264_firstslice_flag : 1; ++ u32 reserved : 27; ++ } reg064; ++ ++ u32 cur_top_poc; ++ u32 cur_bot_poc; ++ u32 ref_pocs[32]; ++ ++ struct rkvdec2_h264_info { ++ struct rkvdec2_h264_ref_info { ++ u32 ref_field : 1; ++ u32 ref_topfield_used : 1; ++ u32 ref_botfield_used : 1; ++ u32 ref_colmv_use_flag : 1; ++ u32 ref_reserved : 4; ++ } __packed ref_info[4]; ++ } __packed ref_info_regs[4]; ++ ++ u32 reserved_103_111[9]; ++ ++ struct rkvdec2_error_ref_info { ++ u32 avs2_ref_error_field : 1; ++ u32 avs2_ref_error_topfield : 1; ++ u32 ref_error_topfield_used : 1; ++ u32 ref_error_botfield_used : 1; ++ u32 reserved : 28; ++ } reg112; ++} __packed; ++ ++/* base: OFFSET_CODEC_ADDR_REGS */ ++struct rkvdec2_regs_h264_addr { ++ u32 reserved_160; ++ u32 pps_base; ++ u32 reserved_162; ++ u32 rps_base; ++ u32 ref_base[16]; ++ u32 scanlist_addr; ++ u32 colmv_base[16]; ++ u32 cabactbl_base; ++} __packed; ++ ++struct rkvdec2_regs_h264_highpoc { ++ struct rkvdec2_ref_poc_highbit { ++ u32 ref0_poc_highbit : 4; ++ u32 ref1_poc_highbit : 4; ++ u32 ref2_poc_highbit : 4; ++ u32 ref3_poc_highbit : 4; ++ u32 ref4_poc_highbit : 4; ++ u32 ref5_poc_highbit : 4; ++ u32 ref6_poc_highbit : 4; ++ u32 ref7_poc_highbit : 4; ++ } reg200[4]; ++ struct rkvdec2_cur_poc_highbit { ++ u32 cur_poc_highbit : 4; ++ u32 reserved : 28; ++ } reg204; ++} __packed; ++ ++struct rkvdec2_regs_h264 { ++ struct rkvdec2_regs_common common; ++ struct rkvdec2_regs_h264_params h264_param; ++ struct rkvdec2_regs_common_addr common_addr; ++ struct rkvdec2_regs_h264_addr h264_addr; ++ struct rkvdec2_regs_h264_highpoc h264_highpoc; ++} __packed; ++ ++#endif /* __RKVDEC_REGS_H__ */ +diff --git a/drivers/staging/media/rkvdec2/rkvdec2.c b/drivers/staging/media/rkvdec2/rkvdec2.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/staging/media/rkvdec2/rkvdec2.c +@@ -0,0 +1,1253 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Rockchip Video Decoder 2 driver ++ * ++ * Copyright (C) 2024 Collabora, Ltd. ++ * Detlev Casanova ++ * ++ * Based on rkvdec driver by Boris Brezillon ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "rkvdec2.h" ++ ++static int rkvdec2_try_ctrl(struct v4l2_ctrl *ctrl) ++{ ++ struct rkvdec2_ctx *ctx = container_of(ctrl->handler, struct rkvdec2_ctx, ctrl_hdl); ++ const struct rkvdec2_coded_fmt_desc *desc = ctx->coded_fmt_desc; ++ ++ if (desc->ops->try_ctrl) ++ return desc->ops->try_ctrl(ctx, ctrl); ++ ++ return 0; ++} ++ ++static const struct v4l2_ctrl_ops rkvdec2_ctrl_ops = { ++ .try_ctrl = rkvdec2_try_ctrl, ++}; ++ ++static const struct rkvdec2_ctrl_desc rkvdec2_h264_ctrl_descs[] = { ++ { ++ .cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_H264_SPS, ++ .cfg.ops = &rkvdec2_ctrl_ops, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_H264_PPS, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_H264_SCALING_MATRIX, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_H264_DECODE_MODE, ++ .cfg.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, ++ .cfg.max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, ++ .cfg.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_H264_START_CODE, ++ .cfg.min = V4L2_STATELESS_H264_START_CODE_ANNEX_B, ++ .cfg.def = V4L2_STATELESS_H264_START_CODE_ANNEX_B, ++ .cfg.max = V4L2_STATELESS_H264_START_CODE_ANNEX_B, ++ }, ++ { ++ .cfg.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, ++ .cfg.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, ++ .cfg.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, ++ .cfg.menu_skip_mask = ++ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED), ++ .cfg.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, ++ }, ++ { ++ .cfg.id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, ++ .cfg.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, ++ .cfg.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_1, ++ }, ++}; ++ ++static const struct rkvdec2_ctrls rkvdec2_h264_ctrls = { ++ .ctrls = rkvdec2_h264_ctrl_descs, ++ .num_ctrls = ARRAY_SIZE(rkvdec2_h264_ctrl_descs), ++}; ++ ++static const u32 rkvdec2_h264_decoded_fmts[] = { ++ V4L2_PIX_FMT_NV12 ++}; ++ ++static const struct rkvdec2_coded_fmt_desc rkvdec2_coded_fmts[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_H264_SLICE, ++ .frmsize = { ++ .min_width = 16, ++ .max_width = 65520, ++ .step_width = 16, ++ .min_height = 16, ++ .max_height = 65520, ++ .step_height = 16, ++ }, ++ .ctrls = &rkvdec2_h264_ctrls, ++ .ops = &rkvdec2_h264_fmt_ops, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec2_h264_decoded_fmts), ++ .decoded_fmts = rkvdec2_h264_decoded_fmts, ++ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, ++ }, ++}; ++ ++enum rcb_axis { ++ PIC_WIDTH = 0, ++ PIC_HEIGHT = 1 ++}; ++ ++struct rcb_size_info { ++ u8 multiplier; ++ enum rcb_axis axis; ++}; ++ ++static struct rcb_size_info rcb_sizes[] = { ++ {6, PIC_WIDTH}, // intrar ++ {1, PIC_WIDTH}, // transdr (Is actually 0.4*pic_width) ++ {1, PIC_HEIGHT}, // transdc (Is actually 0.1*pic_height) ++ {3, PIC_WIDTH}, // streamdr ++ {6, PIC_WIDTH}, // interr ++ {3, PIC_HEIGHT}, // interc ++ {22, PIC_WIDTH}, // dblkr ++ {6, PIC_WIDTH}, // saor ++ {11, PIC_WIDTH}, // fbcr ++ {67, PIC_HEIGHT}, // filtc col ++}; ++ ++#define RCB_SIZE(n) (rcb_sizes[(n)].multiplier * (rcb_sizes[(n)].axis ? height : width)) ++ ++static const struct rkvdec2_coded_fmt_desc * ++rkvdec2_find_coded_fmt_desc(u32 fourcc) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(rkvdec2_coded_fmts); i++) { ++ if (rkvdec2_coded_fmts[i].fourcc == fourcc) ++ return &rkvdec2_coded_fmts[i]; ++ } ++ ++ return NULL; ++} ++ ++static void rkvdec2_reset_fmt(struct rkvdec2_ctx *ctx, struct v4l2_format *f, ++ u32 fourcc) ++{ ++ memset(f, 0, sizeof(*f)); ++ f->fmt.pix_mp.pixelformat = fourcc; ++ f->fmt.pix_mp.field = V4L2_FIELD_NONE; ++ f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709; ++ f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; ++ f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; ++ f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; ++} ++ ++static void rkvdec2_reset_coded_fmt(struct rkvdec2_ctx *ctx) ++{ ++ struct v4l2_format *f = &ctx->coded_fmt; ++ ++ ctx->coded_fmt_desc = &rkvdec2_coded_fmts[0]; ++ rkvdec2_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); ++ ++ f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; ++ f->fmt.pix_mp.width = ctx->coded_fmt_desc->frmsize.min_width; ++ f->fmt.pix_mp.height = ctx->coded_fmt_desc->frmsize.min_height; ++ ++ if (ctx->coded_fmt_desc->ops->adjust_fmt) ++ ctx->coded_fmt_desc->ops->adjust_fmt(ctx, f); ++} ++ ++static void rkvdec2_reset_decoded_fmt(struct rkvdec2_ctx *ctx) ++{ ++ struct v4l2_format *f = &ctx->decoded_fmt; ++ ++ rkvdec2_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); ++ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; ++ v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, ++ ctx->coded_fmt_desc->decoded_fmts[0], ++ ctx->coded_fmt.fmt.pix_mp.width, ++ ctx->coded_fmt.fmt.pix_mp.height); ++ ++ ctx->colmv_offset = f->fmt.pix_mp.plane_fmt[0].sizeimage; ++ ++ f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 * ++ DIV_ROUND_UP(f->fmt.pix_mp.width, 16) * ++ DIV_ROUND_UP(f->fmt.pix_mp.height, 16); ++} ++ ++static int rkvdec2_enum_framesizes(struct file *file, void *priv, ++ struct v4l2_frmsizeenum *fsize) ++{ ++ const struct rkvdec2_coded_fmt_desc *fmt; ++ ++ if (fsize->index != 0) ++ return -EINVAL; ++ ++ fmt = rkvdec2_find_coded_fmt_desc(fsize->pixel_format); ++ if (!fmt) ++ return -EINVAL; ++ ++ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; ++ fsize->stepwise = fmt->frmsize; ++ return 0; ++} ++ ++static int rkvdec2_querycap(struct file *file, void *priv, ++ struct v4l2_capability *cap) ++{ ++ struct rkvdec2_dev *rkvdec = video_drvdata(file); ++ struct video_device *vdev = video_devdata(file); ++ ++ strscpy(cap->driver, rkvdec->dev->driver->name, ++ sizeof(cap->driver)); ++ strscpy(cap->card, vdev->name, sizeof(cap->card)); ++ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", ++ rkvdec->dev->driver->name); ++ return 0; ++} ++ ++static int rkvdec2_try_capture_fmt(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; ++ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); ++ const struct rkvdec2_coded_fmt_desc *coded_desc; ++ unsigned int i; ++ ++ /* ++ * The codec context should point to a coded format desc, if the format ++ * on the coded end has not been set yet, it should point to the ++ * default value. ++ */ ++ coded_desc = ctx->coded_fmt_desc; ++ if (WARN_ON(!coded_desc)) ++ return -EINVAL; ++ ++ for (i = 0; i < coded_desc->num_decoded_fmts; i++) { ++ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) ++ break; ++ } ++ ++ if (i == coded_desc->num_decoded_fmts) ++ pix_mp->pixelformat = coded_desc->decoded_fmts[0]; ++ ++ /* Always apply the frmsize constraint of the coded end. */ ++ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); ++ pix_mp->height = max(pix_mp->height, ctx->coded_fmt.fmt.pix_mp.height); ++ v4l2_apply_frmsize_constraints(&pix_mp->width, ++ &pix_mp->height, ++ &coded_desc->frmsize); ++ ++ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, ++ pix_mp->width, pix_mp->height); ++ ++ pix_mp->plane_fmt[0].sizeimage += ++ 128 * ++ DIV_ROUND_UP(pix_mp->width, 16) * ++ DIV_ROUND_UP(pix_mp->height, 16); ++ ++ pix_mp->field = V4L2_FIELD_NONE; ++ ++ return 0; ++} ++ ++static int rkvdec2_try_output_fmt(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; ++ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); ++ const struct rkvdec2_coded_fmt_desc *desc; ++ ++ desc = rkvdec2_find_coded_fmt_desc(pix_mp->pixelformat); ++ if (!desc) { ++ pix_mp->pixelformat = rkvdec2_coded_fmts[0].fourcc; ++ desc = &rkvdec2_coded_fmts[0]; ++ } ++ ++ v4l2_apply_frmsize_constraints(&pix_mp->width, ++ &pix_mp->height, ++ &desc->frmsize); ++ ++ pix_mp->field = V4L2_FIELD_NONE; ++ /* All coded formats are considered single planar for now. */ ++ pix_mp->num_planes = 1; ++ ++ if (desc->ops->adjust_fmt) { ++ int ret; ++ ++ ret = desc->ops->adjust_fmt(ctx, f); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rkvdec2_s_capture_fmt(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); ++ struct vb2_queue *vq; ++ int ret; ++ ++ /* Change not allowed if queue is busy */ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, ++ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ ret = rkvdec2_try_capture_fmt(file, priv, f); ++ if (ret) ++ return ret; ++ ++ ctx->decoded_fmt = *f; ++ return 0; ++} ++ ++static int rkvdec2_s_output_fmt(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); ++ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; ++ const struct rkvdec2_coded_fmt_desc *desc; ++ struct v4l2_format *cap_fmt; ++ struct vb2_queue *peer_vq, *vq; ++ int ret; ++ ++ /* ++ * In order to support dynamic resolution change, the decoder admits ++ * a resolution change, as long as the pixelformat remains. Can't be ++ * done if streaming. ++ */ ++ vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); ++ if (vb2_is_streaming(vq) || ++ (vb2_is_busy(vq) && ++ f->fmt.pix_mp.pixelformat != ctx->coded_fmt.fmt.pix_mp.pixelformat)) ++ return -EBUSY; ++ ++ /* ++ * Since format change on the OUTPUT queue will reset the CAPTURE ++ * queue, we can't allow doing so when the CAPTURE queue has buffers ++ * allocated. ++ */ ++ peer_vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); ++ if (vb2_is_busy(peer_vq)) ++ return -EBUSY; ++ ++ ret = rkvdec2_try_output_fmt(file, priv, f); ++ if (ret) ++ return ret; ++ ++ desc = rkvdec2_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); ++ if (!desc) ++ return -EINVAL; ++ ctx->coded_fmt_desc = desc; ++ ctx->coded_fmt = *f; ++ ++ /* ++ * Current decoded format might have become invalid with newly ++ * selected codec, so reset it to default just to be safe and ++ * keep internal driver state sane. User is mandated to set ++ * the decoded format again after we return, so we don't need ++ * anything smarter. ++ * ++ * Note that this will propagate any size changes to the decoded format. ++ */ ++ rkvdec2_reset_decoded_fmt(ctx); ++ ++ /* Propagate colorspace information to capture. */ ++ cap_fmt = &ctx->decoded_fmt; ++ cap_fmt->fmt.pix_mp.colorspace = f->fmt.pix_mp.colorspace; ++ cap_fmt->fmt.pix_mp.xfer_func = f->fmt.pix_mp.xfer_func; ++ cap_fmt->fmt.pix_mp.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; ++ cap_fmt->fmt.pix_mp.quantization = f->fmt.pix_mp.quantization; ++ ++ /* Enable format specific queue features */ ++ vq->subsystem_flags |= desc->subsystem_flags; ++ ++ return 0; ++} ++ ++static int rkvdec2_g_output_fmt(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); ++ ++ *f = ctx->coded_fmt; ++ return 0; ++} ++ ++static int rkvdec2_g_capture_fmt(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); ++ ++ *f = ctx->decoded_fmt; ++ return 0; ++} ++ ++static int rkvdec2_enum_output_fmt(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ if (f->index >= ARRAY_SIZE(rkvdec2_coded_fmts)) ++ return -EINVAL; ++ ++ f->pixelformat = rkvdec2_coded_fmts[f->index].fourcc; ++ return 0; ++} ++ ++static int rkvdec2_enum_capture_fmt(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(priv); ++ ++ if (WARN_ON(!ctx->coded_fmt_desc)) ++ return -EINVAL; ++ ++ if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) ++ return -EINVAL; ++ ++ f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index]; ++ return 0; ++} ++ ++static const struct v4l2_ioctl_ops rkvdec2_ioctl_ops = { ++ .vidioc_querycap = rkvdec2_querycap, ++ .vidioc_enum_framesizes = rkvdec2_enum_framesizes, ++ ++ .vidioc_try_fmt_vid_cap_mplane = rkvdec2_try_capture_fmt, ++ .vidioc_try_fmt_vid_out_mplane = rkvdec2_try_output_fmt, ++ .vidioc_s_fmt_vid_out_mplane = rkvdec2_s_output_fmt, ++ .vidioc_s_fmt_vid_cap_mplane = rkvdec2_s_capture_fmt, ++ .vidioc_g_fmt_vid_out_mplane = rkvdec2_g_output_fmt, ++ .vidioc_g_fmt_vid_cap_mplane = rkvdec2_g_capture_fmt, ++ .vidioc_enum_fmt_vid_out = rkvdec2_enum_output_fmt, ++ .vidioc_enum_fmt_vid_cap = rkvdec2_enum_capture_fmt, ++ ++ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, ++ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, ++ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, ++ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, ++ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, ++ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, ++ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, ++ ++ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, ++ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, ++ ++ .vidioc_streamon = v4l2_m2m_ioctl_streamon, ++ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, ++ ++ .vidioc_decoder_cmd = v4l2_m2m_ioctl_stateless_decoder_cmd, ++ .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_stateless_try_decoder_cmd, ++}; ++ ++static int rkvdec2_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers, ++ unsigned int *num_planes, unsigned int sizes[], ++ struct device *alloc_devs[]) ++{ ++ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_format *f; ++ unsigned int i; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ f = &ctx->coded_fmt; ++ else ++ f = &ctx->decoded_fmt; ++ ++ if (*num_planes) { ++ if (*num_planes != f->fmt.pix_mp.num_planes) ++ return -EINVAL; ++ ++ for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { ++ if (sizes[i] < f->fmt.pix_mp.plane_fmt[i].sizeimage) ++ return -EINVAL; ++ } ++ } else { ++ *num_planes = f->fmt.pix_mp.num_planes; ++ for (i = 0; i < f->fmt.pix_mp.num_planes; i++) ++ sizes[i] = f->fmt.pix_mp.plane_fmt[i].sizeimage; ++ } ++ ++ return 0; ++} ++ ++static int rkvdec2_buf_prepare(struct vb2_buffer *vb) ++{ ++ struct vb2_queue *vq = vb->vb2_queue; ++ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_format *f; ++ unsigned int i; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ f = &ctx->coded_fmt; ++ else ++ f = &ctx->decoded_fmt; ++ ++ for (i = 0; i < f->fmt.pix_mp.num_planes; ++i) { ++ u32 sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; ++ ++ if (vb2_plane_size(vb, i) < sizeimage) ++ return -EINVAL; ++ } ++ ++ /* ++ * Buffer's bytesused must be written by driver for CAPTURE buffers. ++ * (for OUTPUT buffers, if userspace passes 0 bytesused, v4l2-core sets ++ * it to buffer length). ++ */ ++ if (V4L2_TYPE_IS_CAPTURE(vq->type)) ++ vb2_set_plane_payload(vb, 0, f->fmt.pix_mp.plane_fmt[0].sizeimage); ++ ++ return 0; ++} ++ ++static void rkvdec2_buf_queue(struct vb2_buffer *vb) ++{ ++ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ ++ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); ++} ++ ++static int rkvdec2_buf_out_validate(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ ++ vbuf->field = V4L2_FIELD_NONE; ++ return 0; ++} ++ ++static void rkvdec2_buf_request_complete(struct vb2_buffer *vb) ++{ ++ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); ++ ++ v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->ctrl_hdl); ++} ++ ++static void rkvdec2_free_rcb(struct rkvdec2_ctx *ctx) ++{ ++ u32 width, height; ++ int i; ++ ++ width = ctx->decoded_fmt.fmt.pix_mp.width; ++ height = ctx->decoded_fmt.fmt.pix_mp.height; ++ ++ for (i = 0; i < RKVDEC2_RCB_COUNT; i++) { ++ if (!ctx->rcb_bufs[i].cpu) ++ continue; ++ ++ switch (ctx->rcb_bufs[i].type) { ++ case RKVDEC2_ALLOC_SRAM: ++ gen_pool_free(ctx->dev->sram_pool, ++ (unsigned long)ctx->rcb_bufs[i].cpu, ++ RCB_SIZE(i)); ++ break; ++ case RKVDEC2_ALLOC_DMA: ++ dma_free_coherent(ctx->dev->dev, ++ RCB_SIZE(i), ++ ctx->rcb_bufs[i].cpu, ++ ctx->rcb_bufs[i].dma); ++ break; ++ } ++ } ++} ++ ++static int rkvdec2_allocate_rcb(struct rkvdec2_ctx *ctx) ++{ ++ int ret, i; ++ u32 width, height; ++ ++ memset(ctx->rcb_bufs, 0, sizeof(*ctx->rcb_bufs)); ++ ++ width = ctx->decoded_fmt.fmt.pix_mp.width; ++ height = ctx->decoded_fmt.fmt.pix_mp.height; ++ ++ for (i = 0; i < RKVDEC2_RCB_COUNT; i++) { ++ void *cpu = NULL; ++ dma_addr_t dma; ++ size_t rcb_size = RCB_SIZE(i); ++ enum rkvdec2_alloc_type alloc_type = RKVDEC2_ALLOC_SRAM; ++ ++ if (ctx->dev->sram_pool) { ++ cpu = gen_pool_dma_zalloc_align(ctx->dev->sram_pool, ++ rcb_size, ++ &dma, ++ 64); ++ } ++ ++ /* Fallback to RAM */ ++ if (!cpu) { ++ cpu = dma_alloc_coherent(ctx->dev->dev, ++ rcb_size, ++ &dma, ++ GFP_KERNEL); ++ alloc_type = RKVDEC2_ALLOC_DMA; ++ } ++ ++ if (!cpu) { ++ ret = -ENOMEM; ++ goto err_alloc; ++ } ++ ++ ctx->rcb_bufs[i].cpu = cpu; ++ ctx->rcb_bufs[i].dma = dma; ++ ctx->rcb_bufs[i].size = rcb_size; ++ ctx->rcb_bufs[i].type = alloc_type; ++ } ++ ++ return 0; ++ ++err_alloc: ++ rkvdec2_free_rcb(ctx); ++ ++ return ret; ++} ++ ++static int rkvdec2_start_streaming(struct vb2_queue *q, unsigned int count) ++{ ++ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(q); ++ const struct rkvdec2_coded_fmt_desc *desc; ++ int ret; ++ ++ if (V4L2_TYPE_IS_CAPTURE(q->type)) ++ return 0; ++ ++ desc = ctx->coded_fmt_desc; ++ if (WARN_ON(!desc)) ++ return -EINVAL; ++ ++ ret = rkvdec2_allocate_rcb(ctx); ++ if (ret) ++ return ret; ++ ++ if (desc->ops->start) { ++ ret = desc->ops->start(ctx); ++ if (ret) ++ goto err_ops_start; ++ } ++ ++ return 0; ++ ++err_ops_start: ++ rkvdec2_free_rcb(ctx); ++ ++ return ret; ++} ++ ++static void rkvdec2_queue_cleanup(struct vb2_queue *vq, u32 state) ++{ ++ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(vq); ++ ++ while (true) { ++ struct vb2_v4l2_buffer *vbuf; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ else ++ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ if (!vbuf) ++ break; ++ ++ v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req, ++ &ctx->ctrl_hdl); ++ v4l2_m2m_buf_done(vbuf, state); ++ } ++} ++ ++static void rkvdec2_stop_streaming(struct vb2_queue *q) ++{ ++ struct rkvdec2_ctx *ctx = vb2_get_drv_priv(q); ++ ++ if (V4L2_TYPE_IS_OUTPUT(q->type)) { ++ const struct rkvdec2_coded_fmt_desc *desc = ctx->coded_fmt_desc; ++ ++ if (WARN_ON(!desc)) ++ return; ++ ++ if (desc->ops->stop) ++ desc->ops->stop(ctx); ++ ++ rkvdec2_free_rcb(ctx); ++ } ++ ++ rkvdec2_queue_cleanup(q, VB2_BUF_STATE_ERROR); ++} ++ ++static const struct vb2_ops rkvdec2_queue_ops = { ++ .queue_setup = rkvdec2_queue_setup, ++ .buf_prepare = rkvdec2_buf_prepare, ++ .buf_queue = rkvdec2_buf_queue, ++ .buf_out_validate = rkvdec2_buf_out_validate, ++ .buf_request_complete = rkvdec2_buf_request_complete, ++ .start_streaming = rkvdec2_start_streaming, ++ .stop_streaming = rkvdec2_stop_streaming, ++ .wait_prepare = vb2_ops_wait_prepare, ++ .wait_finish = vb2_ops_wait_finish, ++}; ++ ++static int rkvdec2_request_validate(struct media_request *req) ++{ ++ unsigned int count; ++ ++ count = vb2_request_buffer_cnt(req); ++ if (!count) ++ return -ENOENT; ++ else if (count > 1) ++ return -EINVAL; ++ ++ return vb2_request_validate(req); ++} ++ ++static const struct media_device_ops rkvdec2_media_ops = { ++ .req_validate = rkvdec2_request_validate, ++ .req_queue = v4l2_m2m_request_queue, ++}; ++ ++static void rkvdec2_job_finish_no_pm(struct rkvdec2_ctx *ctx, ++ enum vb2_buffer_state result) ++{ ++ if (ctx->coded_fmt_desc->ops->done) { ++ struct vb2_v4l2_buffer *src_buf, *dst_buf; ++ ++ src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); ++ dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); ++ ctx->coded_fmt_desc->ops->done(ctx, src_buf, dst_buf, result); ++ } ++ ++ v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx, ++ result); ++} ++ ++static void rkvdec2_job_finish(struct rkvdec2_ctx *ctx, ++ enum vb2_buffer_state result) ++{ ++ struct rkvdec2_dev *rkvdec = ctx->dev; ++ ++ pm_runtime_mark_last_busy(rkvdec->dev); ++ pm_runtime_put_autosuspend(rkvdec->dev); ++ rkvdec2_job_finish_no_pm(ctx, result); ++} ++ ++void rkvdec2_run_preamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run) ++{ ++ struct media_request *src_req; ++ ++ memset(run, 0, sizeof(*run)); ++ ++ run->bufs.src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); ++ run->bufs.dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); ++ ++ /* Apply request(s) controls if needed. */ ++ src_req = run->bufs.src->vb2_buf.req_obj.req; ++ if (src_req) ++ v4l2_ctrl_request_setup(src_req, &ctx->ctrl_hdl); ++ ++ v4l2_m2m_buf_copy_metadata(run->bufs.src, run->bufs.dst, true); ++} ++ ++void rkvdec2_run_postamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run) ++{ ++ struct media_request *src_req = run->bufs.src->vb2_buf.req_obj.req; ++ ++ if (src_req) ++ v4l2_ctrl_request_complete(src_req, &ctx->ctrl_hdl); ++} ++ ++static void rkvdec2_device_run(void *priv) ++{ ++ struct rkvdec2_ctx *ctx = priv; ++ struct rkvdec2_dev *rkvdec = ctx->dev; ++ const struct rkvdec2_coded_fmt_desc *desc = ctx->coded_fmt_desc; ++ int ret; ++ ++ if (WARN_ON(!desc)) ++ return; ++ ++ ret = pm_runtime_resume_and_get(rkvdec->dev); ++ if (ret < 0) { ++ rkvdec2_job_finish_no_pm(ctx, VB2_BUF_STATE_ERROR); ++ return; ++ } ++ ++ ret = desc->ops->run(ctx); ++ if (ret) ++ rkvdec2_job_finish(ctx, VB2_BUF_STATE_ERROR); ++} ++ ++static const struct v4l2_m2m_ops rkvdec2_m2m_ops = { ++ .device_run = rkvdec2_device_run, ++}; ++ ++static int rkvdec2_queue_init(void *priv, ++ struct vb2_queue *src_vq, ++ struct vb2_queue *dst_vq) ++{ ++ struct rkvdec2_ctx *ctx = priv; ++ struct rkvdec2_dev *rkvdec = ctx->dev; ++ int ret; ++ ++ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; ++ src_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ src_vq->drv_priv = ctx; ++ src_vq->ops = &rkvdec2_queue_ops; ++ src_vq->mem_ops = &vb2_dma_contig_memops; ++ ++ /* ++ * No CPU access on the queues, so no kernel mapping needed. ++ */ ++ src_vq->dma_attrs = DMA_ATTR_NO_KERNEL_MAPPING; ++ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ src_vq->lock = &rkvdec->vdev_lock; ++ src_vq->dev = rkvdec->v4l2_dev.dev; ++ src_vq->supports_requests = true; ++ src_vq->requires_requests = true; ++ ++ ret = vb2_queue_init(src_vq); ++ if (ret) ++ return ret; ++ ++ dst_vq->bidirectional = true; ++ dst_vq->mem_ops = &vb2_dma_contig_memops; ++ dst_vq->dma_attrs = DMA_ATTR_NO_KERNEL_MAPPING; ++ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; ++ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ dst_vq->drv_priv = ctx; ++ dst_vq->ops = &rkvdec2_queue_ops; ++ dst_vq->buf_struct_size = sizeof(struct rkvdec2_decoded_buffer); ++ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ dst_vq->lock = &rkvdec->vdev_lock; ++ dst_vq->dev = rkvdec->v4l2_dev.dev; ++ ++ return vb2_queue_init(dst_vq); ++} ++ ++static int rkvdec2_add_ctrls(struct rkvdec2_ctx *ctx, ++ const struct rkvdec2_ctrls *ctrls) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ctrls->num_ctrls; i++) { ++ const struct v4l2_ctrl_config *cfg = &ctrls->ctrls[i].cfg; ++ ++ v4l2_ctrl_new_custom(&ctx->ctrl_hdl, cfg, ctx); ++ if (ctx->ctrl_hdl.error) ++ return ctx->ctrl_hdl.error; ++ } ++ ++ return 0; ++} ++ ++static int rkvdec2_init_ctrls(struct rkvdec2_ctx *ctx) ++{ ++ unsigned int i, nctrls = 0; ++ int ret; ++ ++ for (i = 0; i < ARRAY_SIZE(rkvdec2_coded_fmts); i++) ++ nctrls += rkvdec2_coded_fmts[i].ctrls->num_ctrls; ++ ++ v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); ++ ++ for (i = 0; i < ARRAY_SIZE(rkvdec2_coded_fmts); i++) { ++ ret = rkvdec2_add_ctrls(ctx, rkvdec2_coded_fmts[i].ctrls); ++ if (ret) ++ goto err_free_handler; ++ } ++ ++ ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); ++ if (ret) ++ goto err_free_handler; ++ ++ ctx->fh.ctrl_handler = &ctx->ctrl_hdl; ++ return 0; ++ ++err_free_handler: ++ v4l2_ctrl_handler_free(&ctx->ctrl_hdl); ++ return ret; ++} ++ ++static int rkvdec2_open(struct file *filp) ++{ ++ struct rkvdec2_dev *rkvdec = video_drvdata(filp); ++ struct rkvdec2_ctx *ctx; ++ int ret; ++ ++ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); ++ if (!ctx) ++ return -ENOMEM; ++ ++ ctx->dev = rkvdec; ++ rkvdec2_reset_coded_fmt(ctx); ++ rkvdec2_reset_decoded_fmt(ctx); ++ v4l2_fh_init(&ctx->fh, video_devdata(filp)); ++ ++ ret = rkvdec2_init_ctrls(ctx); ++ if (ret) ++ goto err_free_ctx; ++ ++ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rkvdec->m2m_dev, ctx, ++ rkvdec2_queue_init); ++ if (IS_ERR(ctx->fh.m2m_ctx)) { ++ ret = PTR_ERR(ctx->fh.m2m_ctx); ++ goto err_cleanup_ctrls; ++ } ++ ++ filp->private_data = &ctx->fh; ++ v4l2_fh_add(&ctx->fh); ++ ++ return 0; ++ ++err_cleanup_ctrls: ++ v4l2_ctrl_handler_free(&ctx->ctrl_hdl); ++ ++err_free_ctx: ++ kfree(ctx); ++ return ret; ++} ++ ++static int rkvdec2_release(struct file *filp) ++{ ++ struct rkvdec2_ctx *ctx = fh_to_rkvdec2_ctx(filp->private_data); ++ ++ v4l2_fh_del(&ctx->fh); ++ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); ++ v4l2_ctrl_handler_free(&ctx->ctrl_hdl); ++ v4l2_fh_exit(&ctx->fh); ++ kfree(ctx); ++ ++ return 0; ++} ++ ++static const struct v4l2_file_operations rkvdec2_fops = { ++ .owner = THIS_MODULE, ++ .open = rkvdec2_open, ++ .release = rkvdec2_release, ++ .poll = v4l2_m2m_fop_poll, ++ .unlocked_ioctl = video_ioctl2, ++ .mmap = v4l2_m2m_fop_mmap, ++}; ++ ++static int rkvdec2_v4l2_init(struct rkvdec2_dev *rkvdec) ++{ ++ int ret; ++ ++ ret = v4l2_device_register(rkvdec->dev, &rkvdec->v4l2_dev); ++ if (ret) { ++ dev_err(rkvdec->dev, "Failed to register V4L2 device\n"); ++ return ret; ++ } ++ ++ rkvdec->m2m_dev = v4l2_m2m_init(&rkvdec2_m2m_ops); ++ if (IS_ERR(rkvdec->m2m_dev)) { ++ v4l2_err(&rkvdec->v4l2_dev, "Failed to init mem2mem device\n"); ++ ret = PTR_ERR(rkvdec->m2m_dev); ++ goto err_unregister_v4l2; ++ } ++ ++ rkvdec->mdev.dev = rkvdec->dev; ++ strscpy(rkvdec->mdev.model, "rkvdec2", sizeof(rkvdec->mdev.model)); ++ strscpy(rkvdec->mdev.bus_info, "platform:rkvdec2", ++ sizeof(rkvdec->mdev.bus_info)); ++ media_device_init(&rkvdec->mdev); ++ rkvdec->mdev.ops = &rkvdec2_media_ops; ++ rkvdec->v4l2_dev.mdev = &rkvdec->mdev; ++ ++ rkvdec->vdev.lock = &rkvdec->vdev_lock; ++ rkvdec->vdev.v4l2_dev = &rkvdec->v4l2_dev; ++ rkvdec->vdev.fops = &rkvdec2_fops; ++ rkvdec->vdev.release = video_device_release_empty; ++ rkvdec->vdev.vfl_dir = VFL_DIR_M2M; ++ rkvdec->vdev.device_caps = V4L2_CAP_STREAMING | ++ V4L2_CAP_VIDEO_M2M_MPLANE; ++ rkvdec->vdev.ioctl_ops = &rkvdec2_ioctl_ops; ++ video_set_drvdata(&rkvdec->vdev, rkvdec); ++ strscpy(rkvdec->vdev.name, "rkvdec2", sizeof(rkvdec->vdev.name)); ++ ++ ret = video_register_device(&rkvdec->vdev, VFL_TYPE_VIDEO, -1); ++ if (ret) { ++ v4l2_err(&rkvdec->v4l2_dev, "Failed to register video device\n"); ++ goto err_cleanup_mc; ++ } ++ ++ ret = v4l2_m2m_register_media_controller(rkvdec->m2m_dev, &rkvdec->vdev, ++ MEDIA_ENT_F_PROC_VIDEO_DECODER); ++ if (ret) { ++ v4l2_err(&rkvdec->v4l2_dev, ++ "Failed to initialize V4L2 M2M media controller\n"); ++ goto err_unregister_vdev; ++ } ++ ++ ret = media_device_register(&rkvdec->mdev); ++ if (ret) { ++ v4l2_err(&rkvdec->v4l2_dev, "Failed to register media device\n"); ++ goto err_unregister_mc; ++ } ++ ++ return 0; ++ ++err_unregister_mc: ++ v4l2_m2m_unregister_media_controller(rkvdec->m2m_dev); ++ ++err_unregister_vdev: ++ video_unregister_device(&rkvdec->vdev); ++ ++err_cleanup_mc: ++ media_device_cleanup(&rkvdec->mdev); ++ v4l2_m2m_release(rkvdec->m2m_dev); ++ ++err_unregister_v4l2: ++ v4l2_device_unregister(&rkvdec->v4l2_dev); ++ return ret; ++} ++ ++static void rkvdec2_v4l2_cleanup(struct rkvdec2_dev *rkvdec) ++{ ++ media_device_unregister(&rkvdec->mdev); ++ v4l2_m2m_unregister_media_controller(rkvdec->m2m_dev); ++ video_unregister_device(&rkvdec->vdev); ++ media_device_cleanup(&rkvdec->mdev); ++ v4l2_m2m_release(rkvdec->m2m_dev); ++ v4l2_device_unregister(&rkvdec->v4l2_dev); ++} ++ ++static irqreturn_t rkvdec2_irq_handler(int irq, void *priv) ++{ ++ struct rkvdec2_dev *rkvdec = priv; ++ enum vb2_buffer_state state; ++ u32 status; ++ ++ status = readl(rkvdec->regs + RKVDEC2_REG_STA_INT); ++ state = (status & STA_INT_DEC_RDY_STA) ? ++ VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; ++ ++ /* Clear interrupt status */ ++ writel(0, rkvdec->regs + RKVDEC2_REG_STA_INT); ++ if (cancel_delayed_work(&rkvdec->watchdog_work)) { ++ struct rkvdec2_ctx *ctx; ++ ++ ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); ++ rkvdec2_job_finish(ctx, state); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static void rkvdec2_watchdog_func(struct work_struct *work) ++{ ++ struct rkvdec2_dev *rkvdec = container_of(to_delayed_work(work), struct rkvdec2_dev, ++ watchdog_work); ++ struct rkvdec2_ctx *ctx; ++ ++ ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); ++ if (ctx) { ++ dev_err(rkvdec->dev, "Frame processing timed out!\n"); ++ writel(RKVDEC2_REG_DEC_IRQ_DISABLE, rkvdec->regs + RKVDEC2_REG_IMPORTANT_EN); ++ writel(0, rkvdec->regs + RKVDEC2_REG_DEC_E); ++ rkvdec2_job_finish(ctx, VB2_BUF_STATE_ERROR); ++ } ++} ++ ++static const struct of_device_id of_rkvdec2_match[] = { ++ { .compatible = "rockchip,rk3588-vdec" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, of_rkvdec2_match); ++ ++static const char * const rkvdec2_clk_names[] = { ++ "axi", ++ "ahb", ++ "core", ++ "cabac", ++ "hevc_cabac", ++}; ++ ++/* ++ * Some SoCs, like RK3588 have multiple identical vdpu34x cores, but the ++ * kernel is currently missing support for multi-core handling. Exposing ++ * separate devices for each core to userspace is bad, since that does ++ * not allow scheduling tasks properly (and creates ABI). With this workaround ++ * the driver will only probe for the first core and early exit for the other ++ * cores. Once the driver gains multi-core support, the same technique ++ * for detecting the main core can be used to cluster all cores together. ++ */ ++static int rkvdec2_disable_multicore(struct rkvdec2_dev *rkvdec) ++{ ++ const char *compatible; ++ struct device_node *node; ++ int ret; ++ ++ /* Intentionally ignores the fallback strings */ ++ ret = of_property_read_string(rkvdec->dev->of_node, "compatible", &compatible); ++ if (ret) ++ return ret; ++ ++ /* first compatible node found from the root node is considered the main core */ ++ node = of_find_compatible_node(NULL, NULL, compatible); ++ if (!node) ++ return -EINVAL; /* broken DT? */ ++ ++ if (rkvdec->dev->of_node != node) { ++ dev_info(rkvdec->dev, "missing multi-core support, ignoring this instance\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static int rkvdec2_probe(struct platform_device *pdev) ++{ ++ struct rkvdec2_dev *rkvdec; ++ unsigned int i; ++ int ret, irq; ++ ++ rkvdec = devm_kzalloc(&pdev->dev, sizeof(*rkvdec), GFP_KERNEL); ++ if (!rkvdec) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, rkvdec); ++ rkvdec->dev = &pdev->dev; ++ ++ ret = rkvdec2_disable_multicore(rkvdec); ++ if (ret) ++ return ret; ++ ++ mutex_init(&rkvdec->vdev_lock); ++ INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec2_watchdog_func); ++ ++ rkvdec->clocks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(rkvdec2_clk_names), ++ sizeof(*rkvdec->clocks), GFP_KERNEL); ++ if (!rkvdec->clocks) ++ return -ENOMEM; ++ ++ for (i = 0; i < ARRAY_SIZE(rkvdec2_clk_names); i++) ++ rkvdec->clocks[i].id = rkvdec2_clk_names[i]; ++ ++ ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(rkvdec2_clk_names), ++ rkvdec->clocks); ++ if (ret) ++ return ret; ++ ++ rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(rkvdec->regs)) ++ return PTR_ERR(rkvdec->regs); ++ ++ /* ++ * Without IOMMU support, keep DMA in the lower 32 bits. ++ */ ++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n"); ++ return ret; ++ } ++ ++ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq <= 0) ++ return -ENXIO; ++ ++ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, ++ rkvdec2_irq_handler, IRQF_ONESHOT, ++ dev_name(&pdev->dev), rkvdec); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not request vdec2 IRQ\n"); ++ return ret; ++ } ++ ++ rkvdec->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0); ++ if (!rkvdec->sram_pool) ++ dev_info(&pdev->dev, "No sram node, RCB will be stored in RAM\n"); ++ ++ pm_runtime_set_autosuspend_delay(&pdev->dev, 100); ++ pm_runtime_use_autosuspend(&pdev->dev); ++ pm_runtime_enable(&pdev->dev); ++ ++ ret = rkvdec2_v4l2_init(rkvdec); ++ if (ret) ++ goto err_disable_runtime_pm; ++ ++ return 0; ++ ++err_disable_runtime_pm: ++ pm_runtime_dont_use_autosuspend(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ ++ if (rkvdec->sram_pool) ++ gen_pool_destroy(rkvdec->sram_pool); ++ ++ return ret; ++} ++ ++static void rkvdec2_remove(struct platform_device *pdev) ++{ ++ struct rkvdec2_dev *rkvdec = platform_get_drvdata(pdev); ++ ++ cancel_delayed_work_sync(&rkvdec->watchdog_work); ++ ++ rkvdec2_v4l2_cleanup(rkvdec); ++ pm_runtime_disable(&pdev->dev); ++ pm_runtime_dont_use_autosuspend(&pdev->dev); ++ ++ if (rkvdec->sram_pool) ++ gen_pool_destroy(rkvdec->sram_pool); ++} ++ ++#ifdef CONFIG_PM ++static int rkvdec2_runtime_resume(struct device *dev) ++{ ++ struct rkvdec2_dev *rkvdec = dev_get_drvdata(dev); ++ ++ return clk_bulk_prepare_enable(ARRAY_SIZE(rkvdec2_clk_names), ++ rkvdec->clocks); ++} ++ ++static int rkvdec2_runtime_suspend(struct device *dev) ++{ ++ struct rkvdec2_dev *rkvdec = dev_get_drvdata(dev); ++ ++ clk_bulk_disable_unprepare(ARRAY_SIZE(rkvdec2_clk_names), ++ rkvdec->clocks); ++ return 0; ++} ++#endif ++ ++static const struct dev_pm_ops rkvdec2_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++ SET_RUNTIME_PM_OPS(rkvdec2_runtime_suspend, rkvdec2_runtime_resume, NULL) ++}; ++ ++static struct platform_driver rkvdec2_driver = { ++ .probe = rkvdec2_probe, ++ .remove_new = rkvdec2_remove, ++ .driver = { ++ .name = "rkvdec2", ++ .of_match_table = of_rkvdec2_match, ++ .pm = &rkvdec2_pm_ops, ++ }, ++}; ++module_platform_driver(rkvdec2_driver); ++ ++MODULE_AUTHOR("Detlev Casanova "); ++MODULE_DESCRIPTION("Rockchip Video Decoder 2 driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/staging/media/rkvdec2/rkvdec2.h b/drivers/staging/media/rkvdec2/rkvdec2.h +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/staging/media/rkvdec2/rkvdec2.h +@@ -0,0 +1,130 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Rockchip Video Decoder 2 driver ++ * ++ * Copyright (C) 2024 Collabora, Ltd. ++ * Detlev Casanova ++ * ++ * Based on rkvdec driver by Boris Brezillon ++ */ ++#ifndef RKVDEC_H_ ++#define RKVDEC_H_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "rkvdec2-regs.h" ++ ++#define RKVDEC2_RCB_COUNT 10 ++ ++struct rkvdec2_ctx; ++ ++enum rkvdec2_alloc_type { ++ RKVDEC2_ALLOC_SRAM, ++ RKVDEC2_ALLOC_DMA, ++}; ++ ++struct rkvdec2_aux_buf { ++ void *cpu; ++ dma_addr_t dma; ++ size_t size; ++ enum rkvdec2_alloc_type type; ++}; ++ ++struct rkvdec2_ctrl_desc { ++ struct v4l2_ctrl_config cfg; ++}; ++ ++struct rkvdec2_ctrls { ++ const struct rkvdec2_ctrl_desc *ctrls; ++ unsigned int num_ctrls; ++}; ++ ++struct rkvdec2_run { ++ struct { ++ struct vb2_v4l2_buffer *src; ++ struct vb2_v4l2_buffer *dst; ++ } bufs; ++}; ++ ++struct rkvdec2_decoded_buffer { ++ /* Must be the first field in this struct. */ ++ struct v4l2_m2m_buffer base; ++}; ++ ++static inline struct rkvdec2_decoded_buffer * ++vb2_to_rkvdec2_decoded_buf(struct vb2_buffer *buf) ++{ ++ return container_of(buf, struct rkvdec2_decoded_buffer, ++ base.vb.vb2_buf); ++} ++ ++struct rkvdec2_coded_fmt_ops { ++ int (*adjust_fmt)(struct rkvdec2_ctx *ctx, ++ struct v4l2_format *f); ++ int (*start)(struct rkvdec2_ctx *ctx); ++ void (*stop)(struct rkvdec2_ctx *ctx); ++ int (*run)(struct rkvdec2_ctx *ctx); ++ void (*done)(struct rkvdec2_ctx *ctx, struct vb2_v4l2_buffer *src_buf, ++ struct vb2_v4l2_buffer *dst_buf, ++ enum vb2_buffer_state result); ++ int (*try_ctrl)(struct rkvdec2_ctx *ctx, struct v4l2_ctrl *ctrl); ++}; ++ ++struct rkvdec2_coded_fmt_desc { ++ u32 fourcc; ++ struct v4l2_frmsize_stepwise frmsize; ++ const struct rkvdec2_ctrls *ctrls; ++ const struct rkvdec2_coded_fmt_ops *ops; ++ unsigned int num_decoded_fmts; ++ const u32 *decoded_fmts; ++ u32 subsystem_flags; ++}; ++ ++struct rkvdec2_dev { ++ struct v4l2_device v4l2_dev; ++ struct media_device mdev; ++ struct video_device vdev; ++ struct v4l2_m2m_dev *m2m_dev; ++ struct device *dev; ++ struct clk_bulk_data *clocks; ++ void __iomem *regs; ++ struct gen_pool *sram_pool; ++ struct mutex vdev_lock; /* serializes ioctls */ ++ struct delayed_work watchdog_work; ++}; ++ ++struct rkvdec2_ctx { ++ struct v4l2_fh fh; ++ struct v4l2_format coded_fmt; ++ struct v4l2_format decoded_fmt; ++ const struct rkvdec2_coded_fmt_desc *coded_fmt_desc; ++ struct v4l2_ctrl_handler ctrl_hdl; ++ struct rkvdec2_dev *dev; ++ struct rkvdec2_aux_buf rcb_bufs[RKVDEC2_RCB_COUNT]; ++ ++ u32 colmv_offset; ++ ++ void *priv; ++}; ++ ++static inline struct rkvdec2_ctx *fh_to_rkvdec2_ctx(struct v4l2_fh *fh) ++{ ++ return container_of(fh, struct rkvdec2_ctx, fh); ++} ++ ++void rkvdec2_run_preamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run); ++void rkvdec2_run_postamble(struct rkvdec2_ctx *ctx, struct rkvdec2_run *run); ++ ++extern const struct rkvdec2_coded_fmt_ops rkvdec2_h264_fmt_ops; ++ ++#endif /* RKVDEC_H_ */ +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Thu, 20 Jun 2024 10:19:46 -0400 +Subject: arm64: dts: rockchip: Add rkvdec2 Video Decoder on rk3588(s) + +Add the rkvdec2 Video Decoder to the RK3588s devicetree. + +Signed-off-by: Detlev Casanova +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 ++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -3001,6 +3001,16 @@ system_sram2: sram@ff001000 { + ranges = <0x0 0x0 0xff001000 0xef000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ vdec0_sram: rkvdec-sram@0 { ++ reg = <0x0 0x78000>; ++ pool; ++ }; ++ ++ vdec1_sram: rkvdec-sram@1 { ++ reg = <0x78000 0x77000>; ++ pool; ++ }; + }; + + pinctrl: pinctrl { +@@ -3070,6 +3080,44 @@ gpio4: gpio@fec50000 { + #interrupt-cells = <2>; + }; + }; ++ ++ vdec0: video-decoder@fdc38100 { ++ compatible = "rockchip,rk3588-vdec"; ++ reg = <0x0 0xfdc38100 0x0 0x500>; ++ interrupts = ; ++ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, ++ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; ++ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, ++ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; ++ assigned-clock-rates = <800000000>, <600000000>, ++ <600000000>, <1000000000>; ++ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, ++ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; ++ reset-names = "rst_axi", "rst_ahb", "rst_cabac", ++ "rst_core", "rst_hevc_cabac"; ++ power-domains = <&power RK3588_PD_RKVDEC0>; ++ sram = <&vdec0_sram>; ++ }; ++ ++ vdec1: video-decoder@fdc40100 { ++ compatible = "rockchip,rk3588-vdec"; ++ reg = <0x0 0xfdc40100 0x0 0x500>; ++ interrupts = ; ++ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, ++ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; ++ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, ++ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; ++ assigned-clock-rates = <800000000>, <600000000>, ++ <600000000>, <1000000000>; ++ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, ++ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; ++ reset-names = "rst_axi", "rst_ahb", "rst_cabac", ++ "rst_core", "rst_hevc_cabac"; ++ power-domains = <&power RK3588_PD_RKVDEC1>; ++ sram = <&vdec1_sram>; ++ }; + }; + + #include "rk3588s-pinctrl.dtsi" +-- +Armbian + diff --git a/kernel.patches/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch b/kernel.patches/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch new file mode 100644 index 0000000..13b5aec --- /dev/null +++ b/kernel.patches/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch @@ -0,0 +1,43 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: amazingfate +Date: Fri, 21 Jun 2024 16:32:55 +0800 +Subject: media: v4l2-core: Initialize h264 frame_mbs_only_flag as 1 + +--- + drivers/media/v4l2-core/v4l2-ctrls-core.c | 13 ++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c +index 111111111111..222222222222 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls-core.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c +@@ -111,6 +111,7 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx, + struct v4l2_ctrl_vp9_frame *p_vp9_frame; + struct v4l2_ctrl_fwht_params *p_fwht_params; + struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; ++ struct v4l2_ctrl_h264_sps *p_h264_sps; + struct v4l2_ctrl_av1_sequence *p_av1_sequence; + void *p = ptr.p + idx * ctrl->elem_size; + +@@ -179,6 +180,18 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx, + */ + memset(p_h264_scaling_matrix, 16, sizeof(*p_h264_scaling_matrix)); + break; ++ case V4L2_CTRL_TYPE_H264_SPS: ++ p_h264_sps = p; ++ /* ++ * Without V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY, ++ * frame_mbs_only_flag set to 0 will translate to a miniumum ++ * height of 32 (see H.264 specification 7-8). Some driver may ++ * have a minimum size lower then 32, which would fail ++ * validation with the SPS value. Set this flag, so that there ++ * is now doubling in the height, allowing a valid default. ++ */ ++ p_h264_sps->flags = V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY; ++ break; + } + } + +-- +Armbian + diff --git a/kernel.patches/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch b/kernel.patches/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch new file mode 100644 index 0000000..0e5c748 --- /dev/null +++ b/kernel.patches/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch @@ -0,0 +1,81 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Mon, 15 Jan 2024 22:47:41 +0200 +Subject: arm64: dts: rockchip: Add HDMI0 bridge to rk3588 + +Add DT node for the HDMI0 bridge found on RK3588 SoC. + +Signed-off-by: Cristian Ciocaltea +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 55 ++++++++++ + 1 file changed, 55 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1516,6 +1516,61 @@ i2s9_8ch: i2s@fddfc000 { + status = "disabled"; + }; + ++ hdmi0: hdmi@fde80000 { ++ compatible = "rockchip,rk3588-dw-hdmi"; ++ reg = <0x0 0xfde80000 0x0 0x20000>; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ clocks = <&cru PCLK_HDMITX0>, ++ <&cru CLK_HDMIHDP0>, ++ <&cru CLK_HDMITX0_EARC>, ++ <&cru CLK_HDMITX0_REF>, ++ <&cru MCLK_I2S5_8CH_TX>, ++ <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, ++ <&cru DCLK_VOP2>, ++ <&cru DCLK_VOP3>, ++ <&cru HCLK_VO1>; ++ clock-names = "pclk", ++ "hpd", ++ "earc", ++ "hdmitx_ref", ++ "aud", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3", ++ "hclk_vo1"; ++ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; ++ reset-names = "ref", "hdp"; ++ power-domains = <&power RK3588_PD_VO1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd ++ &hdmim0_tx0_scl &hdmim0_tx0_sda>; ++ reg-io-width = <4>; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo1_grf = <&vo1_grf>; ++ phys = <&hdptxphy_hdmi0>; ++ phy-names = "hdmi"; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi0_in: port@0 { ++ reg = <0>; ++ }; ++ ++ hdmi0_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ + qos_gpu_m0: qos@fdf35000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; +-- +Armbian + diff --git a/kernel.patches/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch b/kernel.patches/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch new file mode 100644 index 0000000..6013a8d --- /dev/null +++ b/kernel.patches/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch @@ -0,0 +1,26 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Tue, 16 Jan 2024 03:13:38 +0200 +Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on rk3588 + +The HDMI0 PHY can be used as a clock provider on RK3588, hence add the +missing #clock-cells property. +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -2985,6 +2985,7 @@ hdptxphy_hdmi0: phy@fed60000 { + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; ++ #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, +-- +Armbian + diff --git a/kernel.patches/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch b/kernel.patches/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch new file mode 100644 index 0000000..edcf535 --- /dev/null +++ b/kernel.patches/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch @@ -0,0 +1,549 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Mon, 5 Feb 2024 01:38:48 +0200 +Subject: phy: phy-rockchip-samsung-hdptx: Add FRL & EARC support + +For upstreaming, this requires extending the standard PHY API to support +HDMI configuration options [1]. + +Currently, the bus_width PHY attribute is used to pass clock rate and +flags for 10-bit color depth, FRL and EARC. This is done by the HDMI +bridge driver via phy_set_bus_width(). + +[1]: https://lore.kernel.org/all/59d5595a24bbcca897e814440179fa2caf3dff38.1707040881.git.Sandor.yu@nxp.com/ + +Signed-off-by: Cristian Ciocaltea +--- + drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 434 +++++++++- + 1 file changed, 431 insertions(+), 3 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +index 111111111111..222222222222 100644 +--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c ++++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +@@ -190,6 +190,12 @@ + #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3) + #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2) + ++#define HDMI20_MAX_RATE 600000000 ++#define DATA_RATE_MASK 0xFFFFFFF ++#define COLOR_DEPTH_MASK BIT(31) ++#define HDMI_MODE_MASK BIT(30) ++#define HDMI_EARC_MASK BIT(29) ++ + struct lcpll_config { + u32 bit_rate; + u8 lcvco_mode_en; +@@ -272,6 +278,25 @@ struct rk_hdptx_phy { + struct clk_bulk_data *clks; + int nr_clks; + struct reset_control_bulk_data rsts[RST_MAX]; ++ bool earc_en; ++}; ++ ++static const struct lcpll_config lcpll_cfg[] = { ++ { 48000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2, ++ 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, ++ { 40000000, 1, 1, 0, 0x68, 0x68, 1, 1, 0, 0, 0, 1, 1, 1, 1, 9, 0, 1, 1, ++ 0, 2, 3, 1, 0, 0x20, 0x0c, 1, 0, }, ++ { 32000000, 1, 1, 1, 0x6b, 0x6b, 1, 1, 0, 1, 2, 1, 1, 1, 1, 9, 1, 2, 1, ++ 0, 0x0d, 0x18, 1, 0, 0x20, 0x0c, 1, 1, }, ++}; ++ ++static const struct ropll_config ropll_frl_cfg[] = { ++ { 24000000, 0x19, 0x19, 1, 1, 0, 1, 2, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, ++ 0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, ++ { 18000000, 0x7d, 0x7d, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, ++ 0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, ++ { 9000000, 0x7d, 0x7d, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, ++ 0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, + }; + + static const struct ropll_config ropll_tmds_cfg[] = { +@@ -449,6 +474,73 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = { + REG_SEQ0(CMN_REG(009b), 0x00), + }; + ++static const struct reg_sequence rk_hdtpx_frl_cmn_init_seq[] = { ++ REG_SEQ0(CMN_REG(0011), 0x00), ++ REG_SEQ0(CMN_REG(0017), 0x00), ++ REG_SEQ0(CMN_REG(0026), 0x53), ++ REG_SEQ0(CMN_REG(0030), 0x00), ++ REG_SEQ0(CMN_REG(0031), 0x20), ++ REG_SEQ0(CMN_REG(0032), 0x30), ++ REG_SEQ0(CMN_REG(0033), 0x0b), ++ REG_SEQ0(CMN_REG(0034), 0x23), ++ REG_SEQ0(CMN_REG(0042), 0xb8), ++ REG_SEQ0(CMN_REG(004e), 0x14), ++ REG_SEQ0(CMN_REG(0074), 0x00), ++ REG_SEQ0(CMN_REG(0081), 0x09), ++ REG_SEQ0(CMN_REG(0086), 0x01), ++ REG_SEQ0(CMN_REG(0087), 0x0c), ++ REG_SEQ0(CMN_REG(009b), 0x10), ++}; ++ ++static const struct reg_sequence rk_hdtpx_frl_ropll_cmn_init_seq[] = { ++ REG_SEQ0(CMN_REG(0008), 0x00), ++ REG_SEQ0(CMN_REG(001e), 0x14), ++ REG_SEQ0(CMN_REG(0020), 0x00), ++ REG_SEQ0(CMN_REG(0021), 0x00), ++ REG_SEQ0(CMN_REG(0022), 0x11), ++ REG_SEQ0(CMN_REG(0023), 0x00), ++ REG_SEQ0(CMN_REG(0025), 0x00), ++ REG_SEQ0(CMN_REG(0027), 0x00), ++ REG_SEQ0(CMN_REG(0028), 0x00), ++ REG_SEQ0(CMN_REG(002a), 0x01), ++ REG_SEQ0(CMN_REG(002b), 0x00), ++ REG_SEQ0(CMN_REG(002c), 0x00), ++ REG_SEQ0(CMN_REG(002d), 0x00), ++ REG_SEQ0(CMN_REG(002e), 0x00), ++ REG_SEQ0(CMN_REG(002f), 0x04), ++ REG_SEQ0(CMN_REG(003d), 0x40), ++ REG_SEQ0(CMN_REG(005c), 0x25), ++ REG_SEQ0(CMN_REG(0089), 0x00), ++ REG_SEQ0(CMN_REG(0094), 0x00), ++ REG_SEQ0(CMN_REG(0097), 0x02), ++ REG_SEQ0(CMN_REG(0099), 0x04), ++}; ++ ++static const struct reg_sequence rk_hdtpx_frl_lcpll_cmn_init_seq[] = { ++ REG_SEQ0(CMN_REG(0025), 0x10), ++ REG_SEQ0(CMN_REG(0027), 0x01), ++ REG_SEQ0(CMN_REG(0028), 0x0d), ++ REG_SEQ0(CMN_REG(002e), 0x02), ++ REG_SEQ0(CMN_REG(002f), 0x0d), ++ REG_SEQ0(CMN_REG(003d), 0x00), ++ REG_SEQ0(CMN_REG(0051), 0x00), ++ REG_SEQ0(CMN_REG(0055), 0x00), ++ REG_SEQ0(CMN_REG(0059), 0x11), ++ REG_SEQ0(CMN_REG(005a), 0x03), ++ REG_SEQ0(CMN_REG(005c), 0x05), ++ REG_SEQ0(CMN_REG(005e), 0x07), ++ REG_SEQ0(CMN_REG(0060), 0x01), ++ REG_SEQ0(CMN_REG(0064), 0x07), ++ REG_SEQ0(CMN_REG(0065), 0x00), ++ REG_SEQ0(CMN_REG(0069), 0x00), ++ REG_SEQ0(CMN_REG(006c), 0x00), ++ REG_SEQ0(CMN_REG(0070), 0x01), ++ REG_SEQ0(CMN_REG(0089), 0x02), ++ REG_SEQ0(CMN_REG(0095), 0x00), ++ REG_SEQ0(CMN_REG(0097), 0x00), ++ REG_SEQ0(CMN_REG(0099), 0x00), ++}; ++ + static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = { + REG_SEQ0(SB_REG(0114), 0x00), + REG_SEQ0(SB_REG(0115), 0x00), +@@ -472,6 +564,17 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = { + REG_SEQ0(LNTOP_REG(0205), 0x1f), + }; + ++static const struct reg_sequence rk_hdtpx_frl_lntop_init_seq[] = { ++ REG_SEQ0(LNTOP_REG(0200), 0x04), ++ REG_SEQ0(LNTOP_REG(0201), 0x00), ++ REG_SEQ0(LNTOP_REG(0202), 0x00), ++ REG_SEQ0(LNTOP_REG(0203), 0xf0), ++ REG_SEQ0(LNTOP_REG(0204), 0xff), ++ REG_SEQ0(LNTOP_REG(0205), 0xff), ++ REG_SEQ0(LNTOP_REG(0206), 0x05), ++ REG_SEQ0(LNTOP_REG(0207), 0x0f), ++}; ++ + static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = { + REG_SEQ0(LANE_REG(0303), 0x0c), + REG_SEQ0(LANE_REG(0307), 0x20), +@@ -550,6 +653,40 @@ static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = { + REG_SEQ0(LANE_REG(0606), 0x1c), + }; + ++static const struct reg_sequence rk_hdtpx_frl_ropll_lane_init_seq[] = { ++ REG_SEQ0(LANE_REG(0312), 0x3c), ++ REG_SEQ0(LANE_REG(0412), 0x3c), ++ REG_SEQ0(LANE_REG(0512), 0x3c), ++ REG_SEQ0(LANE_REG(0612), 0x3c), ++}; ++ ++static const struct reg_sequence rk_hdtpx_frl_lcpll_lane_init_seq[] = { ++ REG_SEQ0(LANE_REG(0312), 0x3c), ++ REG_SEQ0(LANE_REG(0412), 0x3c), ++ REG_SEQ0(LANE_REG(0512), 0x3c), ++ REG_SEQ0(LANE_REG(0612), 0x3c), ++ REG_SEQ0(LANE_REG(0303), 0x2f), ++ REG_SEQ0(LANE_REG(0403), 0x2f), ++ REG_SEQ0(LANE_REG(0503), 0x2f), ++ REG_SEQ0(LANE_REG(0603), 0x2f), ++ REG_SEQ0(LANE_REG(0305), 0x03), ++ REG_SEQ0(LANE_REG(0405), 0x03), ++ REG_SEQ0(LANE_REG(0505), 0x03), ++ REG_SEQ0(LANE_REG(0605), 0x03), ++ REG_SEQ0(LANE_REG(0306), 0xfc), ++ REG_SEQ0(LANE_REG(0406), 0xfc), ++ REG_SEQ0(LANE_REG(0506), 0xfc), ++ REG_SEQ0(LANE_REG(0606), 0xfc), ++ REG_SEQ0(LANE_REG(0305), 0x4f), ++ REG_SEQ0(LANE_REG(0405), 0x4f), ++ REG_SEQ0(LANE_REG(0505), 0x4f), ++ REG_SEQ0(LANE_REG(0605), 0x4f), ++ REG_SEQ0(LANE_REG(0304), 0x14), ++ REG_SEQ0(LANE_REG(0404), 0x14), ++ REG_SEQ0(LANE_REG(0504), 0x14), ++ REG_SEQ0(LANE_REG(0604), 0x14), ++}; ++ + static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg) + { + switch (reg) { +@@ -651,6 +788,47 @@ static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx) + return 0; + } + ++static int rk_hdptx_post_power_up(struct rk_hdptx_phy *hdptx) ++{ ++ u32 val; ++ int ret; ++ ++ val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | ++ HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; ++ regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); ++ ++ usleep_range(10, 15); ++ reset_control_deassert(hdptx->rsts[RST_INIT].rstc); ++ ++ usleep_range(10, 15); ++ val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; ++ regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); ++ ++ usleep_range(10, 15); ++ reset_control_deassert(hdptx->rsts[RST_CMN].rstc); ++ ++ ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, ++ val & HDPTX_O_PLL_LOCK_DONE, 20, 400); ++ if (ret) { ++ dev_err(hdptx->dev, "Failed to get PHY PLL lock: %d\n", ret); ++ return ret; ++ } ++ ++ usleep_range(20, 30); ++ reset_control_deassert(hdptx->rsts[RST_LANE].rstc); ++ ++ ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, ++ val & HDPTX_O_PHY_RDY, 100, 5000); ++ if (ret) { ++ dev_err(hdptx->dev, "Failed to get PHY ready: %d\n", ret); ++ return ret; ++ } ++ ++ dev_dbg(hdptx->dev, "PHY ready\n"); ++ ++ return 0; ++} ++ + static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) + { + u32 val; +@@ -680,6 +858,99 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) + regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); + } + ++static void rk_hdptx_earc_config(struct rk_hdptx_phy *hdptx) ++{ ++ regmap_update_bits(hdptx->regmap, SB_REG(0113), SB_RX_RCAL_OPT_CODE_MASK, ++ FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 1)); ++ regmap_write(hdptx->regmap, SB_REG(011c), 0x04); ++ regmap_update_bits(hdptx->regmap, SB_REG(011b), SB_AFC_TOL_MASK, ++ FIELD_PREP(SB_AFC_TOL_MASK, 3)); ++ regmap_write(hdptx->regmap, SB_REG(0109), 0x05); ++ ++ regmap_update_bits(hdptx->regmap, SB_REG(0120), ++ SB_EARC_EN_MASK | SB_EARC_AFC_EN_MASK, ++ FIELD_PREP(SB_EARC_EN_MASK, 1) | ++ FIELD_PREP(SB_EARC_AFC_EN_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(011b), SB_EARC_SIG_DET_BYPASS_MASK, ++ FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(011f), ++ SB_PWM_AFC_CTRL_MASK | SB_RCAL_RSTN_MASK, ++ FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0xc) | ++ FIELD_PREP(SB_RCAL_RSTN_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0115), SB_READY_DELAY_TIME_MASK, ++ FIELD_PREP(SB_READY_DELAY_TIME_MASK, 2)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0113), SB_RX_RTERM_CTRL_MASK, ++ FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 3)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK, ++ FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 3)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK, ++ FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 3)); ++ ++ regmap_write(hdptx->regmap, SB_REG(011a), 0x03); ++ regmap_write(hdptx->regmap, SB_REG(0118), 0x0a); ++ regmap_write(hdptx->regmap, SB_REG(011e), 0x6a); ++ regmap_write(hdptx->regmap, SB_REG(011d), 0x67); ++ ++ regmap_update_bits(hdptx->regmap, SB_REG(0117), FAST_PULSE_TIME_MASK, ++ FIELD_PREP(FAST_PULSE_TIME_MASK, 4)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0114), ++ SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK, ++ FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 2) | ++ FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 2)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK, ++ FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 7)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK, ++ FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 7)); ++ regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK, ++ FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0110), ANA_SB_VREG_REF_SEL_MASK, ++ FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0115), SB_TG_OSC_EN_DELAY_TIME_MASK, ++ FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 2)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0116), AFC_RSTN_DELAY_TIME_MASK, ++ FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 2)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0109), ANA_SB_DMRX_AFC_DIV_RATIO_MASK, ++ FIELD_PREP(ANA_SB_DMRX_AFC_DIV_RATIO_MASK, 5)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK, ++ FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK, ++ FIELD_PREP(OVRD_SB_EN_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK, ++ FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0105), OVRD_SB_EARC_CMDC_EN_MASK, ++ FIELD_PREP(OVRD_SB_EARC_CMDC_EN_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(010f), ++ OVRD_SB_VREG_EN_MASK | OVRD_SB_VREG_LPF_BYPASS_MASK, ++ FIELD_PREP(OVRD_SB_VREG_EN_MASK, 1) | ++ FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(0123), OVRD_SB_READY_MASK, ++ FIELD_PREP(OVRD_SB_READY_MASK, 1)); ++ ++ usleep_range(1000, 1100); ++ regmap_update_bits(hdptx->regmap, SB_REG(0103), SB_RX_RESCAL_DONE_MASK, ++ FIELD_PREP(SB_RX_RESCAL_DONE_MASK, 1)); ++ usleep_range(50, 60); ++ regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK, ++ FIELD_PREP(SB_EN_MASK, 1)); ++ usleep_range(50, 60); ++ regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK, ++ FIELD_PREP(SB_RXTERM_EN_MASK, 1)); ++ usleep_range(50, 60); ++ regmap_update_bits(hdptx->regmap, SB_REG(0105), SB_EARC_CMDC_EN_MASK, ++ FIELD_PREP(SB_EARC_CMDC_EN_MASK, 1)); ++ regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK, ++ FIELD_PREP(SB_VREG_EN_MASK, 1)); ++ usleep_range(50, 60); ++ regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_LPF_BYPASS_MASK, ++ FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 1)); ++ usleep_range(250, 300); ++ regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_LPF_BYPASS_MASK, ++ FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 0)); ++ usleep_range(100, 120); ++ regmap_update_bits(hdptx->regmap, SB_REG(0123), SB_READY_MASK, ++ FIELD_PREP(SB_READY_MASK, 1)); ++} ++ + static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, + struct ropll_config *cfg) + { +@@ -755,9 +1026,13 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, + static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, + unsigned int rate) + { ++ int i, bus_width = phy_get_bus_width(hdptx->phy); ++ u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; + const struct ropll_config *cfg = NULL; + struct ropll_config rc = {0}; +- int i; ++ ++ if (color_depth) ++ rate = rate * 10 / 8; + + for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) + if (rate == ropll_tmds_cfg[i].bit_rate) { +@@ -813,6 +1088,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, + FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); + ++ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, ++ FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth)); ++ + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN, + PLL_PCG_CLK_EN); + +@@ -853,9 +1131,146 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, + rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); + ++ if (hdptx->earc_en) ++ rk_hdptx_earc_config(hdptx); ++ + return rk_hdptx_post_enable_lane(hdptx); + } + ++static int rk_hdptx_ropll_frl_mode_config(struct rk_hdptx_phy *hdptx, ++ u32 bus_width) ++{ ++ u32 bit_rate = bus_width & DATA_RATE_MASK; ++ u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; ++ const struct ropll_config *cfg = NULL; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(ropll_frl_cfg); i++) ++ if (bit_rate == ropll_frl_cfg[i].bit_rate) { ++ cfg = &ropll_frl_cfg[i]; ++ break; ++ } ++ ++ if (!cfg) { ++ dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__); ++ return -EINVAL; ++ } ++ ++ rk_hdptx_pre_power_up(hdptx); ++ ++ reset_control_assert(hdptx->rsts[RST_ROPLL].rstc); ++ usleep_range(10, 20); ++ reset_control_deassert(hdptx->rsts[RST_ROPLL].rstc); ++ ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_cmn_init_seq); ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_ropll_cmn_init_seq); ++ ++ regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); ++ regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); ++ regmap_write(hdptx->regmap, CMN_REG(0059), ++ (cfg->pms_pdiv << 4) | cfg->pms_refdiv); ++ regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4); ++ ++ regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, ++ FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); ++ if (!cfg->sdm_en) ++ regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0); ++ ++ regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK, ++ FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign)); ++ ++ regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno); ++ regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num); ++ ++ regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, ++ FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n)); ++ ++ regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num); ++ regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno); ++ ++ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, ++ FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); ++ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, ++ FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth)); ++ ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lntop_init_seq); ++ ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_ropll_lane_init_seq); ++ ++ if (hdptx->earc_en) ++ rk_hdptx_earc_config(hdptx); ++ ++ return rk_hdptx_post_power_up(hdptx); ++} ++ ++static int rk_hdptx_lcpll_frl_mode_config(struct rk_hdptx_phy *hdptx, ++ u32 bus_width) ++{ ++ u32 bit_rate = bus_width & DATA_RATE_MASK; ++ u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0; ++ const struct lcpll_config *cfg = NULL; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(lcpll_cfg); i++) ++ if (bit_rate == lcpll_cfg[i].bit_rate) { ++ cfg = &lcpll_cfg[i]; ++ break; ++ } ++ ++ if (!cfg) { ++ dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__); ++ return -EINVAL; ++ } ++ ++ rk_hdptx_pre_power_up(hdptx); ++ ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_cmn_init_seq); ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lcpll_cmn_init_seq); ++ ++ regmap_update_bits(hdptx->regmap, CMN_REG(0008), ++ LCPLL_EN_MASK | LCPLL_LCVCO_MODE_EN_MASK, ++ FIELD_PREP(LCPLL_EN_MASK, 1) | ++ FIELD_PREP(LCPLL_LCVCO_MODE_EN_MASK, cfg->lcvco_mode_en)); ++ ++ regmap_update_bits(hdptx->regmap, CMN_REG(001e), ++ LCPLL_PI_EN_MASK | LCPLL_100M_CLK_EN_MASK, ++ FIELD_PREP(LCPLL_PI_EN_MASK, cfg->pi_en) | ++ FIELD_PREP(LCPLL_100M_CLK_EN_MASK, cfg->clk_en_100m)); ++ ++ regmap_write(hdptx->regmap, CMN_REG(0020), cfg->pms_mdiv); ++ regmap_write(hdptx->regmap, CMN_REG(0021), cfg->pms_mdiv_afc); ++ regmap_write(hdptx->regmap, CMN_REG(0022), ++ (cfg->pms_pdiv << 4) | cfg->pms_refdiv); ++ regmap_write(hdptx->regmap, CMN_REG(0023), ++ (cfg->pms_sdiv << 4) | cfg->pms_sdiv); ++ regmap_write(hdptx->regmap, CMN_REG(002a), cfg->sdm_deno); ++ regmap_write(hdptx->regmap, CMN_REG(002b), cfg->sdm_num_sign); ++ regmap_write(hdptx->regmap, CMN_REG(002c), cfg->sdm_num); ++ ++ regmap_update_bits(hdptx->regmap, CMN_REG(002d), LCPLL_SDC_N_MASK, ++ FIELD_PREP(LCPLL_SDC_N_MASK, cfg->sdc_n)); ++ ++ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, ++ FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); ++ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, ++ FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth)); ++ ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lntop_init_seq); ++ ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); ++ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lcpll_lane_init_seq); ++ ++ if (hdptx->earc_en) ++ rk_hdptx_earc_config(hdptx); ++ ++ return rk_hdptx_post_power_up(hdptx); ++} ++ + static int rk_hdptx_phy_power_on(struct phy *phy) + { + struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); +@@ -865,7 +1280,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) + * from the HDMI bridge driver until phy_configure_opts_hdmi + * becomes available in the PHY API. + */ +- unsigned int rate = bus_width & 0xfffffff; ++ unsigned int rate = bus_width & DATA_RATE_MASK; + + dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n", + __func__, bus_width, rate); +@@ -876,7 +1291,20 @@ static int rk_hdptx_phy_power_on(struct phy *phy) + return ret; + } + +- ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); ++ if (bus_width & HDMI_EARC_MASK) ++ hdptx->earc_en = true; ++ else ++ hdptx->earc_en = false; ++ ++ if (bus_width & HDMI_MODE_MASK) { ++ if (rate > 24000000) ++ ret = rk_hdptx_lcpll_frl_mode_config(hdptx, bus_width); ++ else ++ ret = rk_hdptx_ropll_frl_mode_config(hdptx, bus_width); ++ } else { ++ ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); ++ } ++ + if (ret) + pm_runtime_put(hdptx->dev); + +-- +Armbian + diff --git a/kernel.patches/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch b/kernel.patches/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch new file mode 100644 index 0000000..43173de --- /dev/null +++ b/kernel.patches/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch @@ -0,0 +1,222 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Tue, 16 Jan 2024 19:27:40 +0200 +Subject: phy: phy-rockchip-samsung-hdptx: Add clock provider + +The HDMI PHY PLL can be used as an alternative dclk source to SoC CRU. +It provides more accurate clock rates required to properly support +various display modes, e.g. those relying on non-integer refresh rates. + +Also note this only works for HDMI 2.0 or bellow, e.g. cannot be used to +support HDMI 2.1 4K@120Hz mode. + +Signed-off-by: Cristian Ciocaltea +--- + drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 148 +++++++++- + 1 file changed, 143 insertions(+), 5 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +index 111111111111..222222222222 100644 +--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c ++++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +@@ -8,6 +8,7 @@ + */ + #include + #include ++#include + #include + #include + #include +@@ -279,6 +280,12 @@ struct rk_hdptx_phy { + int nr_clks; + struct reset_control_bulk_data rsts[RST_MAX]; + bool earc_en; ++ ++ /* clk provider */ ++ struct clk_hw hw; ++ unsigned long rate; ++ int id; ++ int count; + }; + + static const struct lcpll_config lcpll_cfg[] = { +@@ -1031,6 +1038,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, + const struct ropll_config *cfg = NULL; + struct ropll_config rc = {0}; + ++ hdptx->rate = rate * 100; ++ + if (color_depth) + rate = rate * 10 / 8; + +@@ -1315,11 +1324,13 @@ static int rk_hdptx_phy_power_off(struct phy *phy) + { + struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); + u32 val; +- int ret; ++ int ret = 0; + +- ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); +- if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) +- rk_hdptx_phy_disable(hdptx); ++ if (hdptx->count == 0) { ++ ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); ++ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) ++ rk_hdptx_phy_disable(hdptx); ++ } + + pm_runtime_put(hdptx->dev); + +@@ -1332,6 +1343,129 @@ static const struct phy_ops rk_hdptx_phy_ops = { + .owner = THIS_MODULE, + }; + ++static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw) ++{ ++ return container_of(hw, struct rk_hdptx_phy, hw); ++} ++ ++static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) ++{ ++ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); ++ int ret; ++ ++ ret = pm_runtime_resume_and_get(hdptx->dev); ++ if (ret) { ++ dev_err(hdptx->dev, "Failed to resume phy clk: %d\n", ret); ++ return ret; ++ } ++ ++ if (!hdptx->count && hdptx->rate) { ++ ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, hdptx->rate / 100); ++ if (ret < 0) { ++ dev_err(hdptx->dev, "Failed to init PHY PLL: %d\n", ret); ++ pm_runtime_put(hdptx->dev); ++ return ret; ++ } ++ } ++ ++ hdptx->count++; ++ ++ return 0; ++} ++ ++static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) ++{ ++ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); ++ ++ if (hdptx->count == 1) { ++ u32 val; ++ int ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); ++ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) ++ rk_hdptx_phy_disable(hdptx); ++ } ++ ++ hdptx->count--; ++ pm_runtime_put(hdptx->dev); ++} ++ ++static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); ++ ++ return hdptx->rate; ++} ++ ++static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ const struct ropll_config *cfg = NULL; ++ u32 bit_rate = rate / 100; ++ int i; ++ ++ if (rate > HDMI20_MAX_RATE) ++ return rate; ++ ++ for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) ++ if (bit_rate == ropll_tmds_cfg[i].bit_rate) { ++ cfg = &ropll_tmds_cfg[i]; ++ break; ++ } ++ ++ if (!cfg && !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) ++ return -EINVAL; ++ ++ return rate; ++} ++ ++static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); ++ u32 val; ++ int ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); ++ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) ++ rk_hdptx_phy_disable(hdptx); ++ ++ return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); ++} ++ ++static const struct clk_ops hdptx_phy_clk_ops = { ++ .prepare = rk_hdptx_phy_clk_prepare, ++ .unprepare = rk_hdptx_phy_clk_unprepare, ++ .recalc_rate = rk_hdptx_phy_clk_recalc_rate, ++ .round_rate = rk_hdptx_phy_clk_round_rate, ++ .set_rate = rk_hdptx_phy_clk_set_rate, ++}; ++ ++static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx) ++{ ++ struct device *dev = hdptx->dev; ++ const char *name, *pname; ++ struct clk *refclk; ++ int ret; ++ ++ refclk = devm_clk_get(dev, "ref"); ++ if (IS_ERR(refclk)) ++ return dev_err_probe(dev, PTR_ERR(refclk), ++ "Failed to get ref clock\n"); ++ ++ pname = __clk_get_name(refclk); ++ name = hdptx->id ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0"; ++ hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops, ++ CLK_GET_RATE_NOCACHE); ++ ++ ret = devm_clk_hw_register(dev, &hdptx->hw); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to register clock\n"); ++ ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "Failed to register clk provider\n"); ++ return 0; ++} ++ + static int rk_hdptx_phy_runtime_suspend(struct device *dev) + { + struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); +@@ -1367,6 +1501,10 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev) + + hdptx->dev = dev; + ++ hdptx->id = of_alias_get_id(dev->of_node, "hdptxphy"); ++ if (hdptx->id < 0) ++ hdptx->id = 0; ++ + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return dev_err_probe(dev, PTR_ERR(regs), +@@ -1426,7 +1564,7 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev) + reset_control_deassert(hdptx->rsts[RST_CMN].rstc); + reset_control_deassert(hdptx->rsts[RST_INIT].rstc); + +- return 0; ++ return rk_hdptx_phy_clk_register(hdptx); + } + + static const struct dev_pm_ops rk_hdptx_phy_pm_ops = { +-- +Armbian + diff --git a/kernel.patches/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch b/kernel.patches/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch new file mode 100644 index 0000000..ca6f5d4 --- /dev/null +++ b/kernel.patches/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch @@ -0,0 +1,679 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Fri, 3 Nov 2023 19:58:02 +0200 +Subject: drm/rockchip: vop2: Improve display modes handling on rk3588 + +The initial vop2 support for rk3588 in mainline is not able to handle +all display modes supported by connected displays, e.g. +2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. + +Additionally, it doesn't cope with non-integer refresh rates like 59.94, +29.97, 23.98, etc. + +Improve HDMI0 clocking in order to support the additional display modes. + +Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588") +Signed-off-by: Cristian Ciocaltea +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 553 +++++++++- + 1 file changed, 552 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +@@ -5,6 +5,8 @@ + */ + #include + #include ++#include ++#include + #include + #include + #include +@@ -212,6 +214,10 @@ struct vop2 { + struct clk *hclk; + struct clk *aclk; + struct clk *pclk; ++ // [CC:] hack to support additional display modes ++ struct clk *hdmi0_phy_pll; ++ /* list_head of internal clk */ ++ struct list_head clk_list_head; + + /* optional internal rgb encoder */ + struct rockchip_rgb *rgb; +@@ -220,6 +226,19 @@ struct vop2 { + struct vop2_win win[]; + }; + ++struct vop2_clk { ++ struct vop2 *vop2; ++ struct list_head list; ++ unsigned long rate; ++ struct clk_hw hw; ++ struct clk_divider div; ++ int div_val; ++ u8 parent_index; ++}; ++ ++#define to_vop2_clk(_hw) container_of(_hw, struct vop2_clk, hw) ++#define VOP2_MAX_DCLK_RATE 600000 /* kHz */ ++ + #define vop2_output_if_is_hdmi(x) ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \ + (x) == ROCKCHIP_VOP2_EP_HDMI1) + +@@ -1476,9 +1495,30 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) + { ++ struct vop2_video_port *vp = to_vop2_video_port(crtc); ++ struct drm_connector *connector; ++ struct drm_connector_list_iter conn_iter; ++ struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode); + drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | + CRTC_STEREO_DOUBLE); + ++ if (mode->flags & DRM_MODE_FLAG_DBLCLK) ++ adj_mode->crtc_clock *= 2; ++ ++ drm_connector_list_iter_begin(crtc->dev, &conn_iter); ++ drm_for_each_connector_iter(connector, &conn_iter) { ++ if ((new_crtc_state->connector_mask & drm_connector_mask(connector)) && ++ ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || ++ (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))) { ++ drm_connector_list_iter_end(&conn_iter); ++ return true; ++ } ++ } ++ drm_connector_list_iter_end(&conn_iter); ++ ++ if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE) ++ adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk, ++ adj_mode->crtc_clock * 1000), 1000); + return true; + } + +@@ -1663,6 +1703,31 @@ static unsigned long rk3588_calc_dclk(unsigned long child_clk, unsigned long max + return 0; + } + ++static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name); ++ ++static int vop2_cru_set_rate(struct vop2_clk *if_pixclk, struct vop2_clk *if_dclk) ++{ ++ int ret = 0; ++ ++ if (if_pixclk) { ++ ret = clk_set_rate(if_pixclk->hw.clk, if_pixclk->rate); ++ if (ret < 0) { ++ DRM_DEV_ERROR(if_pixclk->vop2->dev, "set %s to %ld failed: %d\n", ++ clk_hw_get_name(&if_pixclk->hw), if_pixclk->rate, ret); ++ return ret; ++ } ++ } ++ ++ if (if_dclk) { ++ ret = clk_set_rate(if_dclk->hw.clk, if_dclk->rate); ++ if (ret < 0) ++ DRM_DEV_ERROR(if_dclk->vop2->dev, "set %s to %ld failed %d\n", ++ clk_hw_get_name(&if_dclk->hw), if_dclk->rate, ret); ++ } ++ ++ return ret; ++} ++ + /* + * 4 pixclk/cycle on rk3588 + * RGB/eDP/HDMI: if_pixclk >= dclk_core +@@ -1686,6 +1751,72 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id, + int K = 1; + + if (vop2_output_if_is_hdmi(id)) { ++ if (vop2->data->soc_id == 3588 && id == ROCKCHIP_VOP2_EP_HDMI0 && ++ vop2->hdmi0_phy_pll) { ++ const char *clk_src_name = "hdmi_edp0_clk_src"; ++ const char *clk_parent_name = "dclk"; ++ const char *pixclk_name = "hdmi_edp0_pixclk"; ++ const char *dclk_name = "hdmi_edp0_dclk"; ++ struct vop2_clk *if_clk_src, *if_clk_parent, *if_pixclk, *if_dclk, *dclk, *dclk_core, *dclk_out; ++ char clk_name[32]; ++ int ret; ++ ++ if_clk_src = vop2_clk_get(vop2, clk_src_name); ++ snprintf(clk_name, sizeof(clk_name), "%s%d", clk_parent_name, vp->id); ++ if_clk_parent = vop2_clk_get(vop2, clk_name); ++ if_pixclk = vop2_clk_get(vop2, pixclk_name); ++ if_dclk = vop2_clk_get(vop2, dclk_name); ++ if (!if_pixclk || !if_clk_parent) { ++ DRM_DEV_ERROR(vop2->dev, "failed to get connector interface clk\n"); ++ return -ENODEV; ++ } ++ ++ ret = clk_set_parent(if_clk_src->hw.clk, if_clk_parent->hw.clk); ++ if (ret < 0) { ++ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n", ++ __clk_get_name(if_clk_parent->hw.clk), ++ __clk_get_name(if_clk_src->hw.clk), ret); ++ return ret; ++ } ++ ++ if (output_mode == ROCKCHIP_OUT_MODE_YUV420) ++ K = 2; ++ ++ if_pixclk->rate = (dclk_core_rate << 1) / K; ++ if_dclk->rate = dclk_core_rate / K; ++ ++ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id); ++ dclk_core = vop2_clk_get(vop2, clk_name); ++ ++ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id); ++ dclk_out = vop2_clk_get(vop2, clk_name); ++ ++ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id); ++ dclk = vop2_clk_get(vop2, clk_name); ++ if (v_pixclk <= (VOP2_MAX_DCLK_RATE * 1000)) { ++ if (output_mode == ROCKCHIP_OUT_MODE_YUV420) ++ v_pixclk = v_pixclk >> 1; ++ } else { ++ v_pixclk = v_pixclk >> 2; ++ } ++ clk_set_rate(dclk->hw.clk, v_pixclk); ++ ++ if (dclk_core_rate > if_pixclk->rate) { ++ clk_set_rate(dclk_core->hw.clk, dclk_core_rate); ++ ret = vop2_cru_set_rate(if_pixclk, if_dclk); ++ } else { ++ ret = vop2_cru_set_rate(if_pixclk, if_dclk); ++ clk_set_rate(dclk_core->hw.clk, dclk_core_rate); ++ } ++ ++ *dclk_core_div = dclk_core->div_val; ++ *dclk_out_div = dclk_out->div_val; ++ *if_pixclk_div = if_pixclk->div_val; ++ *if_dclk_div = if_dclk->div_val; ++ ++ return dclk->rate; ++ } ++ + /* + * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate + * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate +@@ -1917,6 +2048,22 @@ static int us_to_vertical_line(struct drm_display_mode *mode, int us) + return us * mode->clock / mode->htotal / 1000; + } + ++// [CC:] rework virtual clock ++static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name) ++{ ++ struct vop2_clk *clk, *n; ++ ++ if (!name) ++ return NULL; ++ ++ list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) { ++ if (!strcmp(clk_hw_get_name(&clk->hw), name)) ++ return clk; ++ } ++ ++ return NULL; ++} ++ + static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_state *state) + { +@@ -1944,6 +2091,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, + u32 val, polflags; + int ret; + struct drm_encoder *encoder; ++ char clk_name[32]; ++ struct vop2_clk *dclk; + + drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", + hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", +@@ -2044,11 +2193,38 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, + + if (mode->flags & DRM_MODE_FLAG_DBLCLK) { + dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; +- clock *= 2; ++ // [CC:] done via mode_fixup ++ // clock *= 2; + } + + vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); + ++ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id); ++ dclk = vop2_clk_get(vop2, clk_name); ++ if (dclk) { ++ /* ++ * use HDMI_PHY_PLL as dclk source under 4K@60 if it is available, ++ * otherwise use system cru as dclk source. ++ */ ++ drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { ++ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); ++ ++ // [CC:] Using PHY PLL to handle all display modes ++ if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { ++ clk_get_rate(vop2->hdmi0_phy_pll); ++ ++ if (mode->crtc_clock <= VOP2_MAX_DCLK_RATE) { ++ ret = clk_set_parent(vp->dclk, vop2->hdmi0_phy_pll); ++ if (ret < 0) ++ DRM_WARN("failed to set clock parent for %s\n", ++ __clk_get_name(vp->dclk)); ++ } ++ ++ clock = dclk->rate; ++ } ++ } ++ } ++ + clk_set_rate(vp->dclk, clock); + + vop2_post_config(crtc); +@@ -2504,7 +2680,43 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, + spin_unlock_irq(&crtc->dev->event_lock); + } + ++static enum drm_mode_status ++vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) ++{ ++ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); ++ struct vop2_video_port *vp = to_vop2_video_port(crtc); ++ struct vop2 *vop2 = vp->vop2; ++ const struct vop2_data *vop2_data = vop2->data; ++ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; ++ int request_clock = mode->clock; ++ int clock; ++ ++ if (mode->hdisplay > vp_data->max_output.width) ++ return MODE_BAD_HVALUE; ++ ++ if (mode->flags & DRM_MODE_FLAG_DBLCLK) ++ request_clock *= 2; ++ ++ if (request_clock <= VOP2_MAX_DCLK_RATE) { ++ clock = request_clock; ++ } else { ++ request_clock = request_clock >> 2; ++ clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000; ++ } ++ ++ /* ++ * Hdmi or DisplayPort request a Accurate clock. ++ */ ++ if (vcstate->output_type == DRM_MODE_CONNECTOR_HDMIA || ++ vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort) ++ if (clock != request_clock) ++ return MODE_CLOCK_RANGE; ++ ++ return MODE_OK; ++} ++ + static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { ++ .mode_valid = vop2_crtc_mode_valid, + .mode_fixup = vop2_crtc_mode_fixup, + .atomic_check = vop2_crtc_atomic_check, + .atomic_begin = vop2_crtc_atomic_begin, +@@ -3074,6 +3286,336 @@ static const struct regmap_config vop2_regmap_config = { + .cache_type = REGCACHE_MAPLE, + }; + ++/* ++ * BEGIN virtual clock ++ */ ++#define PLL_RATE_MIN 30000000 ++ ++#define cru_dbg(format, ...) do { \ ++ if (cru_debug) \ ++ pr_info("%s: " format, __func__, ## __VA_ARGS__); \ ++ } while (0) ++ ++#define PNAME(x) static const char *const x[] ++ ++enum vop_clk_branch_type { ++ branch_mux, ++ branch_divider, ++ branch_factor, ++ branch_virtual, ++}; ++ ++#define VIR(cname) \ ++ { \ ++ .branch_type = branch_virtual, \ ++ .name = cname, \ ++ } ++ ++ ++#define MUX(cname, pnames, f) \ ++ { \ ++ .branch_type = branch_mux, \ ++ .name = cname, \ ++ .parent_names = pnames, \ ++ .num_parents = ARRAY_SIZE(pnames), \ ++ .flags = f, \ ++ } ++ ++#define FACTOR(cname, pname, f) \ ++ { \ ++ .branch_type = branch_factor, \ ++ .name = cname, \ ++ .parent_names = (const char *[]){ pname }, \ ++ .num_parents = 1, \ ++ .flags = f, \ ++ } ++ ++#define DIV(cname, pname, f, w) \ ++ { \ ++ .branch_type = branch_divider, \ ++ .name = cname, \ ++ .parent_names = (const char *[]){ pname }, \ ++ .num_parents = 1, \ ++ .flags = f, \ ++ .div_width = w, \ ++ } ++ ++struct vop2_clk_branch { ++ enum vop_clk_branch_type branch_type; ++ const char *name; ++ const char *const *parent_names; ++ u8 num_parents; ++ unsigned long flags; ++ u8 div_shift; ++ u8 div_width; ++ u8 div_flags; ++}; ++ ++PNAME(mux_port0_dclk_src_p) = { "dclk0", "dclk1" }; ++PNAME(mux_port2_dclk_src_p) = { "dclk2", "dclk1" }; ++PNAME(mux_dp_pixclk_p) = { "dclk_out0", "dclk_out1", "dclk_out2" }; ++PNAME(mux_hdmi_edp_clk_src_p) = { "dclk0", "dclk1", "dclk2" }; ++PNAME(mux_mipi_clk_src_p) = { "dclk_out1", "dclk_out2", "dclk_out3" }; ++PNAME(mux_dsc_8k_clk_src_p) = { "dclk0", "dclk1", "dclk2", "dclk3" }; ++PNAME(mux_dsc_4k_clk_src_p) = { "dclk0", "dclk1", "dclk2", "dclk3" }; ++ ++/* ++ * We only use this clk driver calculate the div ++ * of dclk_core/dclk_out/if_pixclk/if_dclk and ++ * the rate of the dclk from the soc. ++ * ++ * We don't touch the cru in the vop here, as ++ * these registers has special read andy write ++ * limits. ++ */ ++static struct vop2_clk_branch rk3588_vop_clk_branches[] = { ++ VIR("dclk0"), ++ VIR("dclk1"), ++ VIR("dclk2"), ++ VIR("dclk3"), ++ ++ MUX("port0_dclk_src", mux_port0_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2), ++ DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2), ++ ++ FACTOR("port1_dclk_src", "dclk1", CLK_SET_RATE_PARENT), ++ DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2), ++ DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2), ++ ++ MUX("port2_dclk_src", mux_port2_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2), ++ DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2), ++ ++ FACTOR("port3_dclk_src", "dclk3", CLK_SET_RATE_PARENT), ++ DIV("dclk_core3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2), ++ DIV("dclk_out3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2), ++ ++ MUX("dp0_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ MUX("dp1_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ ++ MUX("hdmi_edp0_clk_src", mux_hdmi_edp_clk_src_p, ++ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ DIV("hdmi_edp0_dclk", "hdmi_edp0_clk_src", 0, 2), ++ DIV("hdmi_edp0_pixclk", "hdmi_edp0_clk_src", CLK_SET_RATE_PARENT, 1), ++ ++ MUX("hdmi_edp1_clk_src", mux_hdmi_edp_clk_src_p, ++ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ DIV("hdmi_edp1_dclk", "hdmi_edp1_clk_src", 0, 2), ++ DIV("hdmi_edp1_pixclk", "hdmi_edp1_clk_src", CLK_SET_RATE_PARENT, 1), ++ ++ MUX("mipi0_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ DIV("mipi0_pixclk", "mipi0_clk_src", CLK_SET_RATE_PARENT, 2), ++ ++ MUX("mipi1_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ DIV("mipi1_pixclk", "mipi1_clk_src", CLK_SET_RATE_PARENT, 2), ++ ++ FACTOR("rgb_pixclk", "port3_dclk_src", CLK_SET_RATE_PARENT), ++ ++ MUX("dsc_8k_txp_clk_src", mux_dsc_8k_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ DIV("dsc_8k_txp_clk", "dsc_8k_txp_clk_src", 0, 2), ++ DIV("dsc_8k_pxl_clk", "dsc_8k_txp_clk_src", 0, 2), ++ DIV("dsc_8k_cds_clk", "dsc_8k_txp_clk_src", 0, 2), ++ ++ MUX("dsc_4k_txp_clk_src", mux_dsc_4k_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), ++ DIV("dsc_4k_txp_clk", "dsc_4k_txp_clk_src", 0, 2), ++ DIV("dsc_4k_pxl_clk", "dsc_4k_txp_clk_src", 0, 2), ++ DIV("dsc_4k_cds_clk", "dsc_4k_txp_clk_src", 0, 2), ++}; ++ ++static unsigned long clk_virtual_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct vop2_clk *vop2_clk = to_vop2_clk(hw); ++ ++ return (unsigned long)vop2_clk->rate; ++} ++ ++static long clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *prate) ++{ ++ struct vop2_clk *vop2_clk = to_vop2_clk(hw); ++ ++ vop2_clk->rate = rate; ++ ++ return rate; ++} ++ ++static int clk_virtual_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ return 0; ++} ++ ++const struct clk_ops clk_virtual_ops = { ++ .round_rate = clk_virtual_round_rate, ++ .set_rate = clk_virtual_set_rate, ++ .recalc_rate = clk_virtual_recalc_rate, ++}; ++ ++static u8 vop2_mux_get_parent(struct clk_hw *hw) ++{ ++ struct vop2_clk *vop2_clk = to_vop2_clk(hw); ++ ++ // cru_dbg("%s index: %d\n", clk_hw_get_name(hw), vop2_clk->parent_index); ++ return vop2_clk->parent_index; ++} ++ ++static int vop2_mux_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct vop2_clk *vop2_clk = to_vop2_clk(hw); ++ ++ vop2_clk->parent_index = index; ++ ++ // cru_dbg("%s index: %d\n", clk_hw_get_name(hw), index); ++ return 0; ++} ++ ++static int vop2_clk_mux_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ // cru_dbg("%s %ld(min: %ld max: %ld)\n", ++ // clk_hw_get_name(hw), req->rate, req->min_rate, req->max_rate); ++ return __clk_mux_determine_rate(hw, req); ++} ++ ++static const struct clk_ops vop2_mux_clk_ops = { ++ .get_parent = vop2_mux_get_parent, ++ .set_parent = vop2_mux_set_parent, ++ .determine_rate = vop2_clk_mux_determine_rate, ++}; ++ ++#define div_mask(width) ((1 << (width)) - 1) ++ ++static int vop2_div_get_val(unsigned long rate, unsigned long parent_rate) ++{ ++ unsigned int div, value; ++ ++ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); ++ ++ value = ilog2(div); ++ ++ return value; ++} ++ ++static unsigned long vop2_clk_div_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct vop2_clk *vop2_clk = to_vop2_clk(hw); ++ unsigned long rate; ++ unsigned int div; ++ ++ div = 1 << vop2_clk->div_val; ++ rate = parent_rate / div; ++ ++ // cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, parent_rate); ++ return rate; ++} ++ ++static long vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *prate) ++{ ++ struct vop2_clk *vop2_clk = to_vop2_clk(hw); ++ ++ if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { ++ if (*prate < rate) ++ *prate = rate; ++ if ((*prate >> vop2_clk->div.width) > rate) ++ *prate = rate; ++ ++ if ((*prate % rate)) ++ *prate = rate; ++ ++ /* SOC PLL can't output a too low pll freq */ ++ if (*prate < PLL_RATE_MIN) ++ *prate = rate << vop2_clk->div.width; ++ } ++ ++ // cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, *prate); ++ return rate; ++} ++ ++static int vop2_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) ++{ ++ struct vop2_clk *vop2_clk = to_vop2_clk(hw); ++ int div_val; ++ ++ div_val = vop2_div_get_val(rate, parent_rate); ++ vop2_clk->div_val = div_val; ++ ++ // cru_dbg("%s prate: %ld rate: %ld div_val: %d\n", ++ // clk_hw_get_name(hw), parent_rate, rate, div_val); ++ return 0; ++} ++ ++static const struct clk_ops vop2_div_clk_ops = { ++ .recalc_rate = vop2_clk_div_recalc_rate, ++ .round_rate = vop2_clk_div_round_rate, ++ .set_rate = vop2_clk_div_set_rate, ++}; ++ ++static struct clk *vop2_clk_register(struct vop2 *vop2, struct vop2_clk_branch *branch) ++{ ++ struct clk_init_data init = {}; ++ struct vop2_clk *vop2_clk; ++ struct clk *clk; ++ ++ vop2_clk = devm_kzalloc(vop2->dev, sizeof(*vop2_clk), GFP_KERNEL); ++ if (!vop2_clk) ++ return ERR_PTR(-ENOMEM); ++ ++ vop2_clk->vop2 = vop2; ++ vop2_clk->hw.init = &init; ++ vop2_clk->div.shift = branch->div_shift; ++ vop2_clk->div.width = branch->div_width; ++ ++ init.name = branch->name; ++ init.flags = branch->flags; ++ init.num_parents = branch->num_parents; ++ init.parent_names = branch->parent_names; ++ if (branch->branch_type == branch_divider) { ++ init.ops = &vop2_div_clk_ops; ++ } else if (branch->branch_type == branch_virtual) { ++ init.ops = &clk_virtual_ops; ++ init.num_parents = 0; ++ init.parent_names = NULL; ++ } else { ++ init.ops = &vop2_mux_clk_ops; ++ } ++ ++ clk = devm_clk_register(vop2->dev, &vop2_clk->hw); ++ if (!IS_ERR(clk)) ++ list_add_tail(&vop2_clk->list, &vop2->clk_list_head); ++ else ++ DRM_DEV_ERROR(vop2->dev, "Register %s failed\n", branch->name); ++ ++ return clk; ++} ++ ++static int vop2_clk_init(struct vop2 *vop2) ++{ ++ struct vop2_clk_branch *branch = rk3588_vop_clk_branches; ++ unsigned int nr_clk = ARRAY_SIZE(rk3588_vop_clk_branches); ++ unsigned int idx; ++ struct vop2_clk *clk, *n; ++ ++ INIT_LIST_HEAD(&vop2->clk_list_head); ++ ++ if (vop2->data->soc_id < 3588 || vop2->hdmi0_phy_pll == NULL) ++ return 0; ++ ++ list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) { ++ list_del(&clk->list); ++ } ++ ++ for (idx = 0; idx < nr_clk; idx++, branch++) ++ vop2_clk_register(vop2, branch); ++ ++ return 0; ++} ++/* ++ * END virtual clock ++ */ ++ + static int vop2_bind(struct device *dev, struct device *master, void *data) + { + struct platform_device *pdev = to_platform_device(dev); +@@ -3167,6 +3709,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) + return PTR_ERR(vop2->pclk); + } + ++ vop2->hdmi0_phy_pll = devm_clk_get_optional(vop2->drm->dev, "hdmi0_phy_pll"); ++ if (IS_ERR(vop2->hdmi0_phy_pll)) { ++ DRM_DEV_ERROR(vop2->dev, "failed to get hdmi0_phy_pll source\n"); ++ return PTR_ERR(vop2->hdmi0_phy_pll); ++ } ++ + vop2->irq = platform_get_irq(pdev, 0); + if (vop2->irq < 0) { + drm_err(vop2->drm, "cannot find irq for vop2\n"); +@@ -3183,6 +3731,9 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) + if (ret) + return ret; + ++ // [CC:] rework virtual clock ++ vop2_clk_init(vop2); ++ + ret = vop2_find_rgb_encoder(vop2); + if (ret >= 0) { + vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc, +-- +Armbian + diff --git a/kernel.patches/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch b/kernel.patches/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch new file mode 100644 index 0000000..e2b7486 --- /dev/null +++ b/kernel.patches/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch @@ -0,0 +1,34 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Mon, 13 May 2024 20:29:49 +0300 +Subject: arm64: dts: rockchip: rk3588: add VDPU and RGA2 nodes + +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 ++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -726,6 +726,17 @@ mmu600_php: iommu@fcb00000 { + status = "disabled"; + }; + ++ rga: rga@fdb80000 { ++ compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; ++ reg = <0x0 0xfdb80000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; ++ clock-names = "aclk", "hclk", "sclk"; ++ resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; ++ reset-names = "core", "axi", "ahb"; ++ power-domains = <&power RK3588_PD_VDPU>; ++ }; ++ + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; +-- +Armbian + diff --git a/kernel.patches/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch b/kernel.patches/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch new file mode 100644 index 0000000..c4994f7 --- /dev/null +++ b/kernel.patches/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch @@ -0,0 +1,6616 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Wed, 1 Nov 2023 18:50:38 +0200 +Subject: [WIP] drm/bridge: synopsys: Add initial support for DW HDMI QP TX + Controller + +Co-developed-by: Algea Cao +Signed-off-by: Algea Cao +Signed-off-by: Cristian Ciocaltea +--- + drivers/gpu/drm/bridge/synopsys/Makefile | 2 +- + drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 2401 ++++++++ + drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h | 831 +++ + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 89 + + drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 4 + + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2740 +++++++++- + include/drm/bridge/dw_hdmi.h | 101 + + 7 files changed, 6102 insertions(+), 66 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/bridge/synopsys/Makefile ++++ b/drivers/gpu/drm/bridge/synopsys/Makefile +@@ -1,5 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o ++obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o dw-hdmi-qp.o + obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o + obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o + obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +@@ -0,0 +1,2401 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) Rockchip Electronics Co.Ltd ++ * Author: ++ * Algea Cao ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "dw-hdmi-qp.h" ++ ++#define DDC_CI_ADDR 0x37 ++#define DDC_SEGMENT_ADDR 0x30 ++ ++#define HDMI_EDID_LEN 512 ++ ++/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ ++#define SCDC_MIN_SOURCE_VERSION 0x1 ++ ++#define HDMI14_MAX_TMDSCLK 340000000 ++#define HDMI20_MAX_TMDSCLK_KHZ 600000 ++ ++static const unsigned int dw_hdmi_cable[] = { ++ EXTCON_DISP_HDMI, ++ EXTCON_NONE, ++}; ++ ++static const struct drm_display_mode dw_hdmi_default_modes[] = { ++ /* 16 - 1920x1080@60Hz 16:9 */ ++ { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, ++ 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), ++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, ++ /* 2 - 720x480@60Hz 4:3 */ ++ { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, ++ 798, 858, 0, 480, 489, 495, 525, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), ++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, ++ /* 4 - 1280x720@60Hz 16:9 */ ++ { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, ++ 1430, 1650, 0, 720, 725, 730, 750, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), ++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, ++ /* 31 - 1920x1080@50Hz 16:9 */ ++ { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, ++ 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), ++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, ++ /* 19 - 1280x720@50Hz 16:9 */ ++ { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, ++ 1760, 1980, 0, 720, 725, 730, 750, 0, ++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), ++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, ++ /* 17 - 720x576@50Hz 4:3 */ ++ { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, ++ 796, 864, 0, 576, 581, 586, 625, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), ++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, ++ /* 2 - 720x480@60Hz 4:3 */ ++ { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, ++ 798, 858, 0, 480, 489, 495, 525, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), ++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, ++}; ++ ++enum frl_mask { ++ FRL_3GBPS_3LANE = 1, ++ FRL_6GBPS_3LANE, ++ FRL_6GBPS_4LANE, ++ FRL_8GBPS_4LANE, ++ FRL_10GBPS_4LANE, ++ FRL_12GBPS_4LANE, ++}; ++ ++struct hdmi_vmode_qp { ++ bool mdataenablepolarity; ++ ++ unsigned int previous_pixelclock; ++ unsigned long mpixelclock; ++ unsigned int mpixelrepetitioninput; ++ unsigned int mpixelrepetitionoutput; ++ unsigned long previous_tmdsclock; ++ unsigned int mtmdsclock; ++}; ++ ++struct hdmi_qp_data_info { ++ unsigned int enc_in_bus_format; ++ unsigned int enc_out_bus_format; ++ unsigned int enc_in_encoding; ++ unsigned int enc_out_encoding; ++ unsigned int quant_range; ++ unsigned int pix_repet_factor; ++ struct hdmi_vmode_qp video_mode; ++ bool update; ++}; ++ ++struct dw_hdmi_qp_i2c { ++ struct i2c_adapter adap; ++ ++ struct mutex lock; /* used to serialize data transfers */ ++ struct completion cmp; ++ u32 stat; ++ ++ u8 slave_reg; ++ bool is_regaddr; ++ bool is_segment; ++ ++ unsigned int scl_high_ns; ++ unsigned int scl_low_ns; ++}; ++ ++struct dw_hdmi_qp { ++ struct drm_connector connector; ++ struct drm_bridge bridge; ++ struct platform_device *hdcp_dev; ++ struct platform_device *audio; ++ struct platform_device *cec; ++ struct device *dev; ++ struct dw_hdmi_qp_i2c *i2c; ++ ++ struct hdmi_qp_data_info hdmi_data; ++ const struct dw_hdmi_plat_data *plat_data; ++ ++ int vic; ++ int main_irq; ++ int avp_irq; ++ int earc_irq; ++ ++ u8 edid[HDMI_EDID_LEN]; ++ ++ struct { ++ const struct dw_hdmi_qp_phy_ops *ops; ++ const char *name; ++ void *data; ++ bool enabled; ++ } phy; ++ ++ struct drm_display_mode previous_mode; ++ ++ struct i2c_adapter *ddc; ++ void __iomem *regs; ++ bool sink_is_hdmi; ++ ++ struct mutex mutex; /* for state below and previous_mode */ ++ //[CC:] curr_conn should be removed ++ struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ ++ enum drm_connector_force force; /* mutex-protected force state */ ++ bool disabled; /* DRM has disabled our bridge */ ++ bool bridge_is_on; /* indicates the bridge is on */ ++ bool rxsense; /* rxsense state */ ++ u8 phy_mask; /* desired phy int mask settings */ ++ u8 mc_clkdis; /* clock disable register */ ++ ++ u32 scdc_intr; ++ u32 flt_intr; ++ //[CC:] remove earc ++ u32 earc_intr; ++ ++ struct dentry *debugfs_dir; ++ bool scramble_low_rates; ++ ++ struct extcon_dev *extcon; ++ ++ struct regmap *regm; ++ ++ bool initialized; /* hdmi is enabled before bind */ ++ struct completion flt_cmp; ++ struct completion earc_cmp; ++ ++ hdmi_codec_plugged_cb plugged_cb; ++ struct device *codec_dev; ++ enum drm_connector_status last_connector_result; ++}; ++ ++static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset) ++{ ++ regmap_write(hdmi->regm, offset, val); ++} ++ ++static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset) ++{ ++ unsigned int val = 0; ++ ++ regmap_read(hdmi->regm, offset, &val); ++ ++ return val; ++} ++ ++static void handle_plugged_change(struct dw_hdmi_qp *hdmi, bool plugged) ++{ ++ if (hdmi->plugged_cb && hdmi->codec_dev) ++ hdmi->plugged_cb(hdmi->codec_dev, plugged); ++} ++ ++static void hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, u32 reg) ++{ ++ regmap_update_bits(hdmi->regm, reg, mask, data); ++} ++ ++static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: ++ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static int hdmi_bus_fmt_color_depth(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ return 8; ++ ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ return 10; ++ ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: ++ return 12; ++ ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: ++ return 16; ++ ++ default: ++ return 0; ++ } ++} ++ ++static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) ++{ ++ /* Software reset */ ++ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); ++ ++ hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); ++ ++ hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); ++ ++ /* Clear DONE and ERROR interrupts */ ++ hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, ++ MAINUNIT_1_INT_CLEAR); ++} ++ ++static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi, ++ unsigned char *buf, unsigned int length) ++{ ++ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; ++ int stat; ++ ++ if (!i2c->is_regaddr) { ++ dev_dbg(hdmi->dev, "set read register address to 0\n"); ++ i2c->slave_reg = 0x00; ++ i2c->is_regaddr = true; ++ } ++ ++ while (length--) { ++ reinit_completion(&i2c->cmp); ++ ++ hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, ++ I2CM_INTERFACE_CONTROL0); ++ ++ hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK, ++ I2CM_INTERFACE_CONTROL0); ++ ++ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); ++ if (!stat) { ++ dev_err(hdmi->dev, "i2c read time out!\n"); ++ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); ++ return -EAGAIN; ++ } ++ ++ /* Check for error condition on the bus */ ++ if (i2c->stat & I2CM_NACK_RCVD_IRQ) { ++ dev_err(hdmi->dev, "i2c read err!\n"); ++ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); ++ return -EIO; ++ } ++ ++ *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; ++ hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); ++ } ++ i2c->is_segment = false; ++ ++ return 0; ++} ++ ++static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, ++ unsigned char *buf, unsigned int length) ++{ ++ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; ++ int stat; ++ ++ if (!i2c->is_regaddr) { ++ /* Use the first write byte as register address */ ++ i2c->slave_reg = buf[0]; ++ length--; ++ buf++; ++ i2c->is_regaddr = true; ++ } ++ ++ while (length--) { ++ reinit_completion(&i2c->cmp); ++ ++ hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); ++ hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, ++ I2CM_INTERFACE_CONTROL0); ++ hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, ++ I2CM_INTERFACE_CONTROL0); ++ ++ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); ++ if (!stat) { ++ dev_err(hdmi->dev, "i2c write time out!\n"); ++ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); ++ return -EAGAIN; ++ } ++ ++ /* Check for error condition on the bus */ ++ if (i2c->stat & I2CM_NACK_RCVD_IRQ) { ++ dev_err(hdmi->dev, "i2c write nack!\n"); ++ hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); ++ return -EIO; ++ } ++ hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); ++ } ++ ++ return 0; ++} ++ ++static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, ++ struct i2c_msg *msgs, int num) ++{ ++ struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap); ++ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; ++ u8 addr = msgs[0].addr; ++ int i, ret = 0; ++ ++ if (addr == DDC_CI_ADDR) ++ /* ++ * The internal I2C controller does not support the multi-byte ++ * read and write operations needed for DDC/CI. ++ * TOFIX: Blacklist the DDC/CI address until we filter out ++ * unsupported I2C operations. ++ */ ++ return -EOPNOTSUPP; ++ ++ for (i = 0; i < num; i++) { ++ if (msgs[i].len == 0) { ++ dev_err(hdmi->dev, ++ "unsupported transfer %d/%d, no data\n", ++ i + 1, num); ++ return -EOPNOTSUPP; ++ } ++ } ++ ++ mutex_lock(&i2c->lock); ++ ++ /* Unmute DONE and ERROR interrupts */ ++ hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, ++ I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, ++ MAINUNIT_1_INT_MASK_N); ++ ++ /* Set slave device address taken from the first I2C message */ ++ if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) ++ addr = DDC_ADDR; ++ ++ hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); ++ ++ /* Set slave device register address on transfer */ ++ i2c->is_regaddr = false; ++ ++ /* Set segment pointer for I2C extended read mode operation */ ++ i2c->is_segment = false; ++ ++ for (i = 0; i < num; i++) { ++ if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { ++ i2c->is_segment = true; ++ hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, ++ I2CM_INTERFACE_CONTROL1); ++ hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR, ++ I2CM_INTERFACE_CONTROL1); ++ } else { ++ if (msgs[i].flags & I2C_M_RD) ++ ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, ++ msgs[i].len); ++ else ++ ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, ++ msgs[i].len); ++ } ++ if (ret < 0) ++ break; ++ } ++ ++ if (!ret) ++ ret = num; ++ ++ /* Mute DONE and ERROR interrupts */ ++ hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, ++ MAINUNIT_1_INT_MASK_N); ++ ++ mutex_unlock(&i2c->lock); ++ ++ return ret; ++} ++ ++static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) ++{ ++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; ++} ++ ++static const struct i2c_algorithm dw_hdmi_algorithm = { ++ .master_xfer = dw_hdmi_i2c_xfer, ++ .functionality = dw_hdmi_i2c_func, ++}; ++ ++static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi_qp *hdmi) ++{ ++ struct i2c_adapter *adap; ++ struct dw_hdmi_qp_i2c *i2c; ++ int ret; ++ ++ i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); ++ if (!i2c) ++ return ERR_PTR(-ENOMEM); ++ ++ mutex_init(&i2c->lock); ++ init_completion(&i2c->cmp); ++ ++ adap = &i2c->adap; ++ adap->owner = THIS_MODULE; ++ adap->dev.parent = hdmi->dev; ++ adap->algo = &dw_hdmi_algorithm; ++ strscpy(adap->name, "ddc", sizeof(adap->name)); ++ i2c_set_adapdata(adap, hdmi); ++ ++ ret = i2c_add_adapter(adap); ++ if (ret) { ++ dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); ++ devm_kfree(hdmi->dev, i2c); ++ return ERR_PTR(ret); ++ } ++ ++ hdmi->i2c = i2c; ++ ++ dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); ++ ++ return adap; ++} ++ ++#define HDMI_PHY_EARC_MASK BIT(29) ++ ++/* ----------------------------------------------------------------------------- ++ * HDMI TX Setup ++ */ ++ ++static void hdmi_infoframe_set_checksum(u8 *ptr, int size) ++{ ++ u8 csum = 0; ++ int i; ++ ++ ptr[3] = 0; ++ /* compute checksum */ ++ for (i = 0; i < size; i++) ++ csum += ptr[i]; ++ ++ ptr[3] = 256 - csum; ++} ++ ++static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, ++ const struct drm_connector *connector, ++ const struct drm_display_mode *mode) ++{ ++ struct hdmi_avi_infoframe frame; ++ u32 val, i, j; ++ u8 buff[17]; ++ enum hdmi_quantization_range rgb_quant_range = ++ hdmi->hdmi_data.quant_range; ++ ++ /* Initialise info frame from DRM mode */ ++ drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); ++ ++ /* ++ * Ignore monitor selectable quantization, use quantization set ++ * by the user ++ */ ++ drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, rgb_quant_range); ++ if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) ++ frame.colorspace = HDMI_COLORSPACE_YUV444; ++ else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) ++ frame.colorspace = HDMI_COLORSPACE_YUV422; ++ else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) ++ frame.colorspace = HDMI_COLORSPACE_YUV420; ++ else ++ frame.colorspace = HDMI_COLORSPACE_RGB; ++ ++ /* Set up colorimetry */ ++ if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { ++ switch (hdmi->hdmi_data.enc_out_encoding) { ++ case V4L2_YCBCR_ENC_601: ++ if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) ++ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; ++ else ++ frame.colorimetry = HDMI_COLORIMETRY_ITU_601; ++ frame.extended_colorimetry = ++ HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; ++ break; ++ case V4L2_YCBCR_ENC_709: ++ if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) ++ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; ++ else ++ frame.colorimetry = HDMI_COLORIMETRY_ITU_709; ++ frame.extended_colorimetry = ++ HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; ++ break; ++ case V4L2_YCBCR_ENC_BT2020: ++ if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020) ++ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; ++ else ++ frame.colorimetry = HDMI_COLORIMETRY_ITU_709; ++ frame.extended_colorimetry = ++ HDMI_EXTENDED_COLORIMETRY_BT2020; ++ break; ++ default: /* Carries no data */ ++ frame.colorimetry = HDMI_COLORIMETRY_ITU_601; ++ frame.extended_colorimetry = ++ HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; ++ break; ++ } ++ } else { ++ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { ++ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; ++ frame.extended_colorimetry = ++ HDMI_EXTENDED_COLORIMETRY_BT2020; ++ } else { ++ frame.colorimetry = HDMI_COLORIMETRY_NONE; ++ frame.extended_colorimetry = ++ HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; ++ } ++ } ++ ++ frame.scan_mode = HDMI_SCAN_MODE_NONE; ++ frame.video_code = hdmi->vic; ++ ++ hdmi_avi_infoframe_pack_only(&frame, buff, 17); ++ ++ /* mode which vic >= 128 must use avi version 3 */ ++ if (hdmi->vic >= 128) { ++ frame.version = 3; ++ buff[1] = frame.version; ++ buff[4] &= 0x1f; ++ buff[4] |= ((frame.colorspace & 0x7) << 5); ++ buff[7] = frame.video_code; ++ hdmi_infoframe_set_checksum(buff, 17); ++ } ++ ++ /* ++ * The Designware IP uses a different byte format from standard ++ * AVI info frames, though generally the bits are in the correct ++ * bytes. ++ */ ++ ++ val = (frame.version << 8) | (frame.length << 16); ++ hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0); ++ ++ for (i = 0; i < 4; i++) { ++ for (j = 0; j < 4; j++) { ++ if (i * 4 + j >= 14) ++ break; ++ if (!j) ++ val = buff[i * 4 + j + 3]; ++ val |= buff[i * 4 + j + 3] << (8 * j); ++ } ++ ++ hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); ++ } ++ ++ hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); ++ ++ hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, ++ PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, ++ PKTSCHED_PKT_EN); ++} ++ ++static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi) ++{ ++ u8 ds_type = 0; ++ u8 sync = 1; ++ u8 vfr = 1; ++ u8 afr = 0; ++ u8 new = 1; ++ u8 end = 0; ++ u8 data_set_length = 136; ++ u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 }; ++ u8 *pps_body; ++ u32 val, i, reg; ++ struct drm_display_mode *mode = &hdmi->previous_mode; ++ int hsync, hfront, hback; ++ struct dw_hdmi_link_config *link_cfg; ++ void *data = hdmi->plat_data->phy_data; ++ ++ hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN); ++ ++ if (hdmi->plat_data->get_link_cfg) { ++ link_cfg = hdmi->plat_data->get_link_cfg(data); ++ } else { ++ dev_err(hdmi->dev, "can't get frl link cfg\n"); ++ return; ++ } ++ ++ if (!link_cfg->dsc_mode) { ++ dev_info(hdmi->dev, "don't use dsc mode\n"); ++ return; ++ } ++ ++ pps_body = link_cfg->pps_payload; ++ ++ hsync = mode->hsync_end - mode->hsync_start; ++ hback = mode->htotal - mode->hsync_end; ++ hfront = mode->hsync_start - mode->hdisplay; ++ ++ for (i = 0; i < 6; i++) { ++ val = i << 16 | hb1[i] << 8; ++ hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20); ++ } ++ ++ val = new << 7 | end << 6 | ds_type << 4 | afr << 3 | ++ vfr << 2 | sync << 1; ++ hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1); ++ ++ val = data_set_length << 16 | pps_body[0] << 24; ++ hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2); ++ ++ reg = PKT0_EMP_CVTEM_CONTENTS3; ++ for (i = 1; i < 125; i++) { ++ if (reg == PKT1_EMP_CVTEM_CONTENTS0 || ++ reg == PKT2_EMP_CVTEM_CONTENTS0 || ++ reg == PKT3_EMP_CVTEM_CONTENTS0 || ++ reg == PKT4_EMP_CVTEM_CONTENTS0 || ++ reg == PKT5_EMP_CVTEM_CONTENTS0) { ++ reg += 4; ++ i--; ++ continue; ++ } ++ if (i % 4 == 1) ++ val = pps_body[i]; ++ if (i % 4 == 2) ++ val |= pps_body[i] << 8; ++ if (i % 4 == 3) ++ val |= pps_body[i] << 16; ++ if (!(i % 4)) { ++ val |= pps_body[i] << 24; ++ hdmi_writel(hdmi, val, reg); ++ reg += 4; ++ } ++ } ++ ++ val = (hfront & 0xff) << 24 | pps_body[127] << 16 | ++ pps_body[126] << 8 | pps_body[125]; ++ hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6); ++ ++ val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 | ++ (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff); ++ hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7); ++ ++ val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff); ++ hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1); ++ ++ for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4) ++ hdmi_writel(hdmi, 0, i); ++ ++ hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN, ++ PKTSCHED_PKT_EN); ++} ++ ++static void hdmi_config_drm_infoframe(struct dw_hdmi_qp *hdmi, ++ const struct drm_connector *connector) ++{ ++ const struct drm_connector_state *conn_state = connector->state; ++ struct hdr_output_metadata *hdr_metadata; ++ struct hdmi_drm_infoframe frame; ++ u8 buffer[30]; ++ ssize_t err; ++ int i; ++ u32 val; ++ ++ if (!hdmi->plat_data->use_drm_infoframe) ++ return; ++ ++ hdmi_modb(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); ++ ++ if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) { ++ DRM_DEBUG("No need to set HDR metadata in infoframe\n"); ++ return; ++ } ++ ++ if (!conn_state->hdr_output_metadata) { ++ DRM_DEBUG("source metadata not set yet\n"); ++ return; ++ } ++ ++ hdr_metadata = (struct hdr_output_metadata *) ++ conn_state->hdr_output_metadata->data; ++ ++ if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf & ++ BIT(hdr_metadata->hdmi_metadata_type1.eotf))) { ++ DRM_ERROR("Not support EOTF %d\n", ++ hdr_metadata->hdmi_metadata_type1.eotf); ++ return; ++ } ++ ++ err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); ++ if (err < 0) ++ return; ++ ++ err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); ++ if (err < 0) { ++ dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); ++ return; ++ } ++ ++ val = (frame.version << 8) | (frame.length << 16); ++ hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS0); ++ ++ for (i = 0; i <= frame.length; i++) { ++ if (i % 4 == 0) ++ val = buffer[3 + i]; ++ val |= buffer[3 + i] << ((i % 4) * 8); ++ ++ if (i % 4 == 3 || (i == (frame.length))) ++ hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS1 + ((i / 4) * 4)); ++ } ++ ++ hdmi_modb(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1); ++ ++ hdmi_modb(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); ++ ++ DRM_DEBUG("%s eotf %d end\n", __func__, ++ hdr_metadata->hdmi_metadata_type1.eotf); ++} ++ ++/* Filter out invalid setups to avoid configuring SCDC and scrambling */ ++static bool dw_hdmi_support_scdc(struct dw_hdmi_qp *hdmi, ++ const struct drm_display_info *display) ++{ ++ /* Disable if no DDC bus */ ++ if (!hdmi->ddc) ++ return false; ++ ++ /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ ++ if (!display->hdmi.scdc.supported || ++ !display->hdmi.scdc.scrambling.supported) ++ return false; ++ ++ /* ++ * Disable if display only support low TMDS rates and scrambling ++ * for low rates is not supported either ++ */ ++ if (!display->hdmi.scdc.scrambling.low_rates && ++ display->max_tmds_clock <= 340000) ++ return false; ++ ++ return true; ++} ++ ++static int hdmi_set_frl_mask(int frl_rate) ++{ ++ switch (frl_rate) { ++ case 48: ++ return FRL_12GBPS_4LANE; ++ case 40: ++ return FRL_10GBPS_4LANE; ++ case 32: ++ return FRL_8GBPS_4LANE; ++ case 24: ++ return FRL_6GBPS_4LANE; ++ case 18: ++ return FRL_6GBPS_3LANE; ++ case 9: ++ return FRL_3GBPS_3LANE; ++ } ++ ++ return 0; ++} ++ ++static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate) ++{ ++ u8 val; ++ u8 ffe_lv = 0; ++ int i = 0, stat; ++ ++ /* FLT_READY & FFE_LEVELS read */ ++ for (i = 0; i < 20; i++) { ++ drm_scdc_readb(hdmi->ddc, SCDC_STATUS_FLAGS_0, &val); ++ if (val & BIT(6)) ++ break; ++ msleep(20); ++ } ++ ++ if (i == 20) { ++ dev_err(hdmi->dev, "sink flt isn't ready\n"); ++ return -EINVAL; ++ } ++ ++ hdmi_modb(hdmi, SCDC_UPD_FLAGS_RD_IRQ, SCDC_UPD_FLAGS_RD_IRQ, ++ MAINUNIT_1_INT_MASK_N); ++ hdmi_modb(hdmi, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, ++ SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, ++ SCDC_CONFIG0); ++ ++ /* max ffe level 3 */ ++ val = 3 << 4 | hdmi_set_frl_mask(rate); ++ drm_scdc_writeb(hdmi->ddc, 0x31, val); ++ ++ /* select FRL_RATE & FFE_LEVELS */ ++ hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0); ++ ++ /* Start LTS_3 state in source DUT */ ++ reinit_completion(&hdmi->flt_cmp); ++ hdmi_modb(hdmi, FLT_EXIT_TO_LTSP_IRQ, FLT_EXIT_TO_LTSP_IRQ, ++ MAINUNIT_1_INT_MASK_N); ++ hdmi_writel(hdmi, 1, FLT_CONTROL0); ++ ++ /* wait for completed link training at source side */ ++ stat = wait_for_completion_timeout(&hdmi->flt_cmp, HZ * 2); ++ if (!stat) { ++ dev_err(hdmi->dev, "wait lts3 finish time out\n"); ++ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | ++ SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); ++ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, ++ MAINUNIT_1_INT_MASK_N); ++ return -EAGAIN; ++ } ++ ++ if (!(hdmi->flt_intr & FLT_EXIT_TO_LTSP_IRQ)) { ++ dev_err(hdmi->dev, "not to ltsp\n"); ++ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | ++ SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); ++ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, ++ MAINUNIT_1_INT_MASK_N); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++#define HDMI_MODE_FRL_MASK BIT(30) ++ ++static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi, ++ struct dw_hdmi_link_config *link_cfg, ++ const struct drm_connector *connector) ++{ ++ int frl_rate; ++ int i; ++ ++ /* set sink frl mode disable and wait sink ready */ ++ hdmi_writel(hdmi, 0, FLT_CONFIG0); ++ if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) ++ drm_scdc_writeb(hdmi->ddc, 0x31, 0); ++ /* ++ * some TVs must wait a while before switching frl mode resolution, ++ * or the signal may not be recognized. ++ */ ++ msleep(200); ++ ++ if (!link_cfg->frl_mode) { ++ dev_info(hdmi->dev, "dw hdmi qp use tmds mode\n"); ++ hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0); ++ hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); ++ return; ++ } ++ ++ if (link_cfg->frl_lanes == 4) ++ hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES, ++ LINK_CONFIG0); ++ else ++ hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); ++ ++ hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0); ++ ++ frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane; ++ hdmi_start_flt(hdmi, frl_rate); ++ ++ for (i = 0; i < 50; i++) { ++ hdmi_modb(hdmi, PKTSCHED_NULL_TX_EN, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); ++ mdelay(1); ++ hdmi_modb(hdmi, 0, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); ++ } ++} ++ ++static unsigned long ++hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock) ++{ ++ unsigned long tmdsclock = mpixelclock; ++ unsigned int depth = ++ hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); ++ ++ if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { ++ switch (depth) { ++ case 16: ++ tmdsclock = mpixelclock * 2; ++ break; ++ case 12: ++ tmdsclock = mpixelclock * 3 / 2; ++ break; ++ case 10: ++ tmdsclock = mpixelclock * 5 / 4; ++ break; ++ default: ++ break; ++ } ++ } ++ ++ return tmdsclock; ++} ++ ++//[CC:] is connector param different from hdmi->connector? ++//[CC:] probably it possible to hook the whole implementation into dw-hdmi.c ++static int dw_hdmi_qp_setup(struct dw_hdmi_qp *hdmi, ++ struct drm_connector *connector, ++ struct drm_display_mode *mode) ++{ ++ int ret; ++ void *data = hdmi->plat_data->phy_data; ++ struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode; ++ struct dw_hdmi_link_config *link_cfg; ++ u8 bytes = 0; ++ ++ hdmi->vic = drm_match_cea_mode(mode); ++ if (!hdmi->vic) ++ dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); ++ else ++ dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); ++ ++ if (hdmi->plat_data->get_enc_out_encoding) ++ hdmi->hdmi_data.enc_out_encoding = ++ hdmi->plat_data->get_enc_out_encoding(data); ++ else if ((hdmi->vic == 6) || (hdmi->vic == 7) || ++ (hdmi->vic == 21) || (hdmi->vic == 22) || ++ (hdmi->vic == 2) || (hdmi->vic == 3) || ++ (hdmi->vic == 17) || (hdmi->vic == 18)) ++ hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; ++ else ++ hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; ++ ++ if (mode->flags & DRM_MODE_FLAG_DBLCLK) { ++ hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; ++ hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; ++ } else { ++ hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; ++ hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; ++ } ++ /* Get input format from plat data or fallback to RGB888 */ ++ if (hdmi->plat_data->get_input_bus_format) ++ hdmi->hdmi_data.enc_in_bus_format = ++ hdmi->plat_data->get_input_bus_format(data); ++ else if (hdmi->plat_data->input_bus_format) ++ hdmi->hdmi_data.enc_in_bus_format = ++ hdmi->plat_data->input_bus_format; ++ else ++ hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; ++ ++ /* Default to RGB888 output format */ ++ if (hdmi->plat_data->get_output_bus_format) ++ hdmi->hdmi_data.enc_out_bus_format = ++ hdmi->plat_data->get_output_bus_format(data); ++ else ++ hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; ++ ++ /* Get input encoding from plat data or fallback to none */ ++ if (hdmi->plat_data->get_enc_in_encoding) ++ hdmi->hdmi_data.enc_in_encoding = ++ hdmi->plat_data->get_enc_in_encoding(data); ++ else if (hdmi->plat_data->input_bus_encoding) ++ hdmi->hdmi_data.enc_in_encoding = ++ hdmi->plat_data->input_bus_encoding; ++ else ++ hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; ++ ++ if (hdmi->plat_data->get_quant_range) ++ hdmi->hdmi_data.quant_range = ++ hdmi->plat_data->get_quant_range(data); ++ else ++ hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; ++ ++ if (hdmi->plat_data->get_link_cfg) ++ link_cfg = hdmi->plat_data->get_link_cfg(data); ++ else ++ return -EINVAL; ++ ++ hdmi->phy.ops->set_mode(hdmi, hdmi->phy.data, HDMI_MODE_FRL_MASK, ++ link_cfg->frl_mode); ++ ++ /* ++ * According to the dw-hdmi specification 6.4.2 ++ * vp_pr_cd[3:0]: ++ * 0000b: No pixel repetition (pixel sent only once) ++ * 0001b: Pixel sent two times (pixel repeated once) ++ */ ++ hdmi->hdmi_data.pix_repet_factor = ++ (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; ++ hdmi->hdmi_data.video_mode.mdataenablepolarity = true; ++ ++ vmode->previous_pixelclock = vmode->mpixelclock; ++ //[CC:] no split mode ++ // if (hdmi->plat_data->split_mode) ++ // mode->crtc_clock /= 2; ++ vmode->mpixelclock = mode->crtc_clock * 1000; ++ if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) ++ vmode->mpixelclock *= 2; ++ dev_dbg(hdmi->dev, "final pixclk = %ld\n", vmode->mpixelclock); ++ vmode->previous_tmdsclock = vmode->mtmdsclock; ++ vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); ++ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) ++ vmode->mtmdsclock /= 2; ++ dev_info(hdmi->dev, "final tmdsclk = %d\n", vmode->mtmdsclock); ++ ++ ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); ++ if (ret) ++ return ret; ++ ++ if (hdmi->plat_data->set_grf_cfg) ++ hdmi->plat_data->set_grf_cfg(data); ++ ++ /* not for DVI mode */ ++ if (hdmi->sink_is_hdmi) { ++ dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); ++ hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0); ++ hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); ++ if (!link_cfg->frl_mode) { ++ if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) { ++ drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, &bytes); ++ drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, ++ min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); ++ //[CC:] use dw_hdmi_set_high_tmds_clock_ratio() ++ drm_scdc_set_high_tmds_clock_ratio(connector, 1); ++ drm_scdc_set_scrambling(connector, 1); ++ hdmi_writel(hdmi, 1, SCRAMB_CONFIG0); ++ } else { ++ if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) { ++ drm_scdc_set_high_tmds_clock_ratio(connector, 0); ++ drm_scdc_set_scrambling(connector, 0); ++ } ++ hdmi_writel(hdmi, 0, SCRAMB_CONFIG0); ++ } ++ } ++ /* HDMI Initialization Step F - Configure AVI InfoFrame */ ++ hdmi_config_AVI(hdmi, connector, mode); ++ hdmi_config_CVTEM(hdmi); ++ hdmi_config_drm_infoframe(hdmi, connector); ++ hdmi_set_op_mode(hdmi, link_cfg, connector); ++ } else { ++ hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); ++ hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0); ++ dev_info(hdmi->dev, "%s DVI mode\n", __func__); ++ } ++ ++ return 0; ++} ++ ++static enum drm_connector_status ++dw_hdmi_connector_detect(struct drm_connector *connector, bool force) ++{ ++ struct dw_hdmi_qp *hdmi = ++ container_of(connector, struct dw_hdmi_qp, connector); ++ struct dw_hdmi_qp *secondary = NULL; ++ enum drm_connector_status result, result_secondary; ++ ++ mutex_lock(&hdmi->mutex); ++ hdmi->force = DRM_FORCE_UNSPECIFIED; ++ mutex_unlock(&hdmi->mutex); ++ ++ if (hdmi->plat_data->left) ++ secondary = hdmi->plat_data->left; ++ else if (hdmi->plat_data->right) ++ secondary = hdmi->plat_data->right; ++ ++ result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); ++ ++ if (secondary) { ++ result_secondary = secondary->phy.ops->read_hpd(secondary, secondary->phy.data); ++ if (result == connector_status_connected && ++ result_secondary == connector_status_connected) ++ result = connector_status_connected; ++ else ++ result = connector_status_disconnected; ++ } ++ ++ mutex_lock(&hdmi->mutex); ++ if (result != hdmi->last_connector_result) { ++ dev_dbg(hdmi->dev, "read_hpd result: %d", result); ++ handle_plugged_change(hdmi, ++ result == connector_status_connected); ++ hdmi->last_connector_result = result; ++ } ++ mutex_unlock(&hdmi->mutex); ++ ++ return result; ++} ++ ++static int ++dw_hdmi_update_hdr_property(struct drm_connector *connector) ++{ ++ struct drm_device *dev = connector->dev; ++ struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, ++ connector); ++ void *data = hdmi->plat_data->phy_data; ++ const struct hdr_static_metadata *metadata = ++ &connector->hdr_sink_metadata.hdmi_type1; ++ size_t size = sizeof(*metadata); ++ struct drm_property *property = NULL; ++ struct drm_property_blob *blob; ++ int ret; ++ ++ if (hdmi->plat_data->get_hdr_property) ++ property = hdmi->plat_data->get_hdr_property(data); ++ ++ if (!property) ++ return -EINVAL; ++ ++ if (hdmi->plat_data->get_hdr_blob) ++ blob = hdmi->plat_data->get_hdr_blob(data); ++ else ++ return -EINVAL; ++ ++ ret = drm_property_replace_global_blob(dev, &blob, size, metadata, ++ &connector->base, property); ++ return ret; ++} ++ ++static int dw_hdmi_connector_get_modes(struct drm_connector *connector) ++{ ++ struct dw_hdmi_qp *hdmi = ++ container_of(connector, struct dw_hdmi_qp, connector); ++ struct hdr_static_metadata *metedata = ++ &connector->hdr_sink_metadata.hdmi_type1; ++ struct edid *edid; ++ struct drm_display_mode *mode; ++ struct drm_display_info *info = &connector->display_info; ++ // void *data = hdmi->plat_data->phy_data; ++ int i, ret = 0; ++ ++ if (!hdmi->ddc) ++ return 0; ++ ++ memset(metedata, 0, sizeof(*metedata)); ++ edid = drm_get_edid(connector, hdmi->ddc); ++ if (edid) { ++ dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", ++ edid->width_cm, edid->height_cm); ++ ++ hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); ++ drm_connector_update_edid_property(connector, edid); ++ // if (hdmi->plat_data->get_edid_dsc_info) ++ // hdmi->plat_data->get_edid_dsc_info(data, edid); ++ ret = drm_add_edid_modes(connector, edid); ++ dw_hdmi_update_hdr_property(connector); ++ // if (ret > 0 && hdmi->plat_data->split_mode) { ++ // struct dw_hdmi_qp *secondary = NULL; ++ // void *secondary_data; ++ // ++ // if (hdmi->plat_data->left) ++ // secondary = hdmi->plat_data->left; ++ // else if (hdmi->plat_data->right) ++ // secondary = hdmi->plat_data->right; ++ // ++ // if (!secondary) ++ // return -ENOMEM; ++ // secondary_data = secondary->plat_data->phy_data; ++ // ++ // list_for_each_entry(mode, &connector->probed_modes, head) ++ // hdmi->plat_data->convert_to_split_mode(mode); ++ // ++ // secondary->sink_is_hdmi = drm_detect_hdmi_monitor(edid); ++ // if (secondary->plat_data->get_edid_dsc_info) ++ // secondary->plat_data->get_edid_dsc_info(secondary_data, edid); ++ // } ++ kfree(edid); ++ } else { ++ hdmi->sink_is_hdmi = true; ++ ++ if (hdmi->plat_data->split_mode) { ++ if (hdmi->plat_data->left) { ++ hdmi->plat_data->left->sink_is_hdmi = true; ++ } else if (hdmi->plat_data->right) { ++ hdmi->plat_data->right->sink_is_hdmi = true; ++ } ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) { ++ const struct drm_display_mode *ptr = ++ &dw_hdmi_default_modes[i]; ++ ++ mode = drm_mode_duplicate(connector->dev, ptr); ++ if (mode) { ++ if (!i) ++ mode->type = DRM_MODE_TYPE_PREFERRED; ++ drm_mode_probed_add(connector, mode); ++ ret++; ++ } ++ } ++ if (ret > 0 && hdmi->plat_data->split_mode) { ++ struct drm_display_mode *mode; ++ ++ list_for_each_entry(mode, &connector->probed_modes, head) ++ hdmi->plat_data->convert_to_split_mode(mode); ++ } ++ info->edid_hdmi_rgb444_dc_modes = 0; ++ info->hdmi.y420_dc_modes = 0; ++ info->color_formats = 0; ++ ++ dev_info(hdmi->dev, "failed to get edid\n"); ++ } ++ ++ return ret; ++} ++ ++static int ++dw_hdmi_atomic_connector_set_property(struct drm_connector *connector, ++ struct drm_connector_state *state, ++ struct drm_property *property, ++ uint64_t val) ++{ ++ struct dw_hdmi_qp *hdmi = ++ container_of(connector, struct dw_hdmi_qp, connector); ++ const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops; ++ ++ if (ops && ops->set_property) ++ return ops->set_property(connector, state, property, ++ val, hdmi->plat_data->phy_data); ++ else ++ return -EINVAL; ++} ++ ++static int ++dw_hdmi_atomic_connector_get_property(struct drm_connector *connector, ++ const struct drm_connector_state *state, ++ struct drm_property *property, ++ uint64_t *val) ++{ ++ struct dw_hdmi_qp *hdmi = ++ container_of(connector, struct dw_hdmi_qp, connector); ++ const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops; ++ ++ if (ops && ops->get_property) ++ return ops->get_property(connector, state, property, ++ val, hdmi->plat_data->phy_data); ++ else ++ return -EINVAL; ++} ++ ++static int ++dw_hdmi_connector_set_property(struct drm_connector *connector, ++ struct drm_property *property, uint64_t val) ++{ ++ return dw_hdmi_atomic_connector_set_property(connector, NULL, ++ property, val); ++} ++ ++static void dw_hdmi_attach_properties(struct dw_hdmi_qp *hdmi) ++{ ++ unsigned int color = MEDIA_BUS_FMT_RGB888_1X24; ++ const struct dw_hdmi_property_ops *ops = ++ hdmi->plat_data->property_ops; ++ ++ if (ops && ops->attach_properties) ++ return ops->attach_properties(&hdmi->connector, color, 0, ++ hdmi->plat_data->phy_data); ++} ++ ++static void dw_hdmi_destroy_properties(struct dw_hdmi_qp *hdmi) ++{ ++ const struct dw_hdmi_property_ops *ops = ++ hdmi->plat_data->property_ops; ++ ++ if (ops && ops->destroy_properties) ++ return ops->destroy_properties(&hdmi->connector, ++ hdmi->plat_data->phy_data); ++} ++ ++static struct drm_encoder * ++dw_hdmi_connector_best_encoder(struct drm_connector *connector) ++{ ++ struct dw_hdmi_qp *hdmi = ++ container_of(connector, struct dw_hdmi_qp, connector); ++ ++ return hdmi->bridge.encoder; ++} ++ ++static bool dw_hdmi_color_changed(struct drm_connector *connector, ++ struct drm_atomic_state *state) ++{ ++ struct dw_hdmi_qp *hdmi = ++ container_of(connector, struct dw_hdmi_qp, connector); ++ void *data = hdmi->plat_data->phy_data; ++ struct drm_connector_state *old_state = ++ drm_atomic_get_old_connector_state(state, connector); ++ struct drm_connector_state *new_state = ++ drm_atomic_get_new_connector_state(state, connector); ++ bool ret = false; ++ ++ if (hdmi->plat_data->get_color_changed) ++ ret = hdmi->plat_data->get_color_changed(data); ++ ++ if (new_state->colorspace != old_state->colorspace) ++ ret = true; ++ ++ return ret; ++} ++ ++static bool hdr_metadata_equal(const struct drm_connector_state *old_state, ++ const struct drm_connector_state *new_state) ++{ ++ struct drm_property_blob *old_blob = old_state->hdr_output_metadata; ++ struct drm_property_blob *new_blob = new_state->hdr_output_metadata; ++ ++ if (!old_blob || !new_blob) ++ return old_blob == new_blob; ++ ++ if (old_blob->length != new_blob->length) ++ return false; ++ ++ return !memcmp(old_blob->data, new_blob->data, old_blob->length); ++} ++ ++static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, ++ struct drm_atomic_state *state) ++{ ++ struct drm_connector_state *old_state = ++ drm_atomic_get_old_connector_state(state, connector); ++ struct drm_connector_state *new_state = ++ drm_atomic_get_new_connector_state(state, connector); ++ struct drm_crtc *crtc = new_state->crtc; ++ struct drm_crtc_state *crtc_state; ++ struct dw_hdmi_qp *hdmi = ++ container_of(connector, struct dw_hdmi_qp, connector); ++ struct drm_display_mode *mode = NULL; ++ void *data = hdmi->plat_data->phy_data; ++ struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode; ++ ++ if (!crtc) ++ return 0; ++ ++ crtc_state = drm_atomic_get_crtc_state(state, crtc); ++ if (IS_ERR(crtc_state)) ++ return PTR_ERR(crtc_state); ++ ++ /* ++ * If HDMI is enabled in uboot, it's need to record ++ * drm_display_mode and set phy status to enabled. ++ */ ++ if (!vmode->mpixelclock) { ++ crtc_state = drm_atomic_get_crtc_state(state, crtc); ++ if (hdmi->plat_data->get_enc_in_encoding) ++ hdmi->hdmi_data.enc_in_encoding = ++ hdmi->plat_data->get_enc_in_encoding(data); ++ if (hdmi->plat_data->get_enc_out_encoding) ++ hdmi->hdmi_data.enc_out_encoding = ++ hdmi->plat_data->get_enc_out_encoding(data); ++ if (hdmi->plat_data->get_input_bus_format) ++ hdmi->hdmi_data.enc_in_bus_format = ++ hdmi->plat_data->get_input_bus_format(data); ++ if (hdmi->plat_data->get_output_bus_format) ++ hdmi->hdmi_data.enc_out_bus_format = ++ hdmi->plat_data->get_output_bus_format(data); ++ ++ mode = &crtc_state->mode; ++ if (hdmi->plat_data->split_mode) { ++ hdmi->plat_data->convert_to_origin_mode(mode); ++ mode->crtc_clock /= 2; ++ } ++ memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); ++ vmode->mpixelclock = mode->crtc_clock * 1000; ++ vmode->previous_pixelclock = mode->clock; ++ vmode->previous_tmdsclock = mode->clock; ++ vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, ++ vmode->mpixelclock); ++ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) ++ vmode->mtmdsclock /= 2; ++ } ++ ++ if (!hdr_metadata_equal(old_state, new_state) || ++ dw_hdmi_color_changed(connector, state)) { ++ crtc_state = drm_atomic_get_crtc_state(state, crtc); ++ if (IS_ERR(crtc_state)) ++ return PTR_ERR(crtc_state); ++ ++ crtc_state->mode_changed = true; ++ } ++ ++ return 0; ++} ++ ++static void dw_hdmi_connector_force(struct drm_connector *connector) ++{ ++ struct dw_hdmi_qp *hdmi = ++ container_of(connector, struct dw_hdmi_qp, connector); ++ ++ mutex_lock(&hdmi->mutex); ++ ++ if (hdmi->force != connector->force) { ++ if (!hdmi->disabled && connector->force == DRM_FORCE_OFF) ++ extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, ++ false); ++ else if (hdmi->disabled && connector->force == DRM_FORCE_ON) ++ extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, ++ true); ++ } ++ ++ hdmi->force = connector->force; ++ mutex_unlock(&hdmi->mutex); ++} ++ ++static int dw_hdmi_qp_fill_modes(struct drm_connector *connector, u32 max_x, ++ u32 max_y) ++{ ++ return drm_helper_probe_single_connector_modes(connector, 9000, 9000); ++} ++ ++static const struct drm_connector_funcs dw_hdmi_connector_funcs = { ++ .fill_modes = dw_hdmi_qp_fill_modes, ++ .detect = dw_hdmi_connector_detect, ++ .destroy = drm_connector_cleanup, ++ .force = dw_hdmi_connector_force, ++ .reset = drm_atomic_helper_connector_reset, ++ .set_property = dw_hdmi_connector_set_property, ++ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, ++ .atomic_set_property = dw_hdmi_atomic_connector_set_property, ++ .atomic_get_property = dw_hdmi_atomic_connector_get_property, ++}; ++ ++static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { ++ .get_modes = dw_hdmi_connector_get_modes, ++ .best_encoder = dw_hdmi_connector_best_encoder, ++ .atomic_check = dw_hdmi_connector_atomic_check, ++}; ++ ++static int dw_hdmi_qp_bridge_attach(struct drm_bridge *bridge, ++ enum drm_bridge_attach_flags flags) ++{ ++ struct dw_hdmi_qp *hdmi = bridge->driver_private; ++ struct drm_encoder *encoder = bridge->encoder; ++ struct drm_connector *connector = &hdmi->connector; ++ ++ if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) ++ return 0; ++ ++ connector->interlace_allowed = 1; ++ connector->polled = DRM_CONNECTOR_POLL_HPD; ++ ++ drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); ++ ++ // [CC:] use drm_connector_init_with_ddc or drmm_connector_init ++ // to provide ddc reference ++ drm_connector_init_with_ddc(bridge->dev, connector, ++ &dw_hdmi_connector_funcs, ++ DRM_MODE_CONNECTOR_HDMIA, ++ hdmi->ddc); ++ ++ drm_connector_attach_encoder(connector, encoder); ++ dw_hdmi_attach_properties(hdmi); ++ ++ return 0; ++} ++ ++static void dw_hdmi_qp_bridge_mode_set(struct drm_bridge *bridge, ++ const struct drm_display_mode *orig_mode, ++ const struct drm_display_mode *mode) ++{ ++ struct dw_hdmi_qp *hdmi = bridge->driver_private; ++ ++ mutex_lock(&hdmi->mutex); ++ ++ /* Store the display mode for plugin/DKMS poweron events */ ++ memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); ++ if (hdmi->plat_data->split_mode) ++ hdmi->plat_data->convert_to_origin_mode(&hdmi->previous_mode); ++ ++ mutex_unlock(&hdmi->mutex); ++} ++ ++static enum drm_mode_status ++dw_hdmi_qp_bridge_mode_valid(struct drm_bridge *bridge, ++ const struct drm_display_info *info, ++ const struct drm_display_mode *mode) ++{ ++ return MODE_OK; ++} ++ ++static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, ++ struct drm_bridge_state *old_state) ++{ ++ struct dw_hdmi_qp *hdmi = bridge->driver_private; ++ struct drm_atomic_state *state = old_state->base.state; ++ struct drm_connector *connector; ++ ++ connector = drm_atomic_get_new_connector_for_encoder(state, ++ bridge->encoder); ++ ++ mutex_lock(&hdmi->mutex); ++ hdmi->curr_conn = connector; ++ dw_hdmi_qp_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); ++ hdmi->disabled = false; ++ mutex_unlock(&hdmi->mutex); ++ ++ extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true); ++ handle_plugged_change(hdmi, true); ++} ++ ++static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, ++ struct drm_bridge_state *old_state) ++{ ++ struct dw_hdmi_qp *hdmi = bridge->driver_private; ++ ++ extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false); ++ handle_plugged_change(hdmi, false); ++ mutex_lock(&hdmi->mutex); ++ ++ hdmi->curr_conn = NULL; ++ ++ if (hdmi->phy.ops->disable) ++ hdmi->phy.ops->disable(hdmi, hdmi->phy.data); ++ hdmi->disabled = true; ++ mutex_unlock(&hdmi->mutex); ++} ++ ++static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { ++ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, ++ .atomic_reset = drm_atomic_helper_bridge_reset, ++ .attach = dw_hdmi_qp_bridge_attach, ++ .mode_set = dw_hdmi_qp_bridge_mode_set, ++ .mode_valid = dw_hdmi_qp_bridge_mode_valid, ++ .atomic_enable = dw_hdmi_qp_bridge_atomic_enable, ++ .atomic_disable = dw_hdmi_qp_bridge_atomic_disable, ++}; ++ ++static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) ++{ ++ struct dw_hdmi_qp *hdmi = dev_id; ++ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; ++ u32 stat; ++ ++ stat = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS); ++ ++ i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | ++ I2CM_NACK_RCVD_IRQ); ++ hdmi->scdc_intr = stat & (SCDC_UPD_FLAGS_RD_IRQ | ++ SCDC_UPD_FLAGS_CHG_IRQ | ++ SCDC_UPD_FLAGS_CLR_IRQ | ++ SCDC_RR_REPLY_STOP_IRQ | ++ SCDC_NACK_RCVD_IRQ); ++ hdmi->flt_intr = stat & (FLT_EXIT_TO_LTSP_IRQ | ++ FLT_EXIT_TO_LTS4_IRQ | ++ FLT_EXIT_TO_LTSL_IRQ); ++ ++ if (i2c->stat) { ++ hdmi_writel(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR); ++ complete(&i2c->cmp); ++ } ++ ++ if (hdmi->flt_intr) { ++ dev_dbg(hdmi->dev, "i2c flt irq:%#x\n", hdmi->flt_intr); ++ hdmi_writel(hdmi, hdmi->flt_intr, MAINUNIT_1_INT_CLEAR); ++ complete(&hdmi->flt_cmp); ++ } ++ ++ if (hdmi->scdc_intr) { ++ u8 val; ++ ++ dev_dbg(hdmi->dev, "i2c scdc irq:%#x\n", hdmi->scdc_intr); ++ hdmi_writel(hdmi, hdmi->scdc_intr, MAINUNIT_1_INT_CLEAR); ++ val = hdmi_readl(hdmi, SCDC_STATUS0); ++ ++ /* frl start */ ++ if (val & BIT(4)) { ++ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | ++ SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); ++ hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, ++ MAINUNIT_1_INT_MASK_N); ++ dev_info(hdmi->dev, "frl start\n"); ++ } ++ ++ } ++ ++ if (stat) ++ return IRQ_HANDLED; ++ ++ return IRQ_NONE; ++} ++ ++static irqreturn_t dw_hdmi_qp_avp_hardirq(int irq, void *dev_id) ++{ ++ struct dw_hdmi_qp *hdmi = dev_id; ++ u32 stat; ++ ++ stat = hdmi_readl(hdmi, AVP_1_INT_STATUS); ++ if (stat) { ++ dev_dbg(hdmi->dev, "HDCP irq %#x\n", stat); ++ stat &= ~stat; ++ hdmi_writel(hdmi, stat, AVP_1_INT_MASK_N); ++ return IRQ_WAKE_THREAD; ++ } ++ ++ return IRQ_NONE; ++} ++ ++static irqreturn_t dw_hdmi_qp_earc_hardirq(int irq, void *dev_id) ++{ ++ struct dw_hdmi_qp *hdmi = dev_id; ++ u32 stat; ++ ++ stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS); ++ if (stat) { ++ dev_dbg(hdmi->dev, "earc irq %#x\n", stat); ++ stat &= ~stat; ++ hdmi_writel(hdmi, stat, EARCRX_0_INT_MASK_N); ++ return IRQ_WAKE_THREAD; ++ } ++ ++ return IRQ_NONE; ++} ++ ++static irqreturn_t dw_hdmi_qp_avp_irq(int irq, void *dev_id) ++{ ++ struct dw_hdmi_qp *hdmi = dev_id; ++ u32 stat; ++ ++ stat = hdmi_readl(hdmi, AVP_1_INT_STATUS); ++ ++ if (!stat) ++ return IRQ_NONE; ++ ++ hdmi_writel(hdmi, stat, AVP_1_INT_CLEAR); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t dw_hdmi_qp_earc_irq(int irq, void *dev_id) ++{ ++ struct dw_hdmi_qp *hdmi = dev_id; ++ u32 stat; ++ ++ stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS); ++ ++ if (!stat) ++ return IRQ_NONE; ++ ++ hdmi_writel(hdmi, stat, EARCRX_0_INT_CLEAR); ++ ++ hdmi->earc_intr = stat; ++ complete(&hdmi->earc_cmp); ++ ++ return IRQ_HANDLED; ++} ++ ++static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi) ++{ ++ u8 phy_type; ++ ++ phy_type = hdmi->plat_data->phy_force_vendor ? ++ DW_HDMI_PHY_VENDOR_PHY : 0; ++ ++ if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { ++ /* Vendor PHYs require support from the glue layer. */ ++ if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) { ++ dev_err(hdmi->dev, ++ "Vendor HDMI PHY not supported by glue layer\n"); ++ return -ENODEV; ++ } ++ ++ hdmi->phy.ops = hdmi->plat_data->qp_phy_ops; ++ hdmi->phy.data = hdmi->plat_data->phy_data; ++ hdmi->phy.name = hdmi->plat_data->phy_name; ++ } ++ ++ return 0; ++} ++ ++static const struct regmap_config hdmi_regmap_config = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = EARCRX_1_INT_FORCE, ++}; ++ ++struct dw_hdmi_qp_reg_table { ++ int reg_base; ++ int reg_end; ++}; ++ ++static const struct dw_hdmi_qp_reg_table hdmi_reg_table[] = { ++ {0x0, 0xc}, ++ {0x14, 0x1c}, ++ {0x44, 0x48}, ++ {0x50, 0x58}, ++ {0x80, 0x84}, ++ {0xa0, 0xc4}, ++ {0xe0, 0xe8}, ++ {0xf0, 0x118}, ++ {0x140, 0x140}, ++ {0x150, 0x150}, ++ {0x160, 0x168}, ++ {0x180, 0x180}, ++ {0x800, 0x800}, ++ {0x808, 0x808}, ++ {0x814, 0x814}, ++ {0x81c, 0x824}, ++ {0x834, 0x834}, ++ {0x840, 0x864}, ++ {0x86c, 0x86c}, ++ {0x880, 0x89c}, ++ {0x8e0, 0x8e8}, ++ {0x900, 0x900}, ++ {0x908, 0x90c}, ++ {0x920, 0x938}, ++ {0x920, 0x938}, ++ {0x960, 0x960}, ++ {0x968, 0x968}, ++ {0xa20, 0xa20}, ++ {0xa30, 0xa30}, ++ {0xa40, 0xa40}, ++ {0xa54, 0xa54}, ++ {0xa80, 0xaac}, ++ {0xab4, 0xab8}, ++ {0xb00, 0xcbc}, ++ {0xce0, 0xce0}, ++ {0xd00, 0xddc}, ++ {0xe20, 0xe24}, ++ {0xe40, 0xe44}, ++ {0xe4c, 0xe4c}, ++ {0xe60, 0xe80}, ++ {0xea0, 0xf24}, ++ {0x1004, 0x100c}, ++ {0x1020, 0x1030}, ++ {0x1040, 0x1050}, ++ {0x1060, 0x1068}, ++ {0x1800, 0x1820}, ++ {0x182c, 0x182c}, ++ {0x1840, 0x1940}, ++ {0x1960, 0x1a60}, ++ {0x1b00, 0x1b00}, ++ {0x1c00, 0x1c00}, ++ {0x3000, 0x3000}, ++ {0x3010, 0x3014}, ++ {0x3020, 0x3024}, ++ {0x3800, 0x3800}, ++ {0x3810, 0x3814}, ++ {0x3820, 0x3824}, ++ {0x3830, 0x3834}, ++ {0x3840, 0x3844}, ++ {0x3850, 0x3854}, ++ {0x3860, 0x3864}, ++ {0x3870, 0x3874}, ++ {0x4000, 0x4004}, ++ {0x4800, 0x4800}, ++ {0x4810, 0x4814}, ++}; ++ ++static int dw_hdmi_ctrl_show(struct seq_file *s, void *v) ++{ ++ struct dw_hdmi_qp *hdmi = s->private; ++ u32 i = 0, j = 0, val = 0; ++ ++ seq_puts(s, "\n---------------------------------------------------"); ++ ++ for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) { ++ for (j = hdmi_reg_table[i].reg_base; ++ j <= hdmi_reg_table[i].reg_end; j += 4) { ++ val = hdmi_readl(hdmi, j); ++ ++ if ((j - hdmi_reg_table[i].reg_base) % 16 == 0) ++ seq_printf(s, "\n>>>hdmi_ctl %04x:", j); ++ seq_printf(s, " %08x", val); ++ } ++ } ++ seq_puts(s, "\n---------------------------------------------------\n"); ++ ++ return 0; ++} ++ ++static int dw_hdmi_ctrl_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, dw_hdmi_ctrl_show, inode->i_private); ++} ++ ++static ssize_t ++dw_hdmi_ctrl_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct dw_hdmi_qp *hdmi = ++ ((struct seq_file *)file->private_data)->private; ++ u32 reg, val; ++ char kbuf[25]; ++ ++ if (count > 24) { ++ dev_err(hdmi->dev, "out of buf range\n"); ++ return count; ++ } ++ ++ if (copy_from_user(kbuf, buf, count)) ++ return -EFAULT; ++ kbuf[count - 1] = '\0'; ++ ++ if (sscanf(kbuf, "%x %x", ®, &val) == -1) ++ return -EFAULT; ++ if (reg > EARCRX_1_INT_FORCE) { ++ dev_err(hdmi->dev, "it is no a hdmi register\n"); ++ return count; ++ } ++ dev_info(hdmi->dev, "/**********hdmi register config******/"); ++ dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val); ++ hdmi_writel(hdmi, val, reg); ++ return count; ++} ++ ++static const struct file_operations dw_hdmi_ctrl_fops = { ++ .owner = THIS_MODULE, ++ .open = dw_hdmi_ctrl_open, ++ .read = seq_read, ++ .write = dw_hdmi_ctrl_write, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static int dw_hdmi_status_show(struct seq_file *s, void *v) ++{ ++ struct dw_hdmi_qp *hdmi = s->private; ++ u32 val; ++ ++ seq_puts(s, "PHY: "); ++ if (hdmi->disabled) { ++ seq_puts(s, "disabled\n"); ++ return 0; ++ } ++ seq_puts(s, "enabled\t\t\tMode: "); ++ if (hdmi->sink_is_hdmi) ++ seq_puts(s, "HDMI\n"); ++ else ++ seq_puts(s, "DVI\n"); ++ ++ if (hdmi->hdmi_data.video_mode.mpixelclock > 600000000) { ++ seq_printf(s, "FRL Mode Pixel Clk: %luHz\n", ++ hdmi->hdmi_data.video_mode.mpixelclock); ++ } else { ++ if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) ++ val = hdmi->hdmi_data.video_mode.mtmdsclock / 4; ++ else ++ val = hdmi->hdmi_data.video_mode.mtmdsclock; ++ seq_printf(s, "TMDS Mode Pixel Clk: %luHz\t\tTMDS Clk: %uHz\n", ++ hdmi->hdmi_data.video_mode.mpixelclock, val); ++ } ++ ++ seq_puts(s, "Color Format: "); ++ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) ++ seq_puts(s, "RGB"); ++ else if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) ++ seq_puts(s, "YUV444"); ++ else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) ++ seq_puts(s, "YUV422"); ++ else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) ++ seq_puts(s, "YUV420"); ++ else ++ seq_puts(s, "UNKNOWN"); ++ val = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); ++ seq_printf(s, "\t\tColor Depth: %d bit\n", val); ++ seq_puts(s, "Colorimetry: "); ++ switch (hdmi->hdmi_data.enc_out_encoding) { ++ case V4L2_YCBCR_ENC_601: ++ seq_puts(s, "ITU.BT601"); ++ break; ++ case V4L2_YCBCR_ENC_709: ++ seq_puts(s, "ITU.BT709"); ++ break; ++ case V4L2_YCBCR_ENC_BT2020: ++ seq_puts(s, "ITU.BT2020"); ++ break; ++ default: /* Carries no data */ ++ seq_puts(s, "ITU.BT601"); ++ break; ++ } ++ ++ seq_puts(s, "\t\tEOTF: "); ++ ++ val = hdmi_readl(hdmi, PKTSCHED_PKT_EN); ++ if (!(val & PKTSCHED_DRMI_TX_EN)) { ++ seq_puts(s, "Off\n"); ++ return 0; ++ } ++ ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS1); ++ val = (val >> 8) & 0x7; ++ switch (val) { ++ case HDMI_EOTF_TRADITIONAL_GAMMA_SDR: ++ seq_puts(s, "SDR"); ++ break; ++ case HDMI_EOTF_TRADITIONAL_GAMMA_HDR: ++ seq_puts(s, "HDR"); ++ break; ++ case HDMI_EOTF_SMPTE_ST2084: ++ seq_puts(s, "ST2084"); ++ break; ++ case HDMI_EOTF_BT_2100_HLG: ++ seq_puts(s, "HLG"); ++ break; ++ default: ++ seq_puts(s, "Not Defined\n"); ++ return 0; ++ } ++ ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS1); ++ val = (val >> 16) & 0xffff; ++ seq_printf(s, "\nx0: %d", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS2); ++ val = val & 0xffff; ++ seq_printf(s, "\t\t\t\ty0: %d\n", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS2); ++ val = (val >> 16) & 0xffff; ++ seq_printf(s, "x1: %d", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS3); ++ val = val & 0xffff; ++ seq_printf(s, "\t\t\t\ty1: %d\n", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS3); ++ val = (val >> 16) & 0xffff; ++ seq_printf(s, "x2: %d", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS4); ++ val = val & 0xffff; ++ seq_printf(s, "\t\t\t\ty2: %d\n", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS4); ++ val = (val >> 16) & 0xffff; ++ seq_printf(s, "white x: %d", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS5); ++ val = val & 0xffff; ++ seq_printf(s, "\t\t\twhite y: %d\n", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS5); ++ val = (val >> 16) & 0xffff; ++ seq_printf(s, "max lum: %d", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS6); ++ val = val & 0xffff; ++ seq_printf(s, "\t\t\tmin lum: %d\n", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS6); ++ val = (val >> 16) & 0xffff; ++ seq_printf(s, "max cll: %d", val); ++ val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS7); ++ val = val & 0xffff; ++ seq_printf(s, "\t\t\tmax fall: %d\n", val); ++ return 0; ++} ++ ++static int dw_hdmi_status_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, dw_hdmi_status_show, inode->i_private); ++} ++ ++static const struct file_operations dw_hdmi_status_fops = { ++ .owner = THIS_MODULE, ++ .open = dw_hdmi_status_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static void dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi_qp *hdmi) ++{ ++ u8 buf[11]; ++ ++ snprintf(buf, sizeof(buf), "dw-hdmi%d", hdmi->plat_data->id); ++ hdmi->debugfs_dir = debugfs_create_dir(buf, NULL); ++ if (IS_ERR(hdmi->debugfs_dir)) { ++ dev_err(dev, "failed to create debugfs dir!\n"); ++ return; ++ } ++ ++ debugfs_create_file("status", 0400, hdmi->debugfs_dir, ++ hdmi, &dw_hdmi_status_fops); ++ debugfs_create_file("ctrl", 0600, hdmi->debugfs_dir, ++ hdmi, &dw_hdmi_ctrl_fops); ++} ++ ++static struct dw_hdmi_qp * ++__dw_hdmi_probe(struct platform_device *pdev, ++ const struct dw_hdmi_plat_data *plat_data) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct device_node *ddc_node; ++ struct dw_hdmi_qp *hdmi; ++ struct resource *iores = NULL; ++ int irq; ++ int ret; ++ ++ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); ++ if (!hdmi) ++ return ERR_PTR(-ENOMEM); ++ ++ hdmi->connector.stereo_allowed = 1; ++ hdmi->plat_data = plat_data; ++ hdmi->dev = dev; ++ hdmi->disabled = true; ++ ++ mutex_init(&hdmi->mutex); ++ ++ ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); ++ if (ddc_node) { ++ hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); ++ of_node_put(ddc_node); ++ if (!hdmi->ddc) { ++ dev_dbg(hdmi->dev, "failed to read ddc node\n"); ++ return ERR_PTR(-EPROBE_DEFER); ++ } ++ ++ } else { ++ dev_dbg(hdmi->dev, "no ddc property found\n"); ++ } ++ ++ if (!plat_data->regm) { ++ const struct regmap_config *reg_config; ++ ++ reg_config = &hdmi_regmap_config; ++ ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ hdmi->regs = devm_ioremap_resource(dev, iores); ++ if (IS_ERR(hdmi->regs)) { ++ ret = PTR_ERR(hdmi->regs); ++ goto err_res; ++ } ++ ++ hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); ++ if (IS_ERR(hdmi->regm)) { ++ dev_err(dev, "Failed to configure regmap\n"); ++ ret = PTR_ERR(hdmi->regm); ++ goto err_res; ++ } ++ } else { ++ hdmi->regm = plat_data->regm; ++ } ++ ++ ret = dw_hdmi_detect_phy(hdmi); ++ if (ret < 0) ++ goto err_res; ++ ++ hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); ++ hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); ++ hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); ++ if ((hdmi_readl(hdmi, CMU_STATUS) & DISPLAY_CLK_MONITOR) == DISPLAY_CLK_LOCKED) { ++ hdmi->initialized = true; ++ hdmi->disabled = false; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ ret = irq; ++ goto err_res; ++ } ++ ++ hdmi->avp_irq = irq; ++ ret = devm_request_threaded_irq(dev, hdmi->avp_irq, ++ dw_hdmi_qp_avp_hardirq, ++ dw_hdmi_qp_avp_irq, IRQF_SHARED, ++ dev_name(dev), hdmi); ++ if (ret) ++ goto err_res; ++ ++ irq = platform_get_irq(pdev, 1); ++ if (irq < 0) { ++ ret = irq; ++ goto err_res; ++ } ++ ++ irq = platform_get_irq(pdev, 2); ++ if (irq < 0) { ++ ret = irq; ++ goto err_res; ++ } ++ ++ hdmi->earc_irq = irq; ++ ret = devm_request_threaded_irq(dev, hdmi->earc_irq, ++ dw_hdmi_qp_earc_hardirq, ++ dw_hdmi_qp_earc_irq, IRQF_SHARED, ++ dev_name(dev), hdmi); ++ if (ret) ++ goto err_res; ++ ++ irq = platform_get_irq(pdev, 3); ++ if (irq < 0) { ++ ret = irq; ++ goto err_res; ++ } ++ ++ hdmi->main_irq = irq; ++ ret = devm_request_threaded_irq(dev, hdmi->main_irq, ++ dw_hdmi_qp_main_hardirq, NULL, ++ IRQF_SHARED, dev_name(dev), hdmi); ++ if (ret) ++ goto err_res; ++ ++ /* If DDC bus is not specified, try to register HDMI I2C bus */ ++ if (!hdmi->ddc) { ++ hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); ++ if (IS_ERR(hdmi->ddc)) ++ hdmi->ddc = NULL; ++ /* ++ * Read high and low time from device tree. If not available use ++ * the default timing scl clock rate is about 99.6KHz. ++ */ ++ if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns", ++ &hdmi->i2c->scl_high_ns)) ++ hdmi->i2c->scl_high_ns = 4708; ++ if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns", ++ &hdmi->i2c->scl_low_ns)) ++ hdmi->i2c->scl_low_ns = 4916; ++ } ++ ++ hdmi->bridge.driver_private = hdmi; ++ hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; ++#ifdef CONFIG_OF ++ hdmi->bridge.of_node = pdev->dev.of_node; ++#endif ++ ++ if (hdmi->phy.ops->setup_hpd) ++ hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); ++ ++ hdmi->connector.ycbcr_420_allowed = hdmi->plat_data->ycbcr_420_allowed; ++ ++ hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, dw_hdmi_cable); ++ if (IS_ERR(hdmi->extcon)) { ++ dev_err(hdmi->dev, "allocate extcon failed\n"); ++ ret = PTR_ERR(hdmi->extcon); ++ goto err_res; ++ } ++ ++ ret = devm_extcon_dev_register(hdmi->dev, hdmi->extcon); ++ if (ret) { ++ dev_err(hdmi->dev, "failed to register extcon: %d\n", ret); ++ goto err_res; ++ } ++ ++ ret = extcon_set_property_capability(hdmi->extcon, EXTCON_DISP_HDMI, ++ EXTCON_PROP_DISP_HPD); ++ if (ret) { ++ dev_err(hdmi->dev, ++ "failed to set USB property capability: %d\n", ret); ++ goto err_res; ++ } ++ ++ /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ ++ if (hdmi->i2c) ++ dw_hdmi_i2c_init(hdmi); ++ ++ init_completion(&hdmi->flt_cmp); ++ init_completion(&hdmi->earc_cmp); ++ ++ if (of_property_read_bool(np, "scramble-low-rates")) ++ hdmi->scramble_low_rates = true; ++ ++ dw_hdmi_register_debugfs(dev, hdmi); ++ ++ return hdmi; ++ ++err_res: ++ if (hdmi->i2c) ++ i2c_del_adapter(&hdmi->i2c->adap); ++ else ++ i2c_put_adapter(hdmi->ddc); ++ ++ return ERR_PTR(ret); ++} ++ ++static void __dw_hdmi_remove(struct dw_hdmi_qp *hdmi) ++{ ++ if (hdmi->avp_irq) ++ disable_irq(hdmi->avp_irq); ++ ++ if (hdmi->main_irq) ++ disable_irq(hdmi->main_irq); ++ ++ if (hdmi->earc_irq) ++ disable_irq(hdmi->earc_irq); ++ ++ debugfs_remove_recursive(hdmi->debugfs_dir); ++ ++ if (!hdmi->plat_data->first_screen) { ++ dw_hdmi_destroy_properties(hdmi); ++ hdmi->connector.funcs->destroy(&hdmi->connector); ++ } ++ ++ if (hdmi->audio && !IS_ERR(hdmi->audio)) ++ platform_device_unregister(hdmi->audio); ++ ++ // [CC:] dw_hdmi_rockchip_unbind() also calls drm_encoder_cleanup() ++ // and causes a seg fault due to NULL ptr dererence ++ // if (hdmi->bridge.encoder && !hdmi->plat_data->first_screen) ++ // hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder); ++ // ++ if (!IS_ERR(hdmi->cec)) ++ platform_device_unregister(hdmi->cec); ++ if (hdmi->i2c) ++ i2c_del_adapter(&hdmi->i2c->adap); ++ else ++ i2c_put_adapter(hdmi->ddc); ++} ++ ++/* ----------------------------------------------------------------------------- ++ * Bind/unbind API, used from platforms based on the component framework. ++ */ ++struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, ++ struct drm_encoder *encoder, ++ struct dw_hdmi_plat_data *plat_data) ++{ ++ struct dw_hdmi_qp *hdmi; ++ int ret; ++ ++ hdmi = __dw_hdmi_probe(pdev, plat_data); ++ if (IS_ERR(hdmi)) ++ return hdmi; ++ ++ if (!plat_data->first_screen) { ++ ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); ++ if (ret) { ++ __dw_hdmi_remove(hdmi); ++ dev_err(hdmi->dev, "Failed to initialize bridge with drm\n"); ++ return ERR_PTR(ret); ++ } ++ ++ plat_data->connector = &hdmi->connector; ++ } ++ ++ if (plat_data->split_mode && !hdmi->plat_data->first_screen) { ++ struct dw_hdmi_qp *secondary = NULL; ++ ++ if (hdmi->plat_data->left) ++ secondary = hdmi->plat_data->left; ++ else if (hdmi->plat_data->right) ++ secondary = hdmi->plat_data->right; ++ ++ if (!secondary) ++ return ERR_PTR(-ENOMEM); ++ ret = drm_bridge_attach(encoder, &secondary->bridge, &hdmi->bridge, ++ DRM_BRIDGE_ATTACH_NO_CONNECTOR); ++ if (ret) ++ return ERR_PTR(ret); ++ } ++ ++ return hdmi; ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind); ++ ++void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi) ++{ ++ __dw_hdmi_remove(hdmi); ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_qp_unbind); ++ ++void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi) ++{ ++ if (!hdmi) { ++ dev_warn(dev, "Hdmi has not been initialized\n"); ++ return; ++ } ++ ++ mutex_lock(&hdmi->mutex); ++ ++ /* ++ * When system shutdown, hdmi should be disabled. ++ * When system suspend, dw_hdmi_qp_bridge_disable will disable hdmi first. ++ * To prevent duplicate operation, we should determine whether hdmi ++ * has been disabled. ++ */ ++ if (!hdmi->disabled) ++ hdmi->disabled = true; ++ mutex_unlock(&hdmi->mutex); ++ ++ if (hdmi->avp_irq) ++ disable_irq(hdmi->avp_irq); ++ ++ if (hdmi->main_irq) ++ disable_irq(hdmi->main_irq); ++ ++ if (hdmi->earc_irq) ++ disable_irq(hdmi->earc_irq); ++ ++ pinctrl_pm_select_sleep_state(dev); ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend); ++ ++void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) ++{ ++ if (!hdmi) { ++ dev_warn(dev, "Hdmi has not been initialized\n"); ++ return; ++ } ++ ++ hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); ++ hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); ++ hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); ++ ++ pinctrl_pm_select_default_state(dev); ++ ++ mutex_lock(&hdmi->mutex); ++ if (hdmi->i2c) ++ dw_hdmi_i2c_init(hdmi); ++ if (hdmi->avp_irq) ++ enable_irq(hdmi->avp_irq); ++ ++ if (hdmi->main_irq) ++ enable_irq(hdmi->main_irq); ++ ++ if (hdmi->earc_irq) ++ enable_irq(hdmi->earc_irq); ++ ++ mutex_unlock(&hdmi->mutex); ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume); ++ ++MODULE_AUTHOR("Algea Cao "); ++MODULE_DESCRIPTION("DW HDMI QP transmitter driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:dw-hdmi-qp"); +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h +@@ -0,0 +1,831 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) Rockchip Electronics Co.Ltd ++ * Author: ++ * Algea Cao ++ */ ++#ifndef __DW_HDMI_QP_H__ ++#define __DW_HDMI_QP_H__ ++/* Main Unit Registers */ ++#define CORE_ID 0x0 ++#define VER_NUMBER 0x4 ++#define VER_TYPE 0x8 ++#define CONFIG_REG 0xc ++#define CONFIG_CEC BIT(28) ++#define CONFIG_AUD_UD BIT(23) ++#define CORE_TIMESTAMP_HHMM 0x14 ++#define CORE_TIMESTAMP_MMDD 0x18 ++#define CORE_TIMESTAMP_YYYY 0x1c ++/* Reset Manager Registers */ ++#define GLOBAL_SWRESET_REQUEST 0x40 ++#define EARCRX_CMDC_SWINIT_P BIT(27) ++#define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P BIT(10) ++#define GLOBAL_SWDISABLE 0x44 ++#define CEC_SWDISABLE BIT(17) ++#define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE BIT(10) ++#define AVP_DATAPATH_VIDEO_SWDISABLE BIT(6) ++#define RESET_MANAGER_CONFIG0 0x48 ++#define RESET_MANAGER_STATUS0 0x50 ++#define RESET_MANAGER_STATUS1 0x54 ++#define RESET_MANAGER_STATUS2 0x58 ++/* Timer Base Registers */ ++#define TIMER_BASE_CONFIG0 0x80 ++#define TIMER_BASE_STATUS0 0x84 ++/* CMU Registers */ ++#define CMU_CONFIG0 0xa0 ++#define CMU_CONFIG1 0xa4 ++#define CMU_CONFIG2 0xa8 ++#define CMU_CONFIG3 0xac ++#define CMU_STATUS 0xb0 ++#define DISPLAY_CLK_MONITOR 0x3f ++#define DISPLAY_CLK_LOCKED 0X15 ++#define EARC_BPCLK_OFF BIT(9) ++#define AUDCLK_OFF BIT(7) ++#define LINKQPCLK_OFF BIT(5) ++#define VIDQPCLK_OFF BIT(3) ++#define IPI_CLK_OFF BIT(1) ++#define CMU_IPI_CLK_FREQ 0xb4 ++#define CMU_VIDQPCLK_FREQ 0xb8 ++#define CMU_LINKQPCLK_FREQ 0xbc ++#define CMU_AUDQPCLK_FREQ 0xc0 ++#define CMU_EARC_BPCLK_FREQ 0xc4 ++/* I2CM Registers */ ++#define I2CM_SM_SCL_CONFIG0 0xe0 ++#define I2CM_FM_SCL_CONFIG0 0xe4 ++#define I2CM_CONFIG0 0xe8 ++#define I2CM_CONTROL0 0xec ++#define I2CM_STATUS0 0xf0 ++#define I2CM_INTERFACE_CONTROL0 0xf4 ++#define I2CM_ADDR 0xff000 ++#define I2CM_SLVADDR 0xfe0 ++#define I2CM_WR_MASK 0x1e ++#define I2CM_EXT_READ BIT(4) ++#define I2CM_SHORT_READ BIT(3) ++#define I2CM_FM_READ BIT(2) ++#define I2CM_FM_WRITE BIT(1) ++#define I2CM_FM_EN BIT(0) ++#define I2CM_INTERFACE_CONTROL1 0xf8 ++#define I2CM_SEG_PTR 0x7f80 ++#define I2CM_SEG_ADDR 0x7f ++#define I2CM_INTERFACE_WRDATA_0_3 0xfc ++#define I2CM_INTERFACE_WRDATA_4_7 0x100 ++#define I2CM_INTERFACE_WRDATA_8_11 0x104 ++#define I2CM_INTERFACE_WRDATA_12_15 0x108 ++#define I2CM_INTERFACE_RDDATA_0_3 0x10c ++#define I2CM_INTERFACE_RDDATA_4_7 0x110 ++#define I2CM_INTERFACE_RDDATA_8_11 0x114 ++#define I2CM_INTERFACE_RDDATA_12_15 0x118 ++/* SCDC Registers */ ++#define SCDC_CONFIG0 0x140 ++#define SCDC_I2C_FM_EN BIT(12) ++#define SCDC_UPD_FLAGS_AUTO_CLR BIT(6) ++#define SCDC_UPD_FLAGS_POLL_EN BIT(4) ++#define SCDC_CONTROL0 0x148 ++#define SCDC_STATUS0 0x150 ++#define STATUS_UPDATE BIT(0) ++#define FRL_START BIT(4) ++#define FLT_UPDATE BIT(5) ++/* FLT Registers */ ++#define FLT_CONFIG0 0x160 ++#define FLT_CONFIG1 0x164 ++#define FLT_CONFIG2 0x168 ++#define FLT_CONTROL0 0x170 ++/* Main Unit 2 Registers */ ++#define MAINUNIT_STATUS0 0x180 ++/* Video Interface Registers */ ++#define VIDEO_INTERFACE_CONFIG0 0x800 ++#define VIDEO_INTERFACE_CONFIG1 0x804 ++#define VIDEO_INTERFACE_CONFIG2 0x808 ++#define VIDEO_INTERFACE_CONTROL0 0x80c ++#define VIDEO_INTERFACE_STATUS0 0x814 ++/* Video Packing Registers */ ++#define VIDEO_PACKING_CONFIG0 0x81c ++/* Audio Interface Registers */ ++#define AUDIO_INTERFACE_CONFIG0 0x820 ++#define AUD_IF_SEL_MSK 0x3 ++#define AUD_IF_SPDIF 0x2 ++#define AUD_IF_I2S 0x1 ++#define AUD_IF_PAI 0x0 ++#define AUD_FIFO_INIT_ON_OVF_MSK BIT(2) ++#define AUD_FIFO_INIT_ON_OVF_EN BIT(2) ++#define I2S_LINES_EN_MSK GENMASK(7, 4) ++#define I2S_LINES_EN(x) BIT(x + 4) ++#define I2S_BPCUV_RCV_MSK BIT(12) ++#define I2S_BPCUV_RCV_EN BIT(12) ++#define I2S_BPCUV_RCV_DIS 0 ++#define SPDIF_LINES_EN GENMASK(19, 16) ++#define AUD_FORMAT_MSK GENMASK(26, 24) ++#define AUD_3DOBA (0x7 << 24) ++#define AUD_3DASP (0x6 << 24) ++#define AUD_MSOBA (0x5 << 24) ++#define AUD_MSASP (0x4 << 24) ++#define AUD_HBR (0x3 << 24) ++#define AUD_DST (0x2 << 24) ++#define AUD_OBA (0x1 << 24) ++#define AUD_ASP (0x0 << 24) ++#define AUDIO_INTERFACE_CONFIG1 0x824 ++#define AUDIO_INTERFACE_CONTROL0 0x82c ++#define AUDIO_FIFO_CLR_P BIT(0) ++#define AUDIO_INTERFACE_STATUS0 0x834 ++/* Frame Composer Registers */ ++#define FRAME_COMPOSER_CONFIG0 0x840 ++#define FRAME_COMPOSER_CONFIG1 0x844 ++#define FRAME_COMPOSER_CONFIG2 0x848 ++#define FRAME_COMPOSER_CONFIG3 0x84c ++#define FRAME_COMPOSER_CONFIG4 0x850 ++#define FRAME_COMPOSER_CONFIG5 0x854 ++#define FRAME_COMPOSER_CONFIG6 0x858 ++#define FRAME_COMPOSER_CONFIG7 0x85c ++#define FRAME_COMPOSER_CONFIG8 0x860 ++#define FRAME_COMPOSER_CONFIG9 0x864 ++#define FRAME_COMPOSER_CONTROL0 0x86c ++/* Video Monitor Registers */ ++#define VIDEO_MONITOR_CONFIG0 0x880 ++#define VIDEO_MONITOR_STATUS0 0x884 ++#define VIDEO_MONITOR_STATUS1 0x888 ++#define VIDEO_MONITOR_STATUS2 0x88c ++#define VIDEO_MONITOR_STATUS3 0x890 ++#define VIDEO_MONITOR_STATUS4 0x894 ++#define VIDEO_MONITOR_STATUS5 0x898 ++#define VIDEO_MONITOR_STATUS6 0x89c ++/* HDCP2 Logic Registers */ ++#define HDCP2LOGIC_CONFIG0 0x8e0 ++#define HDCP2_BYPASS BIT(0) ++#define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 ++#define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 ++/* HDCP14 Registers */ ++#define HDCP14_CONFIG0 0x900 ++#define HDCP14_CONFIG1 0x904 ++#define HDCP14_CONFIG2 0x908 ++#define HDCP14_CONFIG3 0x90c ++#define HDCP14_KEY_SEED 0x914 ++#define HDCP14_KEY_H 0x918 ++#define HDCP14_KEY_L 0x91c ++#define HDCP14_KEY_STATUS 0x920 ++#define HDCP14_AKSV_H 0x924 ++#define HDCP14_AKSV_L 0x928 ++#define HDCP14_AN_H 0x92c ++#define HDCP14_AN_L 0x930 ++#define HDCP14_STATUS0 0x934 ++#define HDCP14_STATUS1 0x938 ++/* Scrambler Registers */ ++#define SCRAMB_CONFIG0 0x960 ++/* Video Configuration Registers */ ++#define LINK_CONFIG0 0x968 ++#define OPMODE_FRL_4LANES BIT(8) ++#define OPMODE_DVI BIT(4) ++#define OPMODE_FRL BIT(0) ++/* TMDS FIFO Registers */ ++#define TMDS_FIFO_CONFIG0 0x970 ++#define TMDS_FIFO_CONTROL0 0x974 ++/* FRL RSFEC Registers */ ++#define FRL_RSFEC_CONFIG0 0xa20 ++#define FRL_RSFEC_STATUS0 0xa30 ++/* FRL Packetizer Registers */ ++#define FRL_PKTZ_CONFIG0 0xa40 ++#define FRL_PKTZ_CONTROL0 0xa44 ++#define FRL_PKTZ_CONTROL1 0xa50 ++#define FRL_PKTZ_STATUS1 0xa54 ++/* Packet Scheduler Registers */ ++#define PKTSCHED_CONFIG0 0xa80 ++#define PKTSCHED_PRQUEUE0_CONFIG0 0xa84 ++#define PKTSCHED_PRQUEUE1_CONFIG0 0xa88 ++#define PKTSCHED_PRQUEUE2_CONFIG0 0xa8c ++#define PKTSCHED_PRQUEUE2_CONFIG1 0xa90 ++#define PKTSCHED_PRQUEUE2_CONFIG2 0xa94 ++#define PKTSCHED_PKT_CONFIG0 0xa98 ++#define PKTSCHED_PKT_CONFIG1 0xa9c ++#define PKTSCHED_DRMI_FIELDRATE BIT(13) ++#define PKTSCHED_AVI_FIELDRATE BIT(12) ++#define PKTSCHED_PKT_CONFIG2 0xaa0 ++#define PKTSCHED_PKT_CONFIG3 0xaa4 ++#define PKTSCHED_PKT_EN 0xaa8 ++#define PKTSCHED_DRMI_TX_EN BIT(17) ++#define PKTSCHED_AUDI_TX_EN BIT(15) ++#define PKTSCHED_AVI_TX_EN BIT(13) ++#define PKTSCHED_EMP_CVTEM_TX_EN BIT(10) ++#define PKTSCHED_AMD_TX_EN BIT(8) ++#define PKTSCHED_GCP_TX_EN BIT(3) ++#define PKTSCHED_AUDS_TX_EN BIT(2) ++#define PKTSCHED_ACR_TX_EN BIT(1) ++#define PKTSCHED_NULL_TX_EN BIT(0) ++#define PKTSCHED_PKT_CONTROL0 0xaac ++#define PKTSCHED_PKT_SEND 0xab0 ++#define PKTSCHED_PKT_STATUS0 0xab4 ++#define PKTSCHED_PKT_STATUS1 0xab8 ++#define PKT_NULL_CONTENTS0 0xb00 ++#define PKT_NULL_CONTENTS1 0xb04 ++#define PKT_NULL_CONTENTS2 0xb08 ++#define PKT_NULL_CONTENTS3 0xb0c ++#define PKT_NULL_CONTENTS4 0xb10 ++#define PKT_NULL_CONTENTS5 0xb14 ++#define PKT_NULL_CONTENTS6 0xb18 ++#define PKT_NULL_CONTENTS7 0xb1c ++#define PKT_ACP_CONTENTS0 0xb20 ++#define PKT_ACP_CONTENTS1 0xb24 ++#define PKT_ACP_CONTENTS2 0xb28 ++#define PKT_ACP_CONTENTS3 0xb2c ++#define PKT_ACP_CONTENTS4 0xb30 ++#define PKT_ACP_CONTENTS5 0xb34 ++#define PKT_ACP_CONTENTS6 0xb38 ++#define PKT_ACP_CONTENTS7 0xb3c ++#define PKT_ISRC1_CONTENTS0 0xb40 ++#define PKT_ISRC1_CONTENTS1 0xb44 ++#define PKT_ISRC1_CONTENTS2 0xb48 ++#define PKT_ISRC1_CONTENTS3 0xb4c ++#define PKT_ISRC1_CONTENTS4 0xb50 ++#define PKT_ISRC1_CONTENTS5 0xb54 ++#define PKT_ISRC1_CONTENTS6 0xb58 ++#define PKT_ISRC1_CONTENTS7 0xb5c ++#define PKT_ISRC2_CONTENTS0 0xb60 ++#define PKT_ISRC2_CONTENTS1 0xb64 ++#define PKT_ISRC2_CONTENTS2 0xb68 ++#define PKT_ISRC2_CONTENTS3 0xb6c ++#define PKT_ISRC2_CONTENTS4 0xb70 ++#define PKT_ISRC2_CONTENTS5 0xb74 ++#define PKT_ISRC2_CONTENTS6 0xb78 ++#define PKT_ISRC2_CONTENTS7 0xb7c ++#define PKT_GMD_CONTENTS0 0xb80 ++#define PKT_GMD_CONTENTS1 0xb84 ++#define PKT_GMD_CONTENTS2 0xb88 ++#define PKT_GMD_CONTENTS3 0xb8c ++#define PKT_GMD_CONTENTS4 0xb90 ++#define PKT_GMD_CONTENTS5 0xb94 ++#define PKT_GMD_CONTENTS6 0xb98 ++#define PKT_GMD_CONTENTS7 0xb9c ++#define PKT_AMD_CONTENTS0 0xba0 ++#define PKT_AMD_CONTENTS1 0xba4 ++#define PKT_AMD_CONTENTS2 0xba8 ++#define PKT_AMD_CONTENTS3 0xbac ++#define PKT_AMD_CONTENTS4 0xbb0 ++#define PKT_AMD_CONTENTS5 0xbb4 ++#define PKT_AMD_CONTENTS6 0xbb8 ++#define PKT_AMD_CONTENTS7 0xbbc ++#define PKT_VSI_CONTENTS0 0xbc0 ++#define PKT_VSI_CONTENTS1 0xbc4 ++#define PKT_VSI_CONTENTS2 0xbc8 ++#define PKT_VSI_CONTENTS3 0xbcc ++#define PKT_VSI_CONTENTS4 0xbd0 ++#define PKT_VSI_CONTENTS5 0xbd4 ++#define PKT_VSI_CONTENTS6 0xbd8 ++#define PKT_VSI_CONTENTS7 0xbdc ++#define PKT_AVI_CONTENTS0 0xbe0 ++#define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT BIT(4) ++#define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR 0x04 ++#define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR 0x08 ++#define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 ++#define PKT_AVI_CONTENTS1 0xbe4 ++#define PKT_AVI_CONTENTS2 0xbe8 ++#define PKT_AVI_CONTENTS3 0xbec ++#define PKT_AVI_CONTENTS4 0xbf0 ++#define PKT_AVI_CONTENTS5 0xbf4 ++#define PKT_AVI_CONTENTS6 0xbf8 ++#define PKT_AVI_CONTENTS7 0xbfc ++#define PKT_SPDI_CONTENTS0 0xc00 ++#define PKT_SPDI_CONTENTS1 0xc04 ++#define PKT_SPDI_CONTENTS2 0xc08 ++#define PKT_SPDI_CONTENTS3 0xc0c ++#define PKT_SPDI_CONTENTS4 0xc10 ++#define PKT_SPDI_CONTENTS5 0xc14 ++#define PKT_SPDI_CONTENTS6 0xc18 ++#define PKT_SPDI_CONTENTS7 0xc1c ++#define PKT_AUDI_CONTENTS0 0xc20 ++#define PKT_AUDI_CONTENTS1 0xc24 ++#define PKT_AUDI_CONTENTS2 0xc28 ++#define PKT_AUDI_CONTENTS3 0xc2c ++#define PKT_AUDI_CONTENTS4 0xc30 ++#define PKT_AUDI_CONTENTS5 0xc34 ++#define PKT_AUDI_CONTENTS6 0xc38 ++#define PKT_AUDI_CONTENTS7 0xc3c ++#define PKT_NVI_CONTENTS0 0xc40 ++#define PKT_NVI_CONTENTS1 0xc44 ++#define PKT_NVI_CONTENTS2 0xc48 ++#define PKT_NVI_CONTENTS3 0xc4c ++#define PKT_NVI_CONTENTS4 0xc50 ++#define PKT_NVI_CONTENTS5 0xc54 ++#define PKT_NVI_CONTENTS6 0xc58 ++#define PKT_NVI_CONTENTS7 0xc5c ++#define PKT_DRMI_CONTENTS0 0xc60 ++#define PKT_DRMI_CONTENTS1 0xc64 ++#define PKT_DRMI_CONTENTS2 0xc68 ++#define PKT_DRMI_CONTENTS3 0xc6c ++#define PKT_DRMI_CONTENTS4 0xc70 ++#define PKT_DRMI_CONTENTS5 0xc74 ++#define PKT_DRMI_CONTENTS6 0xc78 ++#define PKT_DRMI_CONTENTS7 0xc7c ++#define PKT_GHDMI1_CONTENTS0 0xc80 ++#define PKT_GHDMI1_CONTENTS1 0xc84 ++#define PKT_GHDMI1_CONTENTS2 0xc88 ++#define PKT_GHDMI1_CONTENTS3 0xc8c ++#define PKT_GHDMI1_CONTENTS4 0xc90 ++#define PKT_GHDMI1_CONTENTS5 0xc94 ++#define PKT_GHDMI1_CONTENTS6 0xc98 ++#define PKT_GHDMI1_CONTENTS7 0xc9c ++#define PKT_GHDMI2_CONTENTS0 0xca0 ++#define PKT_GHDMI2_CONTENTS1 0xca4 ++#define PKT_GHDMI2_CONTENTS2 0xca8 ++#define PKT_GHDMI2_CONTENTS3 0xcac ++#define PKT_GHDMI2_CONTENTS4 0xcb0 ++#define PKT_GHDMI2_CONTENTS5 0xcb4 ++#define PKT_GHDMI2_CONTENTS6 0xcb8 ++#define PKT_GHDMI2_CONTENTS7 0xcbc ++/* EMP Packetizer Registers */ ++#define PKT_EMP_CONFIG0 0xce0 ++#define PKT_EMP_CONTROL0 0xcec ++#define PKT_EMP_CONTROL1 0xcf0 ++#define PKT_EMP_CONTROL2 0xcf4 ++#define PKT_EMP_VTEM_CONTENTS0 0xd00 ++#define PKT_EMP_VTEM_CONTENTS1 0xd04 ++#define PKT_EMP_VTEM_CONTENTS2 0xd08 ++#define PKT_EMP_VTEM_CONTENTS3 0xd0c ++#define PKT_EMP_VTEM_CONTENTS4 0xd10 ++#define PKT_EMP_VTEM_CONTENTS5 0xd14 ++#define PKT_EMP_VTEM_CONTENTS6 0xd18 ++#define PKT_EMP_VTEM_CONTENTS7 0xd1c ++#define PKT0_EMP_CVTEM_CONTENTS0 0xd20 ++#define PKT0_EMP_CVTEM_CONTENTS1 0xd24 ++#define PKT0_EMP_CVTEM_CONTENTS2 0xd28 ++#define PKT0_EMP_CVTEM_CONTENTS3 0xd2c ++#define PKT0_EMP_CVTEM_CONTENTS4 0xd30 ++#define PKT0_EMP_CVTEM_CONTENTS5 0xd34 ++#define PKT0_EMP_CVTEM_CONTENTS6 0xd38 ++#define PKT0_EMP_CVTEM_CONTENTS7 0xd3c ++#define PKT1_EMP_CVTEM_CONTENTS0 0xd40 ++#define PKT1_EMP_CVTEM_CONTENTS1 0xd44 ++#define PKT1_EMP_CVTEM_CONTENTS2 0xd48 ++#define PKT1_EMP_CVTEM_CONTENTS3 0xd4c ++#define PKT1_EMP_CVTEM_CONTENTS4 0xd50 ++#define PKT1_EMP_CVTEM_CONTENTS5 0xd54 ++#define PKT1_EMP_CVTEM_CONTENTS6 0xd58 ++#define PKT1_EMP_CVTEM_CONTENTS7 0xd5c ++#define PKT2_EMP_CVTEM_CONTENTS0 0xd60 ++#define PKT2_EMP_CVTEM_CONTENTS1 0xd64 ++#define PKT2_EMP_CVTEM_CONTENTS2 0xd68 ++#define PKT2_EMP_CVTEM_CONTENTS3 0xd6c ++#define PKT2_EMP_CVTEM_CONTENTS4 0xd70 ++#define PKT2_EMP_CVTEM_CONTENTS5 0xd74 ++#define PKT2_EMP_CVTEM_CONTENTS6 0xd78 ++#define PKT2_EMP_CVTEM_CONTENTS7 0xd7c ++#define PKT3_EMP_CVTEM_CONTENTS0 0xd80 ++#define PKT3_EMP_CVTEM_CONTENTS1 0xd84 ++#define PKT3_EMP_CVTEM_CONTENTS2 0xd88 ++#define PKT3_EMP_CVTEM_CONTENTS3 0xd8c ++#define PKT3_EMP_CVTEM_CONTENTS4 0xd90 ++#define PKT3_EMP_CVTEM_CONTENTS5 0xd94 ++#define PKT3_EMP_CVTEM_CONTENTS6 0xd98 ++#define PKT3_EMP_CVTEM_CONTENTS7 0xd9c ++#define PKT4_EMP_CVTEM_CONTENTS0 0xda0 ++#define PKT4_EMP_CVTEM_CONTENTS1 0xda4 ++#define PKT4_EMP_CVTEM_CONTENTS2 0xda8 ++#define PKT4_EMP_CVTEM_CONTENTS3 0xdac ++#define PKT4_EMP_CVTEM_CONTENTS4 0xdb0 ++#define PKT4_EMP_CVTEM_CONTENTS5 0xdb4 ++#define PKT4_EMP_CVTEM_CONTENTS6 0xdb8 ++#define PKT4_EMP_CVTEM_CONTENTS7 0xdbc ++#define PKT5_EMP_CVTEM_CONTENTS0 0xdc0 ++#define PKT5_EMP_CVTEM_CONTENTS1 0xdc4 ++#define PKT5_EMP_CVTEM_CONTENTS2 0xdc8 ++#define PKT5_EMP_CVTEM_CONTENTS3 0xdcc ++#define PKT5_EMP_CVTEM_CONTENTS4 0xdd0 ++#define PKT5_EMP_CVTEM_CONTENTS5 0xdd4 ++#define PKT5_EMP_CVTEM_CONTENTS6 0xdd8 ++#define PKT5_EMP_CVTEM_CONTENTS7 0xddc ++/* Audio Packetizer Registers */ ++#define AUDPKT_CONTROL0 0xe20 ++#define AUDPKT_PBIT_FORCE_EN_MASK BIT(12) ++#define AUDPKT_PBIT_FORCE_EN BIT(12) ++#define AUDPKT_CHSTATUS_OVR_EN_MASK BIT(0) ++#define AUDPKT_CHSTATUS_OVR_EN BIT(0) ++#define AUDPKT_CONTROL1 0xe24 ++#define AUDPKT_ACR_CONTROL0 0xe40 ++#define AUDPKT_ACR_N_VALUE 0xfffff ++#define AUDPKT_ACR_CONTROL1 0xe44 ++#define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4) ++#define AUDPKT_ACR_CTS_OVR_VAL(x) ((x) << 4) ++#define AUDPKT_ACR_CTS_OVR_EN_MSK BIT(1) ++#define AUDPKT_ACR_CTS_OVR_EN BIT(1) ++#define AUDPKT_ACR_STATUS0 0xe4c ++#define AUDPKT_CHSTATUS_OVR0 0xe60 ++#define AUDPKT_CHSTATUS_OVR1 0xe64 ++/* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */ ++#define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0) ++#define AUDPKT_CHSTATUS_SR_22050 0x4 ++#define AUDPKT_CHSTATUS_SR_24000 0x6 ++#define AUDPKT_CHSTATUS_SR_32000 0x3 ++#define AUDPKT_CHSTATUS_SR_44100 0x0 ++#define AUDPKT_CHSTATUS_SR_48000 0x2 ++#define AUDPKT_CHSTATUS_SR_88200 0x8 ++#define AUDPKT_CHSTATUS_SR_96000 0xa ++#define AUDPKT_CHSTATUS_SR_176400 0xc ++#define AUDPKT_CHSTATUS_SR_192000 0xe ++#define AUDPKT_CHSTATUS_SR_768000 0x9 ++#define AUDPKT_CHSTATUS_SR_NOT_INDICATED 0x1 ++/* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */ ++#define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12) ++#define AUDPKT_CHSTATUS_OSR_8000 0x6 ++#define AUDPKT_CHSTATUS_OSR_11025 0xa ++#define AUDPKT_CHSTATUS_OSR_12000 0x2 ++#define AUDPKT_CHSTATUS_OSR_16000 0x8 ++#define AUDPKT_CHSTATUS_OSR_22050 0xb ++#define AUDPKT_CHSTATUS_OSR_24000 0x9 ++#define AUDPKT_CHSTATUS_OSR_32000 0xc ++#define AUDPKT_CHSTATUS_OSR_44100 0xf ++#define AUDPKT_CHSTATUS_OSR_48000 0xd ++#define AUDPKT_CHSTATUS_OSR_88200 0x7 ++#define AUDPKT_CHSTATUS_OSR_96000 0x5 ++#define AUDPKT_CHSTATUS_OSR_176400 0x3 ++#define AUDPKT_CHSTATUS_OSR_192000 0x1 ++#define AUDPKT_CHSTATUS_OSR_NOT_INDICATED 0x0 ++#define AUDPKT_CHSTATUS_OVR2 0xe68 ++#define AUDPKT_CHSTATUS_OVR3 0xe6c ++#define AUDPKT_CHSTATUS_OVR4 0xe70 ++#define AUDPKT_CHSTATUS_OVR5 0xe74 ++#define AUDPKT_CHSTATUS_OVR6 0xe78 ++#define AUDPKT_CHSTATUS_OVR7 0xe7c ++#define AUDPKT_CHSTATUS_OVR8 0xe80 ++#define AUDPKT_CHSTATUS_OVR9 0xe84 ++#define AUDPKT_CHSTATUS_OVR10 0xe88 ++#define AUDPKT_CHSTATUS_OVR11 0xe8c ++#define AUDPKT_CHSTATUS_OVR12 0xe90 ++#define AUDPKT_CHSTATUS_OVR13 0xe94 ++#define AUDPKT_CHSTATUS_OVR14 0xe98 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC0 0xea0 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC1 0xea4 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC2 0xea8 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC3 0xeac ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC4 0xeb0 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC5 0xeb4 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC6 0xeb8 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC7 0xebc ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC8 0xec0 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC9 0xec4 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC10 0xec8 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC11 0xecc ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC12 0xed0 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC13 0xed4 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC14 0xed8 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC15 0xedc ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC16 0xee0 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC17 0xee4 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC18 0xee8 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC19 0xeec ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC20 0xef0 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC21 0xef4 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC22 0xef8 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC23 0xefc ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC24 0xf00 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC25 0xf04 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC26 0xf08 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC27 0xf0c ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC28 0xf10 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC29 0xf14 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC30 0xf18 ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC31 0xf1c ++#define AUDPKT_USRDATA_OVR_MSG_GENERIC32 0xf20 ++#define AUDPKT_VBIT_OVR0 0xf24 ++/* CEC Registers */ ++#define CEC_TX_CONTROL 0x1000 ++#define CEC_STATUS 0x1004 ++#define CEC_CONFIG 0x1008 ++#define CEC_ADDR 0x100c ++#define CEC_TX_COUNT 0x1020 ++#define CEC_TX_DATA3_0 0x1024 ++#define CEC_TX_DATA7_4 0x1028 ++#define CEC_TX_DATA11_8 0x102c ++#define CEC_TX_DATA15_12 0x1030 ++#define CEC_RX_COUNT_STATUS 0x1040 ++#define CEC_RX_DATA3_0 0x1044 ++#define CEC_RX_DATA7_4 0x1048 ++#define CEC_RX_DATA11_8 0x104c ++#define CEC_RX_DATA15_12 0x1050 ++#define CEC_LOCK_CONTROL 0x1054 ++#define CEC_RXQUAL_BITTIME_CONFIG 0x1060 ++#define CEC_RX_BITTIME_CONFIG 0x1064 ++#define CEC_TX_BITTIME_CONFIG 0x1068 ++/* eARC RX CMDC Registers */ ++#define EARCRX_CMDC_CONFIG0 0x1800 ++#define EARCRX_XACTREAD_STOP_CFG BIT(26) ++#define EARCRX_XACTREAD_RETRY_CFG BIT(25) ++#define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 BIT(24) ++#define EARCRX_CMDC_XACT_RESTART_EN BIT(18) ++#define EARCRX_CMDC_CONFIG1 0x1804 ++#define EARCRX_CMDC_CONTROL 0x1808 ++#define EARCRX_CMDC_HEARTBEAT_LOSS_EN BIT(4) ++#define EARCRX_CMDC_DISCOVERY_EN BIT(3) ++#define EARCRX_CONNECTOR_HPD BIT(1) ++#define EARCRX_CMDC_WHITELIST0_CONFIG 0x180c ++#define EARCRX_CMDC_WHITELIST1_CONFIG 0x1810 ++#define EARCRX_CMDC_WHITELIST2_CONFIG 0x1814 ++#define EARCRX_CMDC_WHITELIST3_CONFIG 0x1818 ++#define EARCRX_CMDC_STATUS 0x181c ++#define EARCRX_CMDC_XACT_INFO 0x1820 ++#define EARCRX_CMDC_XACT_ACTION 0x1824 ++#define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE 0x1828 ++#define EARCRX_CMDC_HEARTBEAT_STATUS 0x182c ++#define EARCRX_CMDC_XACT_WR0 0x1840 ++#define EARCRX_CMDC_XACT_WR1 0x1844 ++#define EARCRX_CMDC_XACT_WR2 0x1848 ++#define EARCRX_CMDC_XACT_WR3 0x184c ++#define EARCRX_CMDC_XACT_WR4 0x1850 ++#define EARCRX_CMDC_XACT_WR5 0x1854 ++#define EARCRX_CMDC_XACT_WR6 0x1858 ++#define EARCRX_CMDC_XACT_WR7 0x185c ++#define EARCRX_CMDC_XACT_WR8 0x1860 ++#define EARCRX_CMDC_XACT_WR9 0x1864 ++#define EARCRX_CMDC_XACT_WR10 0x1868 ++#define EARCRX_CMDC_XACT_WR11 0x186c ++#define EARCRX_CMDC_XACT_WR12 0x1870 ++#define EARCRX_CMDC_XACT_WR13 0x1874 ++#define EARCRX_CMDC_XACT_WR14 0x1878 ++#define EARCRX_CMDC_XACT_WR15 0x187c ++#define EARCRX_CMDC_XACT_WR16 0x1880 ++#define EARCRX_CMDC_XACT_WR17 0x1884 ++#define EARCRX_CMDC_XACT_WR18 0x1888 ++#define EARCRX_CMDC_XACT_WR19 0x188c ++#define EARCRX_CMDC_XACT_WR20 0x1890 ++#define EARCRX_CMDC_XACT_WR21 0x1894 ++#define EARCRX_CMDC_XACT_WR22 0x1898 ++#define EARCRX_CMDC_XACT_WR23 0x189c ++#define EARCRX_CMDC_XACT_WR24 0x18a0 ++#define EARCRX_CMDC_XACT_WR25 0x18a4 ++#define EARCRX_CMDC_XACT_WR26 0x18a8 ++#define EARCRX_CMDC_XACT_WR27 0x18ac ++#define EARCRX_CMDC_XACT_WR28 0x18b0 ++#define EARCRX_CMDC_XACT_WR29 0x18b4 ++#define EARCRX_CMDC_XACT_WR30 0x18b8 ++#define EARCRX_CMDC_XACT_WR31 0x18bc ++#define EARCRX_CMDC_XACT_WR32 0x18c0 ++#define EARCRX_CMDC_XACT_WR33 0x18c4 ++#define EARCRX_CMDC_XACT_WR34 0x18c8 ++#define EARCRX_CMDC_XACT_WR35 0x18cc ++#define EARCRX_CMDC_XACT_WR36 0x18d0 ++#define EARCRX_CMDC_XACT_WR37 0x18d4 ++#define EARCRX_CMDC_XACT_WR38 0x18d8 ++#define EARCRX_CMDC_XACT_WR39 0x18dc ++#define EARCRX_CMDC_XACT_WR40 0x18e0 ++#define EARCRX_CMDC_XACT_WR41 0x18e4 ++#define EARCRX_CMDC_XACT_WR42 0x18e8 ++#define EARCRX_CMDC_XACT_WR43 0x18ec ++#define EARCRX_CMDC_XACT_WR44 0x18f0 ++#define EARCRX_CMDC_XACT_WR45 0x18f4 ++#define EARCRX_CMDC_XACT_WR46 0x18f8 ++#define EARCRX_CMDC_XACT_WR47 0x18fc ++#define EARCRX_CMDC_XACT_WR48 0x1900 ++#define EARCRX_CMDC_XACT_WR49 0x1904 ++#define EARCRX_CMDC_XACT_WR50 0x1908 ++#define EARCRX_CMDC_XACT_WR51 0x190c ++#define EARCRX_CMDC_XACT_WR52 0x1910 ++#define EARCRX_CMDC_XACT_WR53 0x1914 ++#define EARCRX_CMDC_XACT_WR54 0x1918 ++#define EARCRX_CMDC_XACT_WR55 0x191c ++#define EARCRX_CMDC_XACT_WR56 0x1920 ++#define EARCRX_CMDC_XACT_WR57 0x1924 ++#define EARCRX_CMDC_XACT_WR58 0x1928 ++#define EARCRX_CMDC_XACT_WR59 0x192c ++#define EARCRX_CMDC_XACT_WR60 0x1930 ++#define EARCRX_CMDC_XACT_WR61 0x1934 ++#define EARCRX_CMDC_XACT_WR62 0x1938 ++#define EARCRX_CMDC_XACT_WR63 0x193c ++#define EARCRX_CMDC_XACT_WR64 0x1940 ++#define EARCRX_CMDC_XACT_RD0 0x1960 ++#define EARCRX_CMDC_XACT_RD1 0x1964 ++#define EARCRX_CMDC_XACT_RD2 0x1968 ++#define EARCRX_CMDC_XACT_RD3 0x196c ++#define EARCRX_CMDC_XACT_RD4 0x1970 ++#define EARCRX_CMDC_XACT_RD5 0x1974 ++#define EARCRX_CMDC_XACT_RD6 0x1978 ++#define EARCRX_CMDC_XACT_RD7 0x197c ++#define EARCRX_CMDC_XACT_RD8 0x1980 ++#define EARCRX_CMDC_XACT_RD9 0x1984 ++#define EARCRX_CMDC_XACT_RD10 0x1988 ++#define EARCRX_CMDC_XACT_RD11 0x198c ++#define EARCRX_CMDC_XACT_RD12 0x1990 ++#define EARCRX_CMDC_XACT_RD13 0x1994 ++#define EARCRX_CMDC_XACT_RD14 0x1998 ++#define EARCRX_CMDC_XACT_RD15 0x199c ++#define EARCRX_CMDC_XACT_RD16 0x19a0 ++#define EARCRX_CMDC_XACT_RD17 0x19a4 ++#define EARCRX_CMDC_XACT_RD18 0x19a8 ++#define EARCRX_CMDC_XACT_RD19 0x19ac ++#define EARCRX_CMDC_XACT_RD20 0x19b0 ++#define EARCRX_CMDC_XACT_RD21 0x19b4 ++#define EARCRX_CMDC_XACT_RD22 0x19b8 ++#define EARCRX_CMDC_XACT_RD23 0x19bc ++#define EARCRX_CMDC_XACT_RD24 0x19c0 ++#define EARCRX_CMDC_XACT_RD25 0x19c4 ++#define EARCRX_CMDC_XACT_RD26 0x19c8 ++#define EARCRX_CMDC_XACT_RD27 0x19cc ++#define EARCRX_CMDC_XACT_RD28 0x19d0 ++#define EARCRX_CMDC_XACT_RD29 0x19d4 ++#define EARCRX_CMDC_XACT_RD30 0x19d8 ++#define EARCRX_CMDC_XACT_RD31 0x19dc ++#define EARCRX_CMDC_XACT_RD32 0x19e0 ++#define EARCRX_CMDC_XACT_RD33 0x19e4 ++#define EARCRX_CMDC_XACT_RD34 0x19e8 ++#define EARCRX_CMDC_XACT_RD35 0x19ec ++#define EARCRX_CMDC_XACT_RD36 0x19f0 ++#define EARCRX_CMDC_XACT_RD37 0x19f4 ++#define EARCRX_CMDC_XACT_RD38 0x19f8 ++#define EARCRX_CMDC_XACT_RD39 0x19fc ++#define EARCRX_CMDC_XACT_RD40 0x1a00 ++#define EARCRX_CMDC_XACT_RD41 0x1a04 ++#define EARCRX_CMDC_XACT_RD42 0x1a08 ++#define EARCRX_CMDC_XACT_RD43 0x1a0c ++#define EARCRX_CMDC_XACT_RD44 0x1a10 ++#define EARCRX_CMDC_XACT_RD45 0x1a14 ++#define EARCRX_CMDC_XACT_RD46 0x1a18 ++#define EARCRX_CMDC_XACT_RD47 0x1a1c ++#define EARCRX_CMDC_XACT_RD48 0x1a20 ++#define EARCRX_CMDC_XACT_RD49 0x1a24 ++#define EARCRX_CMDC_XACT_RD50 0x1a28 ++#define EARCRX_CMDC_XACT_RD51 0x1a2c ++#define EARCRX_CMDC_XACT_RD52 0x1a30 ++#define EARCRX_CMDC_XACT_RD53 0x1a34 ++#define EARCRX_CMDC_XACT_RD54 0x1a38 ++#define EARCRX_CMDC_XACT_RD55 0x1a3c ++#define EARCRX_CMDC_XACT_RD56 0x1a40 ++#define EARCRX_CMDC_XACT_RD57 0x1a44 ++#define EARCRX_CMDC_XACT_RD58 0x1a48 ++#define EARCRX_CMDC_XACT_RD59 0x1a4c ++#define EARCRX_CMDC_XACT_RD60 0x1a50 ++#define EARCRX_CMDC_XACT_RD61 0x1a54 ++#define EARCRX_CMDC_XACT_RD62 0x1a58 ++#define EARCRX_CMDC_XACT_RD63 0x1a5c ++#define EARCRX_CMDC_XACT_RD64 0x1a60 ++#define EARCRX_CMDC_SYNC_CONFIG 0x1b00 ++/* eARC RX DMAC Registers */ ++#define EARCRX_DMAC_PHY_CONTROL 0x1c00 ++#define EARCRX_DMAC_CONFIG 0x1c08 ++#define EARCRX_DMAC_CONTROL0 0x1c0c ++#define EARCRX_DMAC_AUDIO_EN BIT(1) ++#define EARCRX_DMAC_EN BIT(0) ++#define EARCRX_DMAC_CONTROL1 0x1c10 ++#define EARCRX_DMAC_STATUS 0x1c14 ++#define EARCRX_DMAC_CHSTATUS0 0x1c18 ++#define EARCRX_DMAC_CHSTATUS1 0x1c1c ++#define EARCRX_DMAC_CHSTATUS2 0x1c20 ++#define EARCRX_DMAC_CHSTATUS3 0x1c24 ++#define EARCRX_DMAC_CHSTATUS4 0x1c28 ++#define EARCRX_DMAC_CHSTATUS5 0x1c2c ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0 0x1c30 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1 0x1c34 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2 0x1c38 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3 0x1c3c ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4 0x1c40 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5 0x1c44 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6 0x1c48 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7 0x1c4c ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8 0x1c50 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9 0x1c54 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10 0x1c58 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11 0x1c5c ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0 0x1c60 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1 0x1c64 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2 0x1c68 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3 0x1c6c ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4 0x1c70 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5 0x1c74 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6 0x1c78 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7 0x1c7c ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8 0x1c80 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9 0x1c84 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10 0x1c88 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11 0x1c8c ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0 0x1c90 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1 0x1c94 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2 0x1c98 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3 0x1c9c ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4 0x1ca0 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5 0x1ca4 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6 0x1ca8 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7 0x1cac ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8 0x1cb0 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9 0x1cb4 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10 0x1cb8 ++#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11 0x1cbc ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC0 0x1cc0 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC1 0x1cc4 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC2 0x1cc8 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC3 0x1ccc ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC4 0x1cd0 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC5 0x1cd4 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC6 0x1cd8 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC7 0x1cdc ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC8 0x1ce0 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC9 0x1ce4 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC10 0x1ce8 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC11 0x1cec ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC12 0x1cf0 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC13 0x1cf4 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC14 0x1cf8 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC15 0x1cfc ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC16 0x1d00 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC17 0x1d04 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC18 0x1d08 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC19 0x1d0c ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC20 0x1d10 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC21 0x1d14 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC22 0x1d18 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC23 0x1d1c ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC24 0x1d20 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC25 0x1d24 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC26 0x1d28 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC27 0x1d2c ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC28 0x1d30 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC29 0x1d34 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC30 0x1d38 ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC31 0x1d3c ++#define EARCRX_DMAC_USRDATA_MSG_GENERIC32 0x1d40 ++#define EARCRX_DMAC_CHSTATUS_STREAMER0 0x1d44 ++#define EARCRX_DMAC_CHSTATUS_STREAMER1 0x1d48 ++#define EARCRX_DMAC_CHSTATUS_STREAMER2 0x1d4c ++#define EARCRX_DMAC_CHSTATUS_STREAMER3 0x1d50 ++#define EARCRX_DMAC_CHSTATUS_STREAMER4 0x1d54 ++#define EARCRX_DMAC_CHSTATUS_STREAMER5 0x1d58 ++#define EARCRX_DMAC_CHSTATUS_STREAMER6 0x1d5c ++#define EARCRX_DMAC_CHSTATUS_STREAMER7 0x1d60 ++#define EARCRX_DMAC_CHSTATUS_STREAMER8 0x1d64 ++#define EARCRX_DMAC_CHSTATUS_STREAMER9 0x1d68 ++#define EARCRX_DMAC_CHSTATUS_STREAMER10 0x1d6c ++#define EARCRX_DMAC_CHSTATUS_STREAMER11 0x1d70 ++#define EARCRX_DMAC_CHSTATUS_STREAMER12 0x1d74 ++#define EARCRX_DMAC_CHSTATUS_STREAMER13 0x1d78 ++#define EARCRX_DMAC_CHSTATUS_STREAMER14 0x1d7c ++#define EARCRX_DMAC_USRDATA_STREAMER0 0x1d80 ++/* Main Unit Interrupt Registers */ ++#define MAIN_INTVEC_INDEX 0x3000 ++#define MAINUNIT_0_INT_STATUS 0x3010 ++#define MAINUNIT_0_INT_MASK_N 0x3014 ++#define MAINUNIT_0_INT_CLEAR 0x3018 ++#define MAINUNIT_0_INT_FORCE 0x301c ++#define MAINUNIT_1_INT_STATUS 0x3020 ++#define FLT_EXIT_TO_LTSL_IRQ BIT(22) ++#define FLT_EXIT_TO_LTS4_IRQ BIT(21) ++#define FLT_EXIT_TO_LTSP_IRQ BIT(20) ++#define SCDC_NACK_RCVD_IRQ BIT(12) ++#define SCDC_RR_REPLY_STOP_IRQ BIT(11) ++#define SCDC_UPD_FLAGS_CLR_IRQ BIT(10) ++#define SCDC_UPD_FLAGS_CHG_IRQ BIT(9) ++#define SCDC_UPD_FLAGS_RD_IRQ BIT(8) ++#define I2CM_NACK_RCVD_IRQ BIT(2) ++#define I2CM_READ_REQUEST_IRQ BIT(1) ++#define I2CM_OP_DONE_IRQ BIT(0) ++#define MAINUNIT_1_INT_MASK_N 0x3024 ++#define I2CM_NACK_RCVD_MASK_N BIT(2) ++#define I2CM_READ_REQUEST_MASK_N BIT(1) ++#define I2CM_OP_DONE_MASK_N BIT(0) ++#define MAINUNIT_1_INT_CLEAR 0x3028 ++#define I2CM_NACK_RCVD_CLEAR BIT(2) ++#define I2CM_READ_REQUEST_CLEAR BIT(1) ++#define I2CM_OP_DONE_CLEAR BIT(0) ++#define MAINUNIT_1_INT_FORCE 0x302c ++/* AVPUNIT Interrupt Registers */ ++#define AVP_INTVEC_INDEX 0x3800 ++#define AVP_0_INT_STATUS 0x3810 ++#define AVP_0_INT_MASK_N 0x3814 ++#define AVP_0_INT_CLEAR 0x3818 ++#define AVP_0_INT_FORCE 0x381c ++#define AVP_1_INT_STATUS 0x3820 ++#define AVP_1_INT_MASK_N 0x3824 ++#define HDCP14_AUTH_CHG_MASK_N BIT(6) ++#define AVP_1_INT_CLEAR 0x3828 ++#define AVP_1_INT_FORCE 0x382c ++#define AVP_2_INT_STATUS 0x3830 ++#define AVP_2_INT_MASK_N 0x3834 ++#define AVP_2_INT_CLEAR 0x3838 ++#define AVP_2_INT_FORCE 0x383c ++#define AVP_3_INT_STATUS 0x3840 ++#define AVP_3_INT_MASK_N 0x3844 ++#define AVP_3_INT_CLEAR 0x3848 ++#define AVP_3_INT_FORCE 0x384c ++#define AVP_4_INT_STATUS 0x3850 ++#define AVP_4_INT_MASK_N 0x3854 ++#define AVP_4_INT_CLEAR 0x3858 ++#define AVP_4_INT_FORCE 0x385c ++#define AVP_5_INT_STATUS 0x3860 ++#define AVP_5_INT_MASK_N 0x3864 ++#define AVP_5_INT_CLEAR 0x3868 ++#define AVP_5_INT_FORCE 0x386c ++#define AVP_6_INT_STATUS 0x3870 ++#define AVP_6_INT_MASK_N 0x3874 ++#define AVP_6_INT_CLEAR 0x3878 ++#define AVP_6_INT_FORCE 0x387c ++/* CEC Interrupt Registers */ ++#define CEC_INT_STATUS 0x4000 ++#define CEC_INT_MASK_N 0x4004 ++#define CEC_INT_CLEAR 0x4008 ++#define CEC_INT_FORCE 0x400c ++/* eARC RX Interrupt Registers */ ++#define EARCRX_INTVEC_INDEX 0x4800 ++#define EARCRX_0_INT_STATUS 0x4810 ++#define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ BIT(9) ++#define EARCRX_CMDC_DISCOVERY_DONE_IRQ BIT(8) ++#define EARCRX_0_INT_MASK_N 0x4814 ++#define EARCRX_0_INT_CLEAR 0x4818 ++#define EARCRX_0_INT_FORCE 0x481c ++#define EARCRX_1_INT_STATUS 0x4820 ++#define EARCRX_1_INT_MASK_N 0x4824 ++#define EARCRX_1_INT_CLEAR 0x4828 ++#define EARCRX_1_INT_FORCE 0x482c ++ ++#endif /* __DW_HDMI_QP_H__ */ +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -163,6 +163,8 @@ struct dw_hdmi { + void __iomem *regs; + bool sink_is_hdmi; + bool sink_has_audio; ++ bool support_hdmi; ++ int force_output; + + struct pinctrl *pinctrl; + struct pinctrl_state *default_state; +@@ -255,6 +257,25 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, + hdmi_modb(hdmi, data << shift, mask, reg); + } + ++static bool dw_hdmi_check_output_type_changed(struct dw_hdmi *hdmi) ++{ ++ bool sink_hdmi; ++ ++ sink_hdmi = hdmi->sink_is_hdmi; ++ ++ if (hdmi->force_output == 1) ++ hdmi->sink_is_hdmi = true; ++ else if (hdmi->force_output == 2) ++ hdmi->sink_is_hdmi = false; ++ else ++ hdmi->sink_is_hdmi = hdmi->support_hdmi; ++ ++ if (sink_hdmi != hdmi->sink_is_hdmi) ++ return true; ++ ++ return false; ++} ++ + static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) + { + hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, +@@ -2539,6 +2560,45 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, + return 0; + } + ++void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi) ++{ ++ if (!hdmi->bridge_is_on) ++ return; ++ ++ hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP); ++ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); ++ hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP); ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_set_quant_range); ++ ++void dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val) ++{ ++ hdmi->force_output = val; ++ ++ if (!dw_hdmi_check_output_type_changed(hdmi)) ++ return; ++ ++ if (!hdmi->bridge_is_on) ++ return; ++ ++ hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP); ++ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); ++ hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP); ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_set_output_type); ++ ++bool dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi) ++{ ++ return hdmi->sink_is_hdmi; ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_get_output_whether_hdmi); ++ ++int dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi) ++{ ++ return hdmi->support_hdmi; ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_get_output_type_cap); ++ + static void dw_hdmi_connector_force(struct drm_connector *connector) + { + struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, +@@ -3668,6 +3728,35 @@ void dw_hdmi_unbind(struct dw_hdmi *hdmi) + } + EXPORT_SYMBOL_GPL(dw_hdmi_unbind); + ++void dw_hdmi_suspend(struct dw_hdmi *hdmi) ++{ ++ if (!hdmi) ++ return; ++ ++ mutex_lock(&hdmi->mutex); ++ ++ /* ++ * When system shutdown, hdmi should be disabled. ++ * When system suspend, dw_hdmi_bridge_disable will disable hdmi first. ++ * To prevent duplicate operation, we should determine whether hdmi ++ * has been disabled. ++ */ ++ if (!hdmi->disabled) { ++ hdmi->disabled = true; ++ dw_hdmi_update_power(hdmi); ++ dw_hdmi_update_phy_mask(hdmi); ++ } ++ mutex_unlock(&hdmi->mutex); ++ ++ //[CC: needed?] ++ // if (hdmi->irq) ++ // disable_irq(hdmi->irq); ++ // cancel_delayed_work(&hdmi->work); ++ // flush_workqueue(hdmi->workqueue); ++ pinctrl_pm_select_sleep_state(hdmi->dev); ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_suspend); ++ + void dw_hdmi_resume(struct dw_hdmi *hdmi) + { + dw_hdmi_init_hw(hdmi); +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +@@ -851,6 +851,10 @@ enum { + HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, + HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, + ++/* HDMI_FC_GCP */ ++ HDMI_FC_GCP_SET_AVMUTE = 0x2, ++ HDMI_FC_GCP_CLEAR_AVMUTE = 0x1, ++ + /* FC_DBGFORCE field values */ + HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, + HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -4,21 +4,32 @@ + */ + + #include ++#include ++#include + #include + #include + #include + #include ++#include + #include + #include + ++#include ++#include ++#include ++#include + #include + #include + #include + #include + #include + ++#include ++ + #include "rockchip_drm_drv.h" + ++#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) ++ + #define RK3228_GRF_SOC_CON2 0x0408 + #define RK3228_HDMI_SDAIN_MSK BIT(14) + #define RK3228_HDMI_SCLIN_MSK BIT(13) +@@ -29,8 +40,11 @@ + + #define RK3288_GRF_SOC_CON6 0x025C + #define RK3288_HDMI_LCDC_SEL BIT(4) +-#define RK3328_GRF_SOC_CON2 0x0408 ++#define RK3288_GRF_SOC_CON16 0x03a8 ++#define RK3288_HDMI_LCDC0_YUV420 BIT(2) ++#define RK3288_HDMI_LCDC1_YUV420 BIT(3) + ++#define RK3328_GRF_SOC_CON2 0x0408 + #define RK3328_HDMI_SDAIN_MSK BIT(11) + #define RK3328_HDMI_SCLIN_MSK BIT(10) + #define RK3328_HDMI_HPD_IOE BIT(2) +@@ -54,32 +68,177 @@ + #define RK3568_HDMI_SDAIN_MSK BIT(15) + #define RK3568_HDMI_SCLIN_MSK BIT(14) + +-#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) ++#define RK3588_GRF_SOC_CON2 0x0308 ++#define RK3588_HDMI1_HPD_INT_MSK BIT(15) ++#define RK3588_HDMI1_HPD_INT_CLR BIT(14) ++#define RK3588_HDMI0_HPD_INT_MSK BIT(13) ++#define RK3588_HDMI0_HPD_INT_CLR BIT(12) ++#define RK3588_GRF_SOC_CON7 0x031c ++#define RK3588_SET_HPD_PATH_MASK (0x3 << 12) ++#define RK3588_GRF_SOC_STATUS1 0x0384 ++#define RK3588_HDMI0_LOW_MORETHAN100MS BIT(20) ++#define RK3588_HDMI0_HPD_PORT_LEVEL BIT(19) ++#define RK3588_HDMI0_IHPD_PORT BIT(18) ++#define RK3588_HDMI0_OHPD_INT BIT(17) ++#define RK3588_HDMI0_LEVEL_INT BIT(16) ++#define RK3588_HDMI0_INTR_CHANGE_CNT (0x7 << 13) ++#define RK3588_HDMI1_LOW_MORETHAN100MS BIT(28) ++#define RK3588_HDMI1_HPD_PORT_LEVEL BIT(27) ++#define RK3588_HDMI1_IHPD_PORT BIT(26) ++#define RK3588_HDMI1_OHPD_INT BIT(25) ++#define RK3588_HDMI1_LEVEL_INT BIT(24) ++#define RK3588_HDMI1_INTR_CHANGE_CNT (0x7 << 21) ++ ++#define RK3588_GRF_VO1_CON3 0x000c ++#define RK3588_COLOR_FORMAT_MASK 0xf ++#define RK3588_YUV444 0x2 ++#define RK3588_YUV420 0x3 ++#define RK3588_COMPRESSED_DATA 0xb ++#define RK3588_COLOR_DEPTH_MASK (0xf << 4) ++#define RK3588_8BPC (0x5 << 4) ++#define RK3588_10BPC (0x6 << 4) ++#define RK3588_CECIN_MASK BIT(8) ++#define RK3588_SCLIN_MASK BIT(9) ++#define RK3588_SDAIN_MASK BIT(10) ++#define RK3588_MODE_MASK BIT(11) ++#define RK3588_COMPRESS_MODE_MASK BIT(12) ++#define RK3588_I2S_SEL_MASK BIT(13) ++#define RK3588_SPDIF_SEL_MASK BIT(14) ++#define RK3588_GRF_VO1_CON4 0x0010 ++#define RK3588_HDMI21_MASK BIT(0) ++#define RK3588_GRF_VO1_CON9 0x0024 ++#define RK3588_HDMI0_GRANT_SEL BIT(10) ++#define RK3588_HDMI0_GRANT_SW BIT(11) ++#define RK3588_HDMI1_GRANT_SEL BIT(12) ++#define RK3588_HDMI1_GRANT_SW BIT(13) ++#define RK3588_GRF_VO1_CON6 0x0018 ++#define RK3588_GRF_VO1_CON7 0x001c ++ ++#define COLOR_DEPTH_10BIT BIT(31) ++#define HDMI_FRL_MODE BIT(30) ++#define HDMI_EARC_MODE BIT(29) ++ ++#define HDMI20_MAX_RATE 600000 ++#define HDMI_8K60_RATE 2376000 + + /** + * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips + * @lcdsel_grf_reg: grf register offset of lcdc select ++ * @ddc_en_reg: grf register offset of hdmi ddc enable + * @lcdsel_big: reg value of selecting vop big for HDMI + * @lcdsel_lit: reg value of selecting vop little for HDMI ++ * @split_mode: flag indicating split mode capability + */ + struct rockchip_hdmi_chip_data { + int lcdsel_grf_reg; ++ int ddc_en_reg; + u32 lcdsel_big; + u32 lcdsel_lit; ++ bool split_mode; ++}; ++ ++enum hdmi_frl_rate_per_lane { ++ FRL_12G_PER_LANE = 12, ++ FRL_10G_PER_LANE = 10, ++ FRL_8G_PER_LANE = 8, ++ FRL_6G_PER_LANE = 6, ++ FRL_3G_PER_LANE = 3, ++}; ++ ++enum rk_if_color_depth { ++ RK_IF_DEPTH_8, ++ RK_IF_DEPTH_10, ++ RK_IF_DEPTH_12, ++ RK_IF_DEPTH_16, ++ RK_IF_DEPTH_420_10, ++ RK_IF_DEPTH_420_12, ++ RK_IF_DEPTH_420_16, ++ RK_IF_DEPTH_6, ++ RK_IF_DEPTH_MAX, ++}; ++ ++enum rk_if_color_format { ++ RK_IF_FORMAT_RGB, /* default RGB */ ++ RK_IF_FORMAT_YCBCR444, /* YCBCR 444 */ ++ RK_IF_FORMAT_YCBCR422, /* YCBCR 422 */ ++ RK_IF_FORMAT_YCBCR420, /* YCBCR 420 */ ++ RK_IF_FORMAT_YCBCR_HQ, /* Highest subsampled YUV */ ++ RK_IF_FORMAT_YCBCR_LQ, /* Lowest subsampled YUV */ ++ RK_IF_FORMAT_MAX, + }; + + struct rockchip_hdmi { + struct device *dev; + struct regmap *regmap; ++ struct regmap *vo1_regmap; + struct rockchip_encoder encoder; ++ struct drm_device *drm_dev; + const struct rockchip_hdmi_chip_data *chip_data; +- const struct dw_hdmi_plat_data *plat_data; ++ struct dw_hdmi_plat_data *plat_data; ++ struct clk *aud_clk; + struct clk *ref_clk; + struct clk *grf_clk; ++ struct clk *hclk_vio; ++ struct clk *hclk_vo1; ++ struct clk *hclk_vop; ++ struct clk *hpd_clk; ++ struct clk *pclk; ++ struct clk *earc_clk; ++ struct clk *hdmitx_ref; + struct dw_hdmi *hdmi; ++ struct dw_hdmi_qp *hdmi_qp; ++ + struct regulator *avdd_0v9; + struct regulator *avdd_1v8; + struct phy *phy; ++ ++ u32 max_tmdsclk; ++ bool unsupported_yuv_input; ++ bool unsupported_deep_color; ++ bool skip_check_420_mode; ++ u8 force_output; ++ u8 id; ++ bool hpd_stat; ++ bool is_hdmi_qp; ++ bool user_split_mode; ++ ++ unsigned long bus_format; ++ unsigned long output_bus_format; ++ unsigned long enc_out_encoding; ++ int color_changed; ++ int hpd_irq; ++ int vp_id; ++ ++ struct drm_property *color_depth_property; ++ struct drm_property *hdmi_output_property; ++ struct drm_property *colordepth_capacity; ++ struct drm_property *outputmode_capacity; ++ struct drm_property *quant_range; ++ struct drm_property *hdr_panel_metadata_property; ++ struct drm_property *next_hdr_sink_data_property; ++ struct drm_property *output_hdmi_dvi; ++ struct drm_property *output_type_capacity; ++ struct drm_property *user_split_mode_prop; ++ ++ struct drm_property_blob *hdr_panel_blob_ptr; ++ struct drm_property_blob *next_hdr_data_ptr; ++ ++ unsigned int colordepth; ++ unsigned int colorimetry; ++ unsigned int hdmi_quant_range; ++ unsigned int phy_bus_width; ++ enum rk_if_color_format hdmi_output; ++ // struct rockchip_drm_sub_dev sub_dev; ++ ++ u8 max_frl_rate_per_lane; ++ u8 max_lanes; ++ // struct rockchip_drm_dsc_cap dsc_cap; ++ // struct next_hdr_sink_data next_hdr_data; ++ struct dw_hdmi_link_config link_cfg; ++ struct gpio_desc *enable_gpio; ++ ++ struct delayed_work work; ++ struct workqueue_struct *workqueue; + }; + + static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) +@@ -202,13 +361,830 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { + /*pixelclk symbol term vlev*/ + { 74250000, 0x8009, 0x0004, 0x0272}, + { 148500000, 0x802b, 0x0004, 0x028d}, ++ { 165000000, 0x802b, 0x0004, 0x0209}, + { 297000000, 0x8039, 0x0005, 0x028d}, ++ { 594000000, 0x8039, 0x0000, 0x019d}, + { ~0UL, 0x0000, 0x0000, 0x0000} + }; + ++enum ROW_INDEX_BPP { ++ ROW_INDEX_6BPP = 0, ++ ROW_INDEX_8BPP, ++ ROW_INDEX_10BPP, ++ ROW_INDEX_12BPP, ++ ROW_INDEX_23BPP, ++ MAX_ROW_INDEX ++}; ++ ++enum COLUMN_INDEX_BPC { ++ COLUMN_INDEX_8BPC = 0, ++ COLUMN_INDEX_10BPC, ++ COLUMN_INDEX_12BPC, ++ COLUMN_INDEX_14BPC, ++ COLUMN_INDEX_16BPC, ++ MAX_COLUMN_INDEX ++}; ++ ++#define PPS_TABLE_LEN 8 ++#define PPS_BPP_LEN 4 ++#define PPS_BPC_LEN 2 ++ ++struct pps_data { ++ u32 pic_width; ++ u32 pic_height; ++ u32 slice_width; ++ u32 slice_height; ++ bool convert_rgb; ++ u8 bpc; ++ u8 bpp; ++ u8 raw_pps[128]; ++}; ++ ++#if 0 ++/* ++ * Selected Rate Control Related Parameter Recommended Values ++ * from DSC_v1.11 spec & C Model release: DSC_model_20161212 ++ */ ++static struct pps_data pps_datas[PPS_TABLE_LEN] = { ++ { ++ /* 7680x4320/960X96 rgb 8bpc 12bpp */ ++ 7680, 4320, 960, 96, 1, 8, 192, ++ { ++ 0x12, 0x00, 0x00, 0x8d, 0x30, 0xc0, 0x10, 0xe0, ++ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0xa0, ++ 0x01, 0x55, 0x03, 0x90, 0x00, 0x0a, 0x05, 0xc9, ++ 0x00, 0xa0, 0x00, 0x0f, 0x01, 0x44, 0x01, 0xaa, ++ 0x08, 0x00, 0x10, 0xf4, 0x03, 0x0c, 0x20, 0x00, ++ 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, ++ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, ++ 0x7d, 0x7e, 0x00, 0x82, 0x00, 0xc0, 0x09, 0x00, ++ 0x09, 0x7e, 0x19, 0xbc, 0x19, 0xba, 0x19, 0xf8, ++ 0x1a, 0x38, 0x1a, 0x38, 0x1a, 0x76, 0x2a, 0x76, ++ 0x2a, 0x76, 0x2a, 0x74, 0x3a, 0xb4, 0x52, 0xf4, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ }, ++ }, ++ { ++ /* 7680x4320/960X96 rgb 8bpc 11bpp */ ++ 7680, 4320, 960, 96, 1, 8, 176, ++ { ++ 0x12, 0x00, 0x00, 0x8d, 0x30, 0xb0, 0x10, 0xe0, ++ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0x28, ++ 0x01, 0x74, 0x03, 0x40, 0x00, 0x0f, 0x06, 0xe0, ++ 0x00, 0x2d, 0x00, 0x0f, 0x01, 0x44, 0x01, 0x33, ++ 0x0f, 0x00, 0x10, 0xf4, 0x03, 0x0c, 0x20, 0x00, ++ 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, ++ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, ++ 0x7d, 0x7e, 0x00, 0x82, 0x01, 0x00, 0x09, 0x40, ++ 0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8, ++ 0x1a, 0x38, 0x1a, 0x38, 0x1a, 0x76, 0x2a, 0x76, ++ 0x2a, 0x76, 0x2a, 0xb4, 0x3a, 0xb4, 0x52, 0xf4, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ }, ++ }, ++ { ++ /* 7680x4320/960X96 rgb 8bpc 10bpp */ ++ 7680, 4320, 960, 96, 1, 8, 160, ++ { ++ 0x12, 0x00, 0x00, 0x8d, 0x30, 0xa0, 0x10, 0xe0, ++ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0xb0, ++ 0x01, 0x9a, 0x02, 0xe0, 0x00, 0x19, 0x09, 0xb0, ++ 0x00, 0x12, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xbb, ++ 0x16, 0x00, 0x10, 0xec, 0x03, 0x0c, 0x20, 0x00, ++ 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, ++ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, ++ 0x7d, 0x7e, 0x00, 0xc2, 0x01, 0x00, 0x09, 0x40, ++ 0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8, ++ 0x1a, 0x38, 0x1a, 0x78, 0x1a, 0x76, 0x2a, 0xb6, ++ 0x2a, 0xb6, 0x2a, 0xf4, 0x3a, 0xf4, 0x5b, 0x34, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ }, ++ }, ++ { ++ /* 7680x4320/960X96 rgb 8bpc 9bpp */ ++ 7680, 4320, 960, 96, 1, 8, 144, ++ { ++ 0x12, 0x00, 0x00, 0x8d, 0x30, 0x90, 0x10, 0xe0, ++ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0x38, ++ 0x01, 0xc7, 0x03, 0x16, 0x00, 0x1c, 0x08, 0xc7, ++ 0x00, 0x10, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xaa, ++ 0x17, 0x00, 0x10, 0xf1, 0x03, 0x0c, 0x20, 0x00, ++ 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, ++ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, ++ 0x7d, 0x7e, 0x00, 0xc2, 0x01, 0x00, 0x09, 0x40, ++ 0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8, ++ 0x1a, 0x38, 0x1a, 0x78, 0x1a, 0x76, 0x2a, 0xb6, ++ 0x2a, 0xb6, 0x2a, 0xf4, 0x3a, 0xf4, 0x63, 0x74, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ }, ++ }, ++ { ++ /* 7680x4320/960X96 rgb 10bpc 12bpp */ ++ 7680, 4320, 960, 96, 1, 10, 192, ++ { ++ 0x12, 0x00, 0x00, 0xad, 0x30, 0xc0, 0x10, 0xe0, ++ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0xa0, ++ 0x01, 0x55, 0x03, 0x90, 0x00, 0x0a, 0x05, 0xc9, ++ 0x00, 0xa0, 0x00, 0x0f, 0x01, 0x44, 0x01, 0xaa, ++ 0x08, 0x00, 0x10, 0xf4, 0x07, 0x10, 0x20, 0x00, ++ 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, ++ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, ++ 0x7d, 0x7e, 0x01, 0x02, 0x11, 0x80, 0x22, 0x00, ++ 0x22, 0x7e, 0x32, 0xbc, 0x32, 0xba, 0x3a, 0xf8, ++ 0x3b, 0x38, 0x3b, 0x38, 0x3b, 0x76, 0x4b, 0x76, ++ 0x4b, 0x76, 0x4b, 0x74, 0x5b, 0xb4, 0x73, 0xf4, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ }, ++ }, ++ { ++ /* 7680x4320/960X96 rgb 10bpc 11bpp */ ++ 7680, 4320, 960, 96, 1, 10, 176, ++ { ++ 0x12, 0x00, 0x00, 0xad, 0x30, 0xb0, 0x10, 0xe0, ++ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0x28, ++ 0x01, 0x74, 0x03, 0x40, 0x00, 0x0f, 0x06, 0xe0, ++ 0x00, 0x2d, 0x00, 0x0f, 0x01, 0x44, 0x01, 0x33, ++ 0x0f, 0x00, 0x10, 0xf4, 0x07, 0x10, 0x20, 0x00, ++ 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, ++ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, ++ 0x7d, 0x7e, 0x01, 0x42, 0x19, 0xc0, 0x2a, 0x40, ++ 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, ++ 0x3b, 0x38, 0x3b, 0x38, 0x3b, 0x76, 0x4b, 0x76, ++ 0x4b, 0x76, 0x4b, 0xb4, 0x5b, 0xb4, 0x73, 0xf4, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ }, ++ }, ++ { ++ /* 7680x4320/960X96 rgb 10bpc 10bpp */ ++ 7680, 4320, 960, 96, 1, 10, 160, ++ { ++ 0x12, 0x00, 0x00, 0xad, 0x30, 0xa0, 0x10, 0xe0, ++ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0xb0, ++ 0x01, 0x9a, 0x02, 0xe0, 0x00, 0x19, 0x09, 0xb0, ++ 0x00, 0x12, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xbb, ++ 0x16, 0x00, 0x10, 0xec, 0x07, 0x10, 0x20, 0x00, ++ 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, ++ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, ++ 0x7d, 0x7e, 0x01, 0xc2, 0x22, 0x00, 0x2a, 0x40, ++ 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, ++ 0x3b, 0x38, 0x3b, 0x78, 0x3b, 0x76, 0x4b, 0xb6, ++ 0x4b, 0xb6, 0x4b, 0xf4, 0x63, 0xf4, 0x7c, 0x34, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ }, ++ }, ++ { ++ /* 7680x4320/960X96 rgb 10bpc 9bpp */ ++ 7680, 4320, 960, 96, 1, 10, 144, ++ { ++ 0x12, 0x00, 0x00, 0xad, 0x30, 0x90, 0x10, 0xe0, ++ 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0x38, ++ 0x01, 0xc7, 0x03, 0x16, 0x00, 0x1c, 0x08, 0xc7, ++ 0x00, 0x10, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xaa, ++ 0x17, 0x00, 0x10, 0xf1, 0x07, 0x10, 0x20, 0x00, ++ 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, ++ 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, ++ 0x7d, 0x7e, 0x01, 0xc2, 0x22, 0x00, 0x2a, 0x40, ++ 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, ++ 0x3b, 0x38, 0x3b, 0x78, 0x3b, 0x76, 0x4b, 0xb6, ++ 0x4b, 0xb6, 0x4b, 0xf4, 0x63, 0xf4, 0x84, 0x74, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ }, ++ }, ++}; ++ ++static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++#endif ++ ++static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: ++ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static int hdmi_bus_fmt_color_depth(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ return 8; ++ ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ return 10; ++ ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: ++ return 12; ++ ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: ++ return 16; ++ ++ default: ++ return 0; ++ } ++} ++ ++static unsigned int ++hdmi_get_tmdsclock(struct rockchip_hdmi *hdmi, unsigned long pixelclock) ++{ ++ unsigned int tmdsclock = pixelclock; ++ unsigned int depth = ++ hdmi_bus_fmt_color_depth(hdmi->output_bus_format); ++ ++ if (!hdmi_bus_fmt_is_yuv422(hdmi->output_bus_format)) { ++ switch (depth) { ++ case 16: ++ tmdsclock = pixelclock * 2; ++ break; ++ case 12: ++ tmdsclock = pixelclock * 3 / 2; ++ break; ++ case 10: ++ tmdsclock = pixelclock * 5 / 4; ++ break; ++ default: ++ break; ++ } ++ } ++ ++ return tmdsclock; ++} ++ ++static int rockchip_hdmi_match_by_id(struct device *dev, const void *data) ++{ ++ struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); ++ const unsigned int *id = data; ++ ++ return hdmi->id == *id; ++} ++ ++static struct rockchip_hdmi * ++rockchip_hdmi_find_by_id(struct device_driver *drv, unsigned int id) ++{ ++ struct device *dev; ++ ++ dev = driver_find_device(drv, NULL, &id, rockchip_hdmi_match_by_id); ++ if (!dev) ++ return NULL; ++ ++ return dev_get_drvdata(dev); ++} ++ ++static void hdmi_select_link_config(struct rockchip_hdmi *hdmi, ++ struct drm_crtc_state *crtc_state, ++ unsigned int tmdsclk) ++{ ++ struct drm_display_mode mode; ++ int max_lanes, max_rate_per_lane; ++ // int max_dsc_lanes, max_dsc_rate_per_lane; ++ unsigned long max_frl_rate; ++ ++ drm_mode_copy(&mode, &crtc_state->mode); ++ ++ max_lanes = hdmi->max_lanes; ++ max_rate_per_lane = hdmi->max_frl_rate_per_lane; ++ max_frl_rate = max_lanes * max_rate_per_lane * 1000000; ++ ++ hdmi->link_cfg.dsc_mode = false; ++ hdmi->link_cfg.frl_lanes = max_lanes; ++ hdmi->link_cfg.rate_per_lane = max_rate_per_lane; ++ ++ if (!max_frl_rate || (tmdsclk < HDMI20_MAX_RATE && mode.clock < HDMI20_MAX_RATE)) { ++ hdmi->link_cfg.frl_mode = false; ++ return; ++ } ++ ++ hdmi->link_cfg.frl_mode = true; ++ dev_warn(hdmi->dev, "use unsupported frl hdmi mode\n"); ++ ++ // if (!hdmi->dsc_cap.v_1p2) ++ // return; ++ // ++ // max_dsc_lanes = hdmi->dsc_cap.max_lanes; ++ // max_dsc_rate_per_lane = ++ // hdmi->dsc_cap.max_frl_rate_per_lane; ++ // ++ // if (mode.clock >= HDMI_8K60_RATE && ++ // !hdmi_bus_fmt_is_yuv420(hdmi->bus_format) && ++ // !hdmi_bus_fmt_is_yuv422(hdmi->bus_format)) { ++ // hdmi->link_cfg.dsc_mode = true; ++ // hdmi->link_cfg.frl_lanes = max_dsc_lanes; ++ // hdmi->link_cfg.rate_per_lane = max_dsc_rate_per_lane; ++ // } else { ++ // hdmi->link_cfg.dsc_mode = false; ++ // hdmi->link_cfg.frl_lanes = max_lanes; ++ // hdmi->link_cfg.rate_per_lane = max_rate_per_lane; ++ // } ++} ++ ++///////////////////////////////////////////////////////////////////////////////////// ++/* CC: disable DSC */ ++#if 0 ++static int hdmi_dsc_get_slice_height(int vactive) ++{ ++ int slice_height; ++ ++ /* ++ * Slice Height determination : HDMI2.1 Section 7.7.5.2 ++ * Select smallest slice height >=96, that results in a valid PPS and ++ * requires minimum padding lines required for final slice. ++ * ++ * Assumption : Vactive is even. ++ */ ++ for (slice_height = 96; slice_height <= vactive; slice_height += 2) ++ if (vactive % slice_height == 0) ++ return slice_height; ++ ++ return 0; ++} ++ ++static int hdmi_dsc_get_num_slices(struct rockchip_hdmi *hdmi, ++ struct drm_crtc_state *crtc_state, ++ int src_max_slices, int src_max_slice_width, ++ int hdmi_max_slices, int hdmi_throughput) ++{ ++/* Pixel rates in KPixels/sec */ ++#define HDMI_DSC_PEAK_PIXEL_RATE 2720000 ++/* ++ * Rates at which the source and sink are required to process pixels in each ++ * slice, can be two levels: either at least 340000KHz or at least 40000KHz. ++ */ ++#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 ++#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 ++ ++/* Spec limits the slice width to 2720 pixels */ ++#define MAX_HDMI_SLICE_WIDTH 2720 ++ int kslice_adjust; ++ int adjusted_clk_khz; ++ int min_slices; ++ int target_slices; ++ int max_throughput; /* max clock freq. in khz per slice */ ++ int max_slice_width; ++ int slice_width; ++ int pixel_clock = crtc_state->mode.clock; ++ ++ if (!hdmi_throughput) ++ return 0; ++ ++ /* ++ * Slice Width determination : HDMI2.1 Section 7.7.5.1 ++ * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as ++ * for 4:4:4 is 1.0. Multiplying these factors by 10 and later ++ * dividing adjusted clock value by 10. ++ */ ++ if (hdmi_bus_fmt_is_yuv444(hdmi->output_bus_format) || ++ hdmi_bus_fmt_is_rgb(hdmi->output_bus_format)) ++ kslice_adjust = 10; ++ else ++ kslice_adjust = 5; ++ ++ /* ++ * As per spec, the rate at which the source and the sink process ++ * the pixels per slice are at two levels: at least 340Mhz or 400Mhz. ++ * This depends upon the pixel clock rate and output formats ++ * (kslice adjust). ++ * If pixel clock * kslice adjust >= 2720MHz slices can be processed ++ * at max 340MHz, otherwise they can be processed at max 400MHz. ++ */ ++ ++ adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); ++ ++ if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) ++ max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; ++ else ++ max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; ++ ++ /* ++ * Taking into account the sink's capability for maximum ++ * clock per slice (in MHz) as read from HF-VSDB. ++ */ ++ max_throughput = min(max_throughput, hdmi_throughput * 1000); ++ ++ min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); ++ max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); ++ ++ /* ++ * Keep on increasing the num of slices/line, starting from min_slices ++ * per line till we get such a number, for which the slice_width is ++ * just less than max_slice_width. The slices/line selected should be ++ * less than or equal to the max horizontal slices that the combination ++ * of PCON encoder and HDMI decoder can support. ++ */ ++ do { ++ if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) ++ target_slices = 1; ++ else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) ++ target_slices = 2; ++ else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) ++ target_slices = 4; ++ else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) ++ target_slices = 8; ++ else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) ++ target_slices = 12; ++ else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) ++ target_slices = 16; ++ else ++ return 0; ++ ++ slice_width = DIV_ROUND_UP(crtc_state->mode.hdisplay, target_slices); ++ if (slice_width > max_slice_width) ++ min_slices = target_slices + 1; ++ } while (slice_width > max_slice_width); ++ ++ return target_slices; ++} ++ ++static int hdmi_dsc_slices(struct rockchip_hdmi *hdmi, ++ struct drm_crtc_state *crtc_state) ++{ ++ int hdmi_throughput = hdmi->dsc_cap.clk_per_slice; ++ int hdmi_max_slices = hdmi->dsc_cap.max_slices; ++ int rk_max_slices = 8; ++ int rk_max_slice_width = 2048; ++ ++ return hdmi_dsc_get_num_slices(hdmi, crtc_state, rk_max_slices, ++ rk_max_slice_width, ++ hdmi_max_slices, hdmi_throughput); ++} ++ ++static int ++hdmi_dsc_get_bpp(struct rockchip_hdmi *hdmi, int src_fractional_bpp, ++ int slice_width, int num_slices, bool hdmi_all_bpp, ++ int hdmi_max_chunk_bytes) ++{ ++ int max_dsc_bpp, min_dsc_bpp; ++ int target_bytes; ++ bool bpp_found = false; ++ int bpp_decrement_x16; ++ int bpp_target; ++ int bpp_target_x16; ++ ++ /* ++ * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec ++ * Start with the max bpp and keep on decrementing with ++ * fractional bpp, if supported by PCON DSC encoder ++ * ++ * for each bpp we check if no of bytes can be supported by HDMI sink ++ */ ++ ++ /* only 9\10\12 bpp was tested */ ++ min_dsc_bpp = 9; ++ max_dsc_bpp = 12; ++ ++ /* ++ * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink ++ * Section 7.7.34 : Source shall not enable compressed Video ++ * Transport with bpp_target settings above 12 bpp unless ++ * DSC_all_bpp is set to 1. ++ */ ++ if (!hdmi_all_bpp) ++ max_dsc_bpp = min(max_dsc_bpp, 12); ++ ++ /* ++ * The Sink has a limit of compressed data in bytes for a scanline, ++ * as described in max_chunk_bytes field in HFVSDB block of edid. ++ * The no. of bytes depend on the target bits per pixel that the ++ * source configures. So we start with the max_bpp and calculate ++ * the target_chunk_bytes. We keep on decrementing the target_bpp, ++ * till we get the target_chunk_bytes just less than what the sink's ++ * max_chunk_bytes, or else till we reach the min_dsc_bpp. ++ * ++ * The decrement is according to the fractional support from PCON DSC ++ * encoder. For fractional BPP we use bpp_target as a multiple of 16. ++ * ++ * bpp_target_x16 = bpp_target * 16 ++ * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps ++ * {1/16, 1/8, 1/4, 1/2, 1} respectively. ++ */ ++ ++ bpp_target = max_dsc_bpp; ++ ++ /* src does not support fractional bpp implies decrement by 16 for bppx16 */ ++ if (!src_fractional_bpp) ++ src_fractional_bpp = 1; ++ bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); ++ bpp_target_x16 = bpp_target * 16; ++ ++ while (bpp_target_x16 > (min_dsc_bpp * 16)) { ++ int bpp; ++ ++ bpp = DIV_ROUND_UP(bpp_target_x16, 16); ++ target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); ++ if (target_bytes <= hdmi_max_chunk_bytes) { ++ bpp_found = true; ++ break; ++ } ++ bpp_target_x16 -= bpp_decrement_x16; ++ } ++ if (bpp_found) ++ return bpp_target_x16; ++ ++ return 0; ++} ++ ++static int ++dw_hdmi_dsc_bpp(struct rockchip_hdmi *hdmi, ++ int num_slices, int slice_width) ++{ ++ bool hdmi_all_bpp = hdmi->dsc_cap.all_bpp; ++ int fractional_bpp = 0; ++ int hdmi_max_chunk_bytes = hdmi->dsc_cap.total_chunk_kbytes * 1024; ++ ++ return hdmi_dsc_get_bpp(hdmi, fractional_bpp, slice_width, ++ num_slices, hdmi_all_bpp, ++ hdmi_max_chunk_bytes); ++} ++ ++static int dw_hdmi_qp_set_link_cfg(struct rockchip_hdmi *hdmi, ++ u16 pic_width, u16 pic_height, ++ u16 slice_width, u16 slice_height, ++ u16 bits_per_pixel, u8 bits_per_component) ++{ ++ int i; ++ ++ for (i = 0; i < PPS_TABLE_LEN; i++) ++ if (pic_width == pps_datas[i].pic_width && ++ pic_height == pps_datas[i].pic_height && ++ slice_width == pps_datas[i].slice_width && ++ slice_height == pps_datas[i].slice_height && ++ bits_per_component == pps_datas[i].bpc && ++ bits_per_pixel == pps_datas[i].bpp && ++ hdmi_bus_fmt_is_rgb(hdmi->output_bus_format) == pps_datas[i].convert_rgb) ++ break; ++ ++ if (i == PPS_TABLE_LEN) { ++ dev_err(hdmi->dev, "can't find pps cfg!\n"); ++ return -EINVAL; ++ } ++ ++ memcpy(hdmi->link_cfg.pps_payload, pps_datas[i].raw_pps, 128); ++ hdmi->link_cfg.hcactive = DIV_ROUND_UP(slice_width * (bits_per_pixel / 16), 8) * ++ (pic_width / slice_width); ++ ++ return 0; ++} ++ ++static void dw_hdmi_qp_dsc_configure(struct rockchip_hdmi *hdmi, ++ struct rockchip_crtc_state *s, ++ struct drm_crtc_state *crtc_state) ++{ ++ int ret; ++ int slice_height; ++ int slice_width; ++ int bits_per_pixel; ++ int slice_count; ++ bool hdmi_is_dsc_1_2; ++ unsigned int depth = hdmi_bus_fmt_color_depth(hdmi->output_bus_format); ++ ++ if (!crtc_state) ++ return; ++ ++ hdmi_is_dsc_1_2 = hdmi->dsc_cap.v_1p2; ++ ++ if (!hdmi_is_dsc_1_2) ++ return; ++ ++ slice_height = hdmi_dsc_get_slice_height(crtc_state->mode.vdisplay); ++ if (!slice_height) ++ return; ++ ++ slice_count = hdmi_dsc_slices(hdmi, crtc_state); ++ if (!slice_count) ++ return; ++ ++ slice_width = DIV_ROUND_UP(crtc_state->mode.hdisplay, slice_count); ++ ++ bits_per_pixel = dw_hdmi_dsc_bpp(hdmi, slice_count, slice_width); ++ if (!bits_per_pixel) ++ return; ++ ++ ret = dw_hdmi_qp_set_link_cfg(hdmi, crtc_state->mode.hdisplay, ++ crtc_state->mode.vdisplay, slice_width, ++ slice_height, bits_per_pixel, depth); ++ ++ if (ret) { ++ dev_err(hdmi->dev, "set vdsc cfg failed\n"); ++ return; ++ } ++ dev_info(hdmi->dev, "dsc_enable\n"); ++ s->dsc_enable = 1; ++ s->dsc_sink_cap.version_major = 1; ++ s->dsc_sink_cap.version_minor = 2; ++ s->dsc_sink_cap.slice_width = slice_width; ++ s->dsc_sink_cap.slice_height = slice_height; ++ s->dsc_sink_cap.target_bits_per_pixel_x16 = bits_per_pixel; ++ s->dsc_sink_cap.block_pred = 1; ++ s->dsc_sink_cap.native_420 = 0; ++ ++ memcpy(&s->pps, hdmi->link_cfg.pps_payload, 128); ++} ++#endif ++///////////////////////////////////////////////////////////////////////////////////////// ++ ++// static int rockchip_hdmi_update_phy_table(struct rockchip_hdmi *hdmi, ++// u32 *config, ++// int phy_table_size) ++// { ++// int i; ++// ++// if (phy_table_size > ARRAY_SIZE(rockchip_phy_config)) { ++// dev_err(hdmi->dev, "phy table array number is out of range\n"); ++// return -E2BIG; ++// } ++// ++// for (i = 0; i < phy_table_size; i++) { ++// if (config[i * 4] != 0) ++// rockchip_phy_config[i].mpixelclock = (u64)config[i * 4]; ++// else ++// rockchip_phy_config[i].mpixelclock = ~0UL; ++// rockchip_phy_config[i].sym_ctr = (u16)config[i * 4 + 1]; ++// rockchip_phy_config[i].term = (u16)config[i * 4 + 2]; ++// rockchip_phy_config[i].vlev_ctr = (u16)config[i * 4 + 3]; ++// } ++// ++// return 0; ++// } ++ ++static void repo_hpd_event(struct work_struct *p_work) ++{ ++ struct rockchip_hdmi *hdmi = container_of(p_work, struct rockchip_hdmi, work.work); ++ bool change; ++ ++ change = drm_helper_hpd_irq_event(hdmi->drm_dev); ++ if (change) { ++ dev_dbg(hdmi->dev, "hpd stat changed:%d\n", hdmi->hpd_stat); ++ // dw_hdmi_qp_cec_set_hpd(hdmi->hdmi_qp, hdmi->hpd_stat, change); ++ } ++} ++ ++static irqreturn_t rockchip_hdmi_hardirq(int irq, void *dev_id) ++{ ++ struct rockchip_hdmi *hdmi = dev_id; ++ u32 intr_stat, val; ++ ++ regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); ++ ++ if (intr_stat) { ++ dev_dbg(hdmi->dev, "hpd irq %#x\n", intr_stat); ++ ++ if (!hdmi->id) ++ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, ++ RK3588_HDMI0_HPD_INT_MSK); ++ else ++ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, ++ RK3588_HDMI1_HPD_INT_MSK); ++ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); ++ return IRQ_WAKE_THREAD; ++ } ++ ++ return IRQ_NONE; ++} ++ ++static irqreturn_t rockchip_hdmi_irq(int irq, void *dev_id) ++{ ++ struct rockchip_hdmi *hdmi = dev_id; ++ u32 intr_stat, val; ++ int msecs; ++ bool stat; ++ ++ regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); ++ ++ if (!intr_stat) ++ return IRQ_NONE; ++ ++ if (!hdmi->id) { ++ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, ++ RK3588_HDMI0_HPD_INT_CLR); ++ if (intr_stat & RK3588_HDMI0_LEVEL_INT) ++ stat = true; ++ else ++ stat = false; ++ } else { ++ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, ++ RK3588_HDMI1_HPD_INT_CLR); ++ if (intr_stat & RK3588_HDMI1_LEVEL_INT) ++ stat = true; ++ else ++ stat = false; ++ } ++ ++ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); ++ ++ if (stat) { ++ hdmi->hpd_stat = true; ++ msecs = 150; ++ } else { ++ hdmi->hpd_stat = false; ++ msecs = 20; ++ } ++ mod_delayed_work(hdmi->workqueue, &hdmi->work, msecs_to_jiffies(msecs)); ++ ++ if (!hdmi->id) { ++ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, ++ RK3588_HDMI0_HPD_INT_CLR) | ++ HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); ++ } else { ++ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, ++ RK3588_HDMI1_HPD_INT_CLR) | ++ HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK); ++ } ++ ++ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); ++ ++ return IRQ_HANDLED; ++} ++ + static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) + { + struct device_node *np = hdmi->dev->of_node; ++ int ret; + + hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); + if (IS_ERR(hdmi->regmap)) { +@@ -216,6 +1192,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) + return PTR_ERR(hdmi->regmap); + } + ++ if (hdmi->is_hdmi_qp) { ++ hdmi->vo1_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,vo1_grf"); ++ if (IS_ERR(hdmi->vo1_regmap)) { ++ DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,vo1_grf\n"); ++ return PTR_ERR(hdmi->vo1_regmap); ++ } ++ } ++ + hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref"); + if (!hdmi->ref_clk) + hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll"); +@@ -245,6 +1229,79 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) + if (IS_ERR(hdmi->avdd_1v8)) + return PTR_ERR(hdmi->avdd_1v8); + ++ hdmi->hclk_vio = devm_clk_get(hdmi->dev, "hclk_vio"); ++ if (PTR_ERR(hdmi->hclk_vio) == -ENOENT) { ++ hdmi->hclk_vio = NULL; ++ } else if (PTR_ERR(hdmi->hclk_vio) == -EPROBE_DEFER) { ++ return -EPROBE_DEFER; ++ } else if (IS_ERR(hdmi->hclk_vio)) { ++ dev_err(hdmi->dev, "failed to get hclk_vio clock\n"); ++ return PTR_ERR(hdmi->hclk_vio); ++ } ++ ++ hdmi->hclk_vop = devm_clk_get(hdmi->dev, "hclk"); ++ if (PTR_ERR(hdmi->hclk_vop) == -ENOENT) { ++ hdmi->hclk_vop = NULL; ++ } else if (PTR_ERR(hdmi->hclk_vop) == -EPROBE_DEFER) { ++ return -EPROBE_DEFER; ++ } else if (IS_ERR(hdmi->hclk_vop)) { ++ dev_err(hdmi->dev, "failed to get hclk_vop clock\n"); ++ return PTR_ERR(hdmi->hclk_vop); ++ } ++ ++ hdmi->aud_clk = devm_clk_get_optional(hdmi->dev, "aud"); ++ if (IS_ERR(hdmi->aud_clk)) { ++ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->aud_clk), ++ "failed to get aud_clk clock\n"); ++ return PTR_ERR(hdmi->aud_clk); ++ } ++ ++ hdmi->hpd_clk = devm_clk_get_optional(hdmi->dev, "hpd"); ++ if (IS_ERR(hdmi->hpd_clk)) { ++ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hpd_clk), ++ "failed to get hpd_clk clock\n"); ++ return PTR_ERR(hdmi->hpd_clk); ++ } ++ ++ hdmi->hclk_vo1 = devm_clk_get_optional(hdmi->dev, "hclk_vo1"); ++ if (IS_ERR(hdmi->hclk_vo1)) { ++ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hclk_vo1), ++ "failed to get hclk_vo1 clock\n"); ++ return PTR_ERR(hdmi->hclk_vo1); ++ } ++ ++ hdmi->earc_clk = devm_clk_get_optional(hdmi->dev, "earc"); ++ if (IS_ERR(hdmi->earc_clk)) { ++ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->earc_clk), ++ "failed to get earc_clk clock\n"); ++ return PTR_ERR(hdmi->earc_clk); ++ } ++ ++ hdmi->hdmitx_ref = devm_clk_get_optional(hdmi->dev, "hdmitx_ref"); ++ if (IS_ERR(hdmi->hdmitx_ref)) { ++ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hdmitx_ref), ++ "failed to get hdmitx_ref clock\n"); ++ return PTR_ERR(hdmi->hdmitx_ref); ++ } ++ ++ hdmi->pclk = devm_clk_get_optional(hdmi->dev, "pclk"); ++ if (IS_ERR(hdmi->pclk)) { ++ dev_err_probe(hdmi->dev, PTR_ERR(hdmi->pclk), ++ "failed to get pclk clock\n"); ++ return PTR_ERR(hdmi->pclk); ++ } ++ ++ hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable", ++ GPIOD_OUT_HIGH); ++ if (IS_ERR(hdmi->enable_gpio)) { ++ ret = PTR_ERR(hdmi->enable_gpio); ++ dev_err(hdmi->dev, "failed to request enable GPIO: %d\n", ret); ++ return ret; ++ } ++ ++ hdmi->skip_check_420_mode = ++ of_property_read_bool(np, "skip-check-420-mode"); ++ + return 0; + } + +@@ -283,9 +1340,114 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data, + + return MODE_BAD; + } ++/* [CC:] enable downstream mode_valid() */ ++// static enum drm_mode_status ++// dw_hdmi_rockchip_mode_valid(struct drm_connector *connector, void *data, ++// const struct drm_display_info *info, ++// const struct drm_display_mode *mode) ++// { ++// struct drm_encoder *encoder = connector->encoder; ++// enum drm_mode_status status = MODE_OK; ++// struct drm_device *dev = connector->dev; ++// struct rockchip_drm_private *priv = dev->dev_private; ++// struct drm_crtc *crtc; ++// struct rockchip_hdmi *hdmi; ++// ++// /* ++// * Pixel clocks we support are always < 2GHz and so fit in an ++// * int. We should make sure source rate does too so we don't get ++// * overflow when we multiply by 1000. ++// */ ++// if (mode->clock > INT_MAX / 1000) ++// return MODE_BAD; ++// ++// if (!encoder) { ++// const struct drm_connector_helper_funcs *funcs; ++// ++// funcs = connector->helper_private; ++// if (funcs->atomic_best_encoder) ++// encoder = funcs->atomic_best_encoder(connector, ++// connector->state); ++// else ++// encoder = funcs->best_encoder(connector); ++// } ++// ++// if (!encoder || !encoder->possible_crtcs) ++// return MODE_BAD; ++// ++// hdmi = to_rockchip_hdmi(encoder); ++// ++// /* ++// * If sink max TMDS clock < 340MHz, we should check the mode pixel ++// * clock > 340MHz is YCbCr420 or not and whether the platform supports ++// * YCbCr420. ++// */ ++// if (!hdmi->skip_check_420_mode) { ++// if (mode->clock > 340000 && ++// connector->display_info.max_tmds_clock < 340000 && ++// (!drm_mode_is_420(&connector->display_info, mode) || ++// !connector->ycbcr_420_allowed)) ++// return MODE_BAD; ++// ++// if (hdmi->max_tmdsclk <= 340000 && mode->clock > 340000 && ++// !drm_mode_is_420(&connector->display_info, mode)) ++// return MODE_BAD; ++// }; ++// ++// if (hdmi->phy) { ++// if (hdmi->is_hdmi_qp) ++// phy_set_bus_width(hdmi->phy, mode->clock * 10); ++// else ++// phy_set_bus_width(hdmi->phy, 8); ++// } ++// ++// /* ++// * ensure all drm display mode can work, if someone want support more ++// * resolutions, please limit the possible_crtc, only connect to ++// * needed crtc. ++// */ ++// drm_for_each_crtc(crtc, connector->dev) { ++// int pipe = drm_crtc_index(crtc); ++// const struct rockchip_crtc_funcs *funcs = ++// priv->crtc_funcs[pipe]; ++// ++// if (!(encoder->possible_crtcs & drm_crtc_mask(crtc))) ++// continue; ++// if (!funcs || !funcs->mode_valid) ++// continue; ++// ++// status = funcs->mode_valid(crtc, mode, ++// DRM_MODE_CONNECTOR_HDMIA); ++// if (status != MODE_OK) ++// return status; ++// } ++// ++// return status; ++// } ++// + + static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) + { ++ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); ++ // struct drm_crtc *crtc = encoder->crtc; ++ // struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); ++ // ++ // if (crtc->state->active_changed) { ++ // if (hdmi->plat_data->split_mode) { ++ // s->output_if &= ~(VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1); ++ // } else { ++ // if (!hdmi->id) ++ // s->output_if &= ~VOP_OUTPUT_IF_HDMI1; ++ // else ++ // s->output_if &= ~VOP_OUTPUT_IF_HDMI0; ++ // } ++ // } ++ /* ++ * when plug out hdmi it will be switch cvbs and then phy bus width ++ * must be set as 8 ++ */ ++ if (hdmi->phy) ++ phy_set_bus_width(hdmi->phy, 8); + } + + static bool +@@ -301,6 +1463,27 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *adj_mode) + { + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); ++ struct drm_crtc *crtc; ++ struct rockchip_crtc_state *s; ++ ++ if (!encoder->crtc) ++ return; ++ crtc = encoder->crtc; ++ ++ if (!crtc->state) ++ return; ++ s = to_rockchip_crtc_state(crtc->state); ++ ++ if (!s) ++ return; ++ ++ if (hdmi->is_hdmi_qp) { ++ // s->dsc_enable = 0; ++ // if (hdmi->link_cfg.dsc_mode) ++ // dw_hdmi_qp_dsc_configure(hdmi, s, crtc->state); ++ ++ phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); ++ } + + clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); + } +@@ -308,14 +1491,25 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, + static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) + { + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); ++ struct drm_crtc *crtc = encoder->crtc; + u32 val; ++ int mux; + int ret; + ++ if (WARN_ON(!crtc || !crtc->state)) ++ return; ++ ++ if (hdmi->phy) ++ phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); ++ ++ clk_set_rate(hdmi->ref_clk, ++ crtc->state->adjusted_mode.crtc_clock * 1000); ++ + if (hdmi->chip_data->lcdsel_grf_reg < 0) + return; + +- ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); +- if (ret) ++ mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); ++ if (mux) + val = hdmi->chip_data->lcdsel_lit; + else + val = hdmi->chip_data->lcdsel_big; +@@ -330,24 +1524,992 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) + if (ret != 0) + DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret); + ++ if (hdmi->chip_data->lcdsel_grf_reg == RK3288_GRF_SOC_CON6) { ++ struct rockchip_crtc_state *s = ++ to_rockchip_crtc_state(crtc->state); ++ u32 mode_mask = mux ? RK3288_HDMI_LCDC1_YUV420 : ++ RK3288_HDMI_LCDC0_YUV420; ++ ++ if (s->output_mode == ROCKCHIP_OUT_MODE_YUV420) ++ val = HIWORD_UPDATE(mode_mask, mode_mask); ++ else ++ val = HIWORD_UPDATE(0, mode_mask); ++ ++ regmap_write(hdmi->regmap, RK3288_GRF_SOC_CON16, val); ++ } ++ + clk_disable_unprepare(hdmi->grf_clk); + DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n", + ret ? "LIT" : "BIG"); + } + +-static int +-dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, +- struct drm_crtc_state *crtc_state, +- struct drm_connector_state *conn_state) ++static void rk3588_set_link_mode(struct rockchip_hdmi *hdmi) + { +- struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); ++ int val; ++ bool is_hdmi0; + +- s->output_mode = ROCKCHIP_OUT_MODE_AAAA; +- s->output_type = DRM_MODE_CONNECTOR_HDMIA; ++ if (!hdmi->id) ++ is_hdmi0 = true; ++ else ++ is_hdmi0 = false; ++ ++ if (!hdmi->link_cfg.frl_mode) { ++ val = HIWORD_UPDATE(0, RK3588_HDMI21_MASK); ++ if (is_hdmi0) ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON4, val); ++ else ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON7, val); ++ ++ val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); ++ if (is_hdmi0) ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); ++ else ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); ++ ++ return; ++ } ++ ++ val = HIWORD_UPDATE(RK3588_HDMI21_MASK, RK3588_HDMI21_MASK); ++ if (is_hdmi0) ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON4, val); ++ else ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON7, val); ++ ++ if (hdmi->link_cfg.dsc_mode) { ++ val = HIWORD_UPDATE(RK3588_COMPRESS_MODE_MASK | RK3588_COMPRESSED_DATA, ++ RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); ++ if (is_hdmi0) ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); ++ else ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); ++ } else { ++ val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); ++ if (is_hdmi0) ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); ++ else ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); ++ } ++} ++ ++static void rk3588_set_color_format(struct rockchip_hdmi *hdmi, u64 bus_format, ++ u32 depth) ++{ ++ u32 val = 0; ++ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ val = HIWORD_UPDATE(0, RK3588_COLOR_FORMAT_MASK); ++ break; ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ val = HIWORD_UPDATE(RK3588_YUV420, RK3588_COLOR_FORMAT_MASK); ++ break; ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ val = HIWORD_UPDATE(RK3588_YUV444, RK3588_COLOR_FORMAT_MASK); ++ break; ++ default: ++ dev_err(hdmi->dev, "can't set correct color format\n"); ++ return; ++ } ++ ++ if (hdmi->link_cfg.dsc_mode) ++ val = HIWORD_UPDATE(RK3588_COMPRESSED_DATA, RK3588_COLOR_FORMAT_MASK); ++ ++ if (depth == 8) ++ val |= HIWORD_UPDATE(RK3588_8BPC, RK3588_COLOR_DEPTH_MASK); ++ else ++ val |= HIWORD_UPDATE(RK3588_10BPC, RK3588_COLOR_DEPTH_MASK); ++ ++ if (!hdmi->id) ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); ++ else ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); ++} ++ ++static void rk3588_set_grf_cfg(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ int color_depth; ++ ++ rk3588_set_link_mode(hdmi); ++ color_depth = hdmi_bus_fmt_color_depth(hdmi->bus_format); ++ rk3588_set_color_format(hdmi, hdmi->bus_format, color_depth); ++} ++ ++static void ++dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state, ++ struct drm_crtc_state *crtc_state, ++ struct rockchip_hdmi *hdmi, ++ unsigned int *color_format, ++ unsigned int *output_mode, ++ unsigned long *bus_format, ++ unsigned int *bus_width, ++ unsigned long *enc_out_encoding, ++ unsigned int *eotf) ++{ ++ struct drm_display_info *info = &conn_state->connector->display_info; ++ struct drm_display_mode mode; ++ struct hdr_output_metadata *hdr_metadata; ++ u32 vic; ++ unsigned long tmdsclock, pixclock; ++ unsigned int color_depth; ++ bool support_dc = false; ++ bool sink_is_hdmi = true; ++ u32 max_tmds_clock = info->max_tmds_clock; ++ int output_eotf; ++ ++ drm_mode_copy(&mode, &crtc_state->mode); ++ pixclock = mode.crtc_clock; ++ // if (hdmi->plat_data->split_mode) { ++ // drm_mode_convert_to_origin_mode(&mode); ++ // pixclock /= 2; ++ // } ++ ++ vic = drm_match_cea_mode(&mode); ++ ++ if (!hdmi->is_hdmi_qp) ++ sink_is_hdmi = dw_hdmi_get_output_whether_hdmi(hdmi->hdmi); ++ ++ *color_format = RK_IF_FORMAT_RGB; ++ ++ switch (hdmi->hdmi_output) { ++ case RK_IF_FORMAT_YCBCR_HQ: ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ *color_format = RK_IF_FORMAT_YCBCR444; ++ else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ *color_format = RK_IF_FORMAT_YCBCR422; ++ else if (conn_state->connector->ycbcr_420_allowed && ++ drm_mode_is_420(info, &mode) && ++ (pixclock >= 594000 && !hdmi->is_hdmi_qp)) ++ *color_format = RK_IF_FORMAT_YCBCR420; ++ break; ++ case RK_IF_FORMAT_YCBCR_LQ: ++ if (conn_state->connector->ycbcr_420_allowed && ++ drm_mode_is_420(info, &mode) && pixclock >= 594000) ++ *color_format = RK_IF_FORMAT_YCBCR420; ++ else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ *color_format = RK_IF_FORMAT_YCBCR422; ++ else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ *color_format = RK_IF_FORMAT_YCBCR444; ++ break; ++ case RK_IF_FORMAT_YCBCR420: ++ if (conn_state->connector->ycbcr_420_allowed && ++ drm_mode_is_420(info, &mode) && pixclock >= 594000) ++ *color_format = RK_IF_FORMAT_YCBCR420; ++ break; ++ case RK_IF_FORMAT_YCBCR422: ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ *color_format = RK_IF_FORMAT_YCBCR422; ++ break; ++ case RK_IF_FORMAT_YCBCR444: ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ *color_format = RK_IF_FORMAT_YCBCR444; ++ break; ++ case RK_IF_FORMAT_RGB: ++ default: ++ break; ++ } ++ ++ if (*color_format == RK_IF_FORMAT_RGB && ++ info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) ++ support_dc = true; ++ if (*color_format == RK_IF_FORMAT_YCBCR444 && ++ info->edid_hdmi_rgb444_dc_modes & ++ (DRM_EDID_HDMI_DC_Y444 | DRM_EDID_HDMI_DC_30)) ++ support_dc = true; ++ if (*color_format == RK_IF_FORMAT_YCBCR422) ++ support_dc = true; ++ if (*color_format == RK_IF_FORMAT_YCBCR420 && ++ info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) ++ support_dc = true; ++ ++ if (hdmi->colordepth > 8 && support_dc) ++ color_depth = 10; ++ else ++ color_depth = 8; ++ ++ if (!sink_is_hdmi) { ++ *color_format = RK_IF_FORMAT_RGB; ++ color_depth = 8; ++ } ++ ++ *eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR; ++ if (conn_state->hdr_output_metadata) { ++ hdr_metadata = (struct hdr_output_metadata *) ++ conn_state->hdr_output_metadata->data; ++ output_eotf = hdr_metadata->hdmi_metadata_type1.eotf; ++ if (output_eotf > HDMI_EOTF_TRADITIONAL_GAMMA_SDR && ++ output_eotf <= HDMI_EOTF_BT_2100_HLG) ++ *eotf = output_eotf; ++ } ++ ++ hdmi->colorimetry = conn_state->colorspace; ++ ++ if ((*eotf > HDMI_EOTF_TRADITIONAL_GAMMA_SDR && ++ conn_state->connector->hdr_sink_metadata.hdmi_type1.eotf & ++ BIT(*eotf)) || ((hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_CYCC) && ++ (hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_YCC))) ++ *enc_out_encoding = V4L2_YCBCR_ENC_BT2020; ++ else if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || ++ (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) ++ *enc_out_encoding = V4L2_YCBCR_ENC_601; ++ else ++ *enc_out_encoding = V4L2_YCBCR_ENC_709; ++ ++ if (*enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { ++ /* BT2020 require color depth at lest 10bit */ ++ color_depth = 10; ++ /* We prefer use YCbCr422 to send 10bit */ ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ *color_format = RK_IF_FORMAT_YCBCR422; ++ if (hdmi->is_hdmi_qp) { ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR420) { ++ if (mode.clock >= 340000) ++ *color_format = RK_IF_FORMAT_YCBCR420; ++ else ++ *color_format = RK_IF_FORMAT_RGB; ++ } else { ++ *color_format = RK_IF_FORMAT_RGB; ++ } ++ } ++ } ++ ++ if (mode.flags & DRM_MODE_FLAG_DBLCLK) ++ pixclock *= 2; ++ if ((mode.flags & DRM_MODE_FLAG_3D_MASK) == ++ DRM_MODE_FLAG_3D_FRAME_PACKING) ++ pixclock *= 2; ++ ++ if (*color_format == RK_IF_FORMAT_YCBCR422 || color_depth == 8) ++ tmdsclock = pixclock; ++ else ++ tmdsclock = pixclock * (color_depth) / 8; ++ ++ if (*color_format == RK_IF_FORMAT_YCBCR420) ++ tmdsclock /= 2; ++ ++ /* XXX: max_tmds_clock of some sink is 0, we think it is 340MHz. */ ++ if (!max_tmds_clock) ++ max_tmds_clock = 340000; ++ ++ max_tmds_clock = min(max_tmds_clock, hdmi->max_tmdsclk); ++ ++ if ((tmdsclock > max_tmds_clock) && !hdmi->is_hdmi_qp) { ++ if (max_tmds_clock >= 594000) { ++ color_depth = 8; ++ } else if (max_tmds_clock > 340000) { ++ if (drm_mode_is_420(info, &mode) || tmdsclock >= 594000) ++ *color_format = RK_IF_FORMAT_YCBCR420; ++ } else { ++ color_depth = 8; ++ if (drm_mode_is_420(info, &mode) || tmdsclock >= 594000) ++ *color_format = RK_IF_FORMAT_YCBCR420; ++ } ++ } ++ ++ if (hdmi->is_hdmi_qp) { ++ if (mode.clock >= 340000) { ++ if (drm_mode_is_420(info, &mode)) ++ *color_format = RK_IF_FORMAT_YCBCR420; ++ else ++ *color_format = RK_IF_FORMAT_RGB; ++ } else if (tmdsclock > max_tmds_clock) { ++ color_depth = 8; ++ if (drm_mode_is_420(info, &mode)) ++ *color_format = RK_IF_FORMAT_YCBCR420; ++ } ++ } ++ ++ if (*color_format == RK_IF_FORMAT_YCBCR420) { ++ *output_mode = ROCKCHIP_OUT_MODE_YUV420; ++ if (color_depth > 8) ++ *bus_format = MEDIA_BUS_FMT_UYYVYY10_0_5X30; ++ else ++ *bus_format = MEDIA_BUS_FMT_UYYVYY8_0_5X24; ++ *bus_width = color_depth / 2; ++ } else { ++ *output_mode = ROCKCHIP_OUT_MODE_AAAA; ++ if (color_depth > 8) { ++ if (*color_format != RK_IF_FORMAT_RGB && ++ !hdmi->unsupported_yuv_input) ++ *bus_format = MEDIA_BUS_FMT_YUV10_1X30; ++ else ++ *bus_format = MEDIA_BUS_FMT_RGB101010_1X30; ++ } else { ++ if (*color_format != RK_IF_FORMAT_RGB && ++ !hdmi->unsupported_yuv_input) ++ *bus_format = MEDIA_BUS_FMT_YUV8_1X24; ++ else ++ *bus_format = MEDIA_BUS_FMT_RGB888_1X24; ++ } ++ if (*color_format == RK_IF_FORMAT_YCBCR422) ++ *bus_width = 8; ++ else ++ *bus_width = color_depth; ++ } ++ ++ hdmi->bus_format = *bus_format; ++ ++ if (*color_format == RK_IF_FORMAT_YCBCR422) { ++ if (color_depth == 12) ++ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY12_1X24; ++ else if (color_depth == 10) ++ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY10_1X20; ++ else ++ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY8_1X16; ++ } else { ++ hdmi->output_bus_format = *bus_format; ++ } ++} ++ ++static bool ++dw_hdmi_rockchip_check_color(struct drm_connector_state *conn_state, ++ struct rockchip_hdmi *hdmi) ++{ ++ struct drm_crtc_state *crtc_state = conn_state->crtc->state; ++ unsigned int colorformat; ++ unsigned long bus_format; ++ unsigned long output_bus_format = hdmi->output_bus_format; ++ unsigned long enc_out_encoding = hdmi->enc_out_encoding; ++ unsigned int eotf, bus_width; ++ unsigned int output_mode; ++ ++ dw_hdmi_rockchip_select_output(conn_state, crtc_state, hdmi, ++ &colorformat, ++ &output_mode, &bus_format, &bus_width, ++ &hdmi->enc_out_encoding, &eotf); ++ ++ if (output_bus_format != hdmi->output_bus_format || ++ enc_out_encoding != hdmi->enc_out_encoding) ++ return true; ++ else ++ return false; ++} ++ ++static int ++dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) ++{ ++ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); ++ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); ++ unsigned int colorformat, bus_width, tmdsclk; ++ struct drm_display_mode mode; ++ unsigned int output_mode; ++ unsigned long bus_format; ++ int color_depth; ++ bool secondary = false; ++ ++ /* ++ * There are two hdmi but only one encoder in split mode, ++ * so we need to check twice. ++ */ ++secondary: ++ drm_mode_copy(&mode, &crtc_state->mode); ++ ++ hdmi->vp_id = 0; ++ // hdmi->vp_id = s->vp_id; ++ // if (hdmi->plat_data->split_mode) ++ // drm_mode_convert_to_origin_mode(&mode); ++ ++ int eotf; ++ dw_hdmi_rockchip_select_output(conn_state, crtc_state, hdmi, ++ &colorformat, ++ &output_mode, &bus_format, &bus_width, ++ // &hdmi->enc_out_encoding, &s->eotf); ++ &hdmi->enc_out_encoding, &eotf); ++ ++ s->bus_format = bus_format; ++ if (hdmi->is_hdmi_qp) { ++ color_depth = hdmi_bus_fmt_color_depth(bus_format); ++ tmdsclk = hdmi_get_tmdsclock(hdmi, crtc_state->mode.clock); ++ if (hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format)) ++ tmdsclk /= 2; ++ hdmi_select_link_config(hdmi, crtc_state, tmdsclk); ++ ++ if (hdmi->link_cfg.frl_mode) { ++ gpiod_set_value(hdmi->enable_gpio, 0); ++ /* in the current version, support max 40G frl */ ++ if (hdmi->link_cfg.rate_per_lane >= 10) { ++ hdmi->link_cfg.frl_lanes = 4; ++ hdmi->link_cfg.rate_per_lane = 10; ++ } ++ bus_width = hdmi->link_cfg.frl_lanes * ++ hdmi->link_cfg.rate_per_lane * 1000000; ++ /* 10 bit color depth and frl mode */ ++ if (color_depth == 10) ++ bus_width |= ++ COLOR_DEPTH_10BIT | HDMI_FRL_MODE; ++ else ++ bus_width |= HDMI_FRL_MODE; ++ } else { ++ gpiod_set_value(hdmi->enable_gpio, 1); ++ bus_width = hdmi_get_tmdsclock(hdmi, mode.clock * 10); ++ if (hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format)) ++ bus_width /= 2; ++ ++ if (color_depth == 10) ++ bus_width |= COLOR_DEPTH_10BIT; ++ } ++ } ++ ++ hdmi->phy_bus_width = bus_width; ++ ++ if (hdmi->phy) ++ phy_set_bus_width(hdmi->phy, bus_width); ++ ++ s->output_type = DRM_MODE_CONNECTOR_HDMIA; ++ // s->tv_state = &conn_state->tv; ++ // ++ // if (hdmi->plat_data->split_mode) { ++ // s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; ++ // if (hdmi->plat_data->right && hdmi->id) ++ // s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; ++ // s->output_if |= VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1; ++ // } else { ++ // if (!hdmi->id) ++ // s->output_if |= VOP_OUTPUT_IF_HDMI0; ++ // else ++ // s->output_if |= VOP_OUTPUT_IF_HDMI1; ++ // } ++ ++ s->output_mode = output_mode; ++ hdmi->bus_format = s->bus_format; ++ ++ if (hdmi->enc_out_encoding == V4L2_YCBCR_ENC_BT2020) ++ s->color_space = V4L2_COLORSPACE_BT2020; ++ else if (colorformat == RK_IF_FORMAT_RGB) ++ s->color_space = V4L2_COLORSPACE_DEFAULT; ++ else if (hdmi->enc_out_encoding == V4L2_YCBCR_ENC_709) ++ s->color_space = V4L2_COLORSPACE_REC709; ++ else ++ s->color_space = V4L2_COLORSPACE_SMPTE170M; ++ ++ if (hdmi->plat_data->split_mode && !secondary) { ++ hdmi = rockchip_hdmi_find_by_id(hdmi->dev->driver, !hdmi->id); ++ secondary = true; ++ goto secondary; ++ } + + return 0; + } + ++static unsigned long ++dw_hdmi_rockchip_get_input_bus_format(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ return hdmi->bus_format; ++} ++ ++static unsigned long ++dw_hdmi_rockchip_get_output_bus_format(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ return hdmi->output_bus_format; ++} ++ ++static unsigned long ++dw_hdmi_rockchip_get_enc_in_encoding(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ return hdmi->enc_out_encoding; ++} ++ ++static unsigned long ++dw_hdmi_rockchip_get_enc_out_encoding(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ return hdmi->enc_out_encoding; ++} ++ ++static unsigned long ++dw_hdmi_rockchip_get_quant_range(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ return hdmi->hdmi_quant_range; ++} ++ ++static struct drm_property * ++dw_hdmi_rockchip_get_hdr_property(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ return hdmi->hdr_panel_metadata_property; ++} ++ ++static struct drm_property_blob * ++dw_hdmi_rockchip_get_hdr_blob(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ return hdmi->hdr_panel_blob_ptr; ++} ++ ++static bool ++dw_hdmi_rockchip_get_color_changed(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ bool ret = false; ++ ++ if (hdmi->color_changed) ++ ret = true; ++ hdmi->color_changed = 0; ++ ++ return ret; ++} ++ ++#if 0 ++static int ++dw_hdmi_rockchip_get_edid_dsc_info(void *data, struct edid *edid) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ if (!edid) ++ return -EINVAL; ++ ++ return rockchip_drm_parse_cea_ext(&hdmi->dsc_cap, ++ &hdmi->max_frl_rate_per_lane, ++ &hdmi->max_lanes, edid); ++} ++ ++static int ++dw_hdmi_rockchip_get_next_hdr_data(void *data, struct edid *edid, ++ struct drm_connector *connector) ++{ ++ int ret; ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ struct next_hdr_sink_data *sink_data = &hdmi->next_hdr_data; ++ size_t size = sizeof(*sink_data); ++ struct drm_property *property = hdmi->next_hdr_sink_data_property; ++ struct drm_property_blob *blob = hdmi->hdr_panel_blob_ptr; ++ ++ if (!edid) ++ return -EINVAL; ++ ++ rockchip_drm_parse_next_hdr(sink_data, edid); ++ ++ ret = drm_property_replace_global_blob(connector->dev, &blob, size, sink_data, ++ &connector->base, property); ++ ++ return ret; ++}; ++#endif ++ ++static ++struct dw_hdmi_link_config *dw_hdmi_rockchip_get_link_cfg(void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ return &hdmi->link_cfg; ++} ++ ++#if 0 ++static const struct drm_prop_enum_list color_depth_enum_list[] = { ++ { 0, "Automatic" }, /* Prefer highest color depth */ ++ { 8, "24bit" }, ++ { 10, "30bit" }, ++}; ++ ++static const struct drm_prop_enum_list drm_hdmi_output_enum_list[] = { ++ { RK_IF_FORMAT_RGB, "rgb" }, ++ { RK_IF_FORMAT_YCBCR444, "ycbcr444" }, ++ { RK_IF_FORMAT_YCBCR422, "ycbcr422" }, ++ { RK_IF_FORMAT_YCBCR420, "ycbcr420" }, ++ { RK_IF_FORMAT_YCBCR_HQ, "ycbcr_high_subsampling" }, ++ { RK_IF_FORMAT_YCBCR_LQ, "ycbcr_low_subsampling" }, ++ { RK_IF_FORMAT_MAX, "invalid_output" }, ++}; ++ ++static const struct drm_prop_enum_list quant_range_enum_list[] = { ++ { HDMI_QUANTIZATION_RANGE_DEFAULT, "default" }, ++ { HDMI_QUANTIZATION_RANGE_LIMITED, "limit" }, ++ { HDMI_QUANTIZATION_RANGE_FULL, "full" }, ++}; ++ ++static const struct drm_prop_enum_list output_hdmi_dvi_enum_list[] = { ++ { 0, "auto" }, ++ { 1, "force_hdmi" }, ++ { 2, "force_dvi" }, ++}; ++ ++static const struct drm_prop_enum_list output_type_cap_list[] = { ++ { 0, "DVI" }, ++ { 1, "HDMI" }, ++}; ++#endif ++ ++static void ++dw_hdmi_rockchip_attach_properties(struct drm_connector *connector, ++ unsigned int color, int version, ++ void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ struct drm_property *prop; ++ // struct rockchip_drm_private *private = connector->dev->dev_private; ++ ++ switch (color) { ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ hdmi->hdmi_output = RK_IF_FORMAT_RGB; ++ hdmi->colordepth = 10; ++ break; ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR444; ++ hdmi->colordepth = 8; ++ break; ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR444; ++ hdmi->colordepth = 10; ++ break; ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR422; ++ hdmi->colordepth = 10; ++ break; ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR422; ++ hdmi->colordepth = 8; ++ break; ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR420; ++ hdmi->colordepth = 8; ++ break; ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ hdmi->hdmi_output = RK_IF_FORMAT_YCBCR420; ++ hdmi->colordepth = 10; ++ break; ++ default: ++ hdmi->hdmi_output = RK_IF_FORMAT_RGB; ++ hdmi->colordepth = 8; ++ } ++ ++ hdmi->bus_format = color; ++ ++ if (hdmi->hdmi_output == RK_IF_FORMAT_YCBCR422) { ++ if (hdmi->colordepth == 12) ++ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY12_1X24; ++ else if (hdmi->colordepth == 10) ++ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY10_1X20; ++ else ++ hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY8_1X16; ++ } else { ++ hdmi->output_bus_format = hdmi->bus_format; ++ } ++ ++#if 0 ++ /* RK3368 does not support deep color mode */ ++ if (!hdmi->color_depth_property && !hdmi->unsupported_deep_color) { ++ prop = drm_property_create_enum(connector->dev, 0, ++ RK_IF_PROP_COLOR_DEPTH, ++ color_depth_enum_list, ++ ARRAY_SIZE(color_depth_enum_list)); ++ if (prop) { ++ hdmi->color_depth_property = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ } ++ ++ prop = drm_property_create_enum(connector->dev, 0, RK_IF_PROP_COLOR_FORMAT, ++ drm_hdmi_output_enum_list, ++ ARRAY_SIZE(drm_hdmi_output_enum_list)); ++ if (prop) { ++ hdmi->hdmi_output_property = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ ++ prop = drm_property_create_range(connector->dev, 0, ++ RK_IF_PROP_COLOR_DEPTH_CAPS, ++ 0, 0xff); ++ if (prop) { ++ hdmi->colordepth_capacity = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ ++ prop = drm_property_create_range(connector->dev, 0, ++ RK_IF_PROP_COLOR_FORMAT_CAPS, ++ 0, 0xf); ++ if (prop) { ++ hdmi->outputmode_capacity = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ ++ prop = drm_property_create(connector->dev, ++ DRM_MODE_PROP_BLOB | ++ DRM_MODE_PROP_IMMUTABLE, ++ "HDR_PANEL_METADATA", 0); ++ if (prop) { ++ hdmi->hdr_panel_metadata_property = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ ++ prop = drm_property_create(connector->dev, ++ DRM_MODE_PROP_BLOB | ++ DRM_MODE_PROP_IMMUTABLE, ++ "NEXT_HDR_SINK_DATA", 0); ++ if (prop) { ++ hdmi->next_hdr_sink_data_property = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ ++ prop = drm_property_create_bool(connector->dev, DRM_MODE_PROP_IMMUTABLE, ++ "USER_SPLIT_MODE"); ++ if (prop) { ++ hdmi->user_split_mode_prop = prop; ++ drm_object_attach_property(&connector->base, prop, ++ hdmi->user_split_mode ? 1 : 0); ++ } ++ ++ if (!hdmi->is_hdmi_qp) { ++ prop = drm_property_create_enum(connector->dev, 0, ++ "output_hdmi_dvi", ++ output_hdmi_dvi_enum_list, ++ ARRAY_SIZE(output_hdmi_dvi_enum_list)); ++ if (prop) { ++ hdmi->output_hdmi_dvi = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ ++ prop = drm_property_create_enum(connector->dev, 0, ++ "output_type_capacity", ++ output_type_cap_list, ++ ARRAY_SIZE(output_type_cap_list)); ++ if (prop) { ++ hdmi->output_type_capacity = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ ++ prop = drm_property_create_enum(connector->dev, 0, ++ "hdmi_quant_range", ++ quant_range_enum_list, ++ ARRAY_SIZE(quant_range_enum_list)); ++ if (prop) { ++ hdmi->quant_range = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ } ++#endif ++ ++ prop = connector->dev->mode_config.hdr_output_metadata_property; ++ if (version >= 0x211a || hdmi->is_hdmi_qp) ++ drm_object_attach_property(&connector->base, prop, 0); ++ ++ if (!drm_mode_create_hdmi_colorspace_property(connector, 0)) ++ drm_object_attach_property(&connector->base, ++ connector->colorspace_property, 0); ++ ++#if 0 ++ // [CC:] if this is not needed, also drop connector_id_prop ++ if (!private->connector_id_prop) ++ private->connector_id_prop = drm_property_create_range(connector->dev, ++ DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_IMMUTABLE, ++ "CONNECTOR_ID", 0, 0xf); ++ if (private->connector_id_prop) ++ drm_object_attach_property(&connector->base, private->connector_id_prop, hdmi->id); ++#endif ++} ++ ++static void ++dw_hdmi_rockchip_destroy_properties(struct drm_connector *connector, ++ void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ if (hdmi->color_depth_property) { ++ drm_property_destroy(connector->dev, ++ hdmi->color_depth_property); ++ hdmi->color_depth_property = NULL; ++ } ++ ++ if (hdmi->hdmi_output_property) { ++ drm_property_destroy(connector->dev, ++ hdmi->hdmi_output_property); ++ hdmi->hdmi_output_property = NULL; ++ } ++ ++ if (hdmi->colordepth_capacity) { ++ drm_property_destroy(connector->dev, ++ hdmi->colordepth_capacity); ++ hdmi->colordepth_capacity = NULL; ++ } ++ ++ if (hdmi->outputmode_capacity) { ++ drm_property_destroy(connector->dev, ++ hdmi->outputmode_capacity); ++ hdmi->outputmode_capacity = NULL; ++ } ++ ++ if (hdmi->quant_range) { ++ drm_property_destroy(connector->dev, ++ hdmi->quant_range); ++ hdmi->quant_range = NULL; ++ } ++ ++ if (hdmi->hdr_panel_metadata_property) { ++ drm_property_destroy(connector->dev, ++ hdmi->hdr_panel_metadata_property); ++ hdmi->hdr_panel_metadata_property = NULL; ++ } ++ ++ if (hdmi->next_hdr_sink_data_property) { ++ drm_property_destroy(connector->dev, ++ hdmi->next_hdr_sink_data_property); ++ hdmi->next_hdr_sink_data_property = NULL; ++ } ++ ++ if (hdmi->output_hdmi_dvi) { ++ drm_property_destroy(connector->dev, ++ hdmi->output_hdmi_dvi); ++ hdmi->output_hdmi_dvi = NULL; ++ } ++ ++ if (hdmi->output_type_capacity) { ++ drm_property_destroy(connector->dev, ++ hdmi->output_type_capacity); ++ hdmi->output_type_capacity = NULL; ++ } ++ ++ if (hdmi->user_split_mode_prop) { ++ drm_property_destroy(connector->dev, ++ hdmi->user_split_mode_prop); ++ hdmi->user_split_mode_prop = NULL; ++ } ++} ++ ++static int ++dw_hdmi_rockchip_set_property(struct drm_connector *connector, ++ struct drm_connector_state *state, ++ struct drm_property *property, ++ u64 val, ++ void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ struct drm_mode_config *config = &connector->dev->mode_config; ++ ++ if (property == hdmi->color_depth_property) { ++ hdmi->colordepth = val; ++ /* If hdmi is disconnected, state->crtc is null */ ++ if (!state->crtc) ++ return 0; ++ if (dw_hdmi_rockchip_check_color(state, hdmi)) ++ hdmi->color_changed++; ++ return 0; ++ } else if (property == hdmi->hdmi_output_property) { ++ hdmi->hdmi_output = val; ++ if (!state->crtc) ++ return 0; ++ if (dw_hdmi_rockchip_check_color(state, hdmi)) ++ hdmi->color_changed++; ++ return 0; ++ } else if (property == hdmi->quant_range) { ++ u64 quant_range = hdmi->hdmi_quant_range; ++ ++ hdmi->hdmi_quant_range = val; ++ if (quant_range != hdmi->hdmi_quant_range) ++ dw_hdmi_set_quant_range(hdmi->hdmi); ++ return 0; ++ } else if (property == config->hdr_output_metadata_property) { ++ return 0; ++ } else if (property == hdmi->output_hdmi_dvi) { ++ if (hdmi->force_output != val) ++ hdmi->color_changed++; ++ hdmi->force_output = val; ++ dw_hdmi_set_output_type(hdmi->hdmi, val); ++ return 0; ++ } else if (property == hdmi->colordepth_capacity) { ++ return 0; ++ } else if (property == hdmi->outputmode_capacity) { ++ return 0; ++ } else if (property == hdmi->output_type_capacity) { ++ return 0; ++ } ++ ++ DRM_ERROR("Unknown property [PROP:%d:%s]\n", ++ property->base.id, property->name); ++ ++ return -EINVAL; ++} ++ ++static int ++dw_hdmi_rockchip_get_property(struct drm_connector *connector, ++ const struct drm_connector_state *state, ++ struct drm_property *property, ++ u64 *val, ++ void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ struct drm_display_info *info = &connector->display_info; ++ struct drm_mode_config *config = &connector->dev->mode_config; ++ ++ if (property == hdmi->color_depth_property) { ++ *val = hdmi->colordepth; ++ return 0; ++ } else if (property == hdmi->hdmi_output_property) { ++ *val = hdmi->hdmi_output; ++ return 0; ++ } else if (property == hdmi->colordepth_capacity) { ++ *val = BIT(RK_IF_DEPTH_8); ++ /* RK3368 only support 8bit */ ++ if (hdmi->unsupported_deep_color) ++ return 0; ++ if (info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) ++ *val |= BIT(RK_IF_DEPTH_10); ++ if (info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36) ++ *val |= BIT(RK_IF_DEPTH_12); ++ if (info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_48) ++ *val |= BIT(RK_IF_DEPTH_16); ++ if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) ++ *val |= BIT(RK_IF_DEPTH_420_10); ++ if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) ++ *val |= BIT(RK_IF_DEPTH_420_12); ++ if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) ++ *val |= BIT(RK_IF_DEPTH_420_16); ++ return 0; ++ } else if (property == hdmi->outputmode_capacity) { ++ *val = BIT(RK_IF_FORMAT_RGB); ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ *val |= BIT(RK_IF_FORMAT_YCBCR444); ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ *val |= BIT(RK_IF_FORMAT_YCBCR422); ++ if (connector->ycbcr_420_allowed && ++ info->color_formats & DRM_COLOR_FORMAT_YCBCR420) ++ *val |= BIT(RK_IF_FORMAT_YCBCR420); ++ return 0; ++ } else if (property == hdmi->quant_range) { ++ *val = hdmi->hdmi_quant_range; ++ return 0; ++ } else if (property == config->hdr_output_metadata_property) { ++ *val = state->hdr_output_metadata ? ++ state->hdr_output_metadata->base.id : 0; ++ return 0; ++ } else if (property == hdmi->output_hdmi_dvi) { ++ *val = hdmi->force_output; ++ return 0; ++ } else if (property == hdmi->output_type_capacity) { ++ *val = dw_hdmi_get_output_type_cap(hdmi->hdmi); ++ return 0; ++ } else if (property == hdmi->user_split_mode_prop) { ++ *val = hdmi->user_split_mode; ++ return 0; ++ } ++ ++ DRM_ERROR("Unknown property [PROP:%d:%s]\n", ++ property->base.id, property->name); ++ ++ return -EINVAL; ++} ++ ++static const struct dw_hdmi_property_ops dw_hdmi_rockchip_property_ops = { ++ .attach_properties = dw_hdmi_rockchip_attach_properties, ++ .destroy_properties = dw_hdmi_rockchip_destroy_properties, ++ .set_property = dw_hdmi_rockchip_set_property, ++ .get_property = dw_hdmi_rockchip_get_property, ++}; ++ + static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { + .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, + .mode_set = dw_hdmi_rockchip_encoder_mode_set, +@@ -356,20 +2518,24 @@ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_fun + .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, + }; + +-static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, +- const struct drm_display_info *display, +- const struct drm_display_mode *mode) ++static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) + { + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + +- return phy_power_on(hdmi->phy); ++ while (hdmi->phy->power_count > 0) ++ phy_power_off(hdmi->phy); + } + +-static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) ++static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, ++ const struct drm_display_info *display, ++ const struct drm_display_mode *mode) + { + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + +- phy_power_off(hdmi->phy); ++ dw_hdmi_rockchip_genphy_disable(dw_hdmi, data); ++ dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display); ++ ++ return phy_power_on(hdmi->phy); + } + + static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) +@@ -436,6 +2602,90 @@ static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) + RK3328_HDMI_HPD_IOE)); + } + ++static void dw_hdmi_qp_rockchip_phy_disable(struct dw_hdmi_qp *dw_hdmi, ++ void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ while (hdmi->phy->power_count > 0) ++ phy_power_off(hdmi->phy); ++} ++ ++static int dw_hdmi_qp_rockchip_genphy_init(struct dw_hdmi_qp *dw_hdmi, void *data, ++ struct drm_display_mode *mode) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ dw_hdmi_qp_rockchip_phy_disable(dw_hdmi, data); ++ ++ return phy_power_on(hdmi->phy); ++} ++ ++static enum drm_connector_status ++dw_hdmi_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) ++{ ++ u32 val; ++ int ret; ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val); ++ ++ if (!hdmi->id) { ++ if (val & RK3588_HDMI0_LEVEL_INT) { ++ hdmi->hpd_stat = true; ++ ret = connector_status_connected; ++ } else { ++ hdmi->hpd_stat = false; ++ ret = connector_status_disconnected; ++ } ++ } else { ++ if (val & RK3588_HDMI1_LEVEL_INT) { ++ hdmi->hpd_stat = true; ++ ret = connector_status_connected; ++ } else { ++ hdmi->hpd_stat = false; ++ ret = connector_status_disconnected; ++ } ++ } ++ ++ return ret; ++} ++ ++static void dw_hdmi_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ u32 val; ++ ++ if (!hdmi->id) { ++ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, ++ RK3588_HDMI0_HPD_INT_CLR) | ++ HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); ++ } else { ++ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, ++ RK3588_HDMI1_HPD_INT_CLR) | ++ HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK); ++ } ++ ++ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); ++} ++ ++static void dw_hdmi_rk3588_phy_set_mode(struct dw_hdmi_qp *dw_hdmi, void *data, ++ u32 mode_mask, bool enable) ++{ ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ ++ if (!hdmi->phy) ++ return; ++ ++ /* set phy earc/frl mode */ ++ if (enable) ++ hdmi->phy_bus_width |= mode_mask; ++ else ++ hdmi->phy_bus_width &= ~mode_mask; ++ ++ phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); ++} ++ + static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { + .init = dw_hdmi_rockchip_genphy_init, + .disable = dw_hdmi_rockchip_genphy_disable, +@@ -525,6 +2775,30 @@ static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { + .use_drm_infoframe = true, + }; + ++static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = { ++ .init = dw_hdmi_qp_rockchip_genphy_init, ++ .disable = dw_hdmi_qp_rockchip_phy_disable, ++ .read_hpd = dw_hdmi_rk3588_read_hpd, ++ .setup_hpd = dw_hdmi_rk3588_setup_hpd, ++ .set_mode = dw_hdmi_rk3588_phy_set_mode, ++}; ++ ++struct rockchip_hdmi_chip_data rk3588_hdmi_chip_data = { ++ .lcdsel_grf_reg = -1, ++ .ddc_en_reg = RK3588_GRF_VO1_CON3, ++ .split_mode = true, ++}; ++ ++static const struct dw_hdmi_plat_data rk3588_hdmi_drv_data = { ++ .phy_data = &rk3588_hdmi_chip_data, ++ .qp_phy_ops = &rk3588_hdmi_phy_ops, ++ .phy_name = "samsung_hdptx_phy", ++ .phy_force_vendor = true, ++ .ycbcr_420_allowed = true, ++ .is_hdmi_qp = true, ++ .use_drm_infoframe = true, ++}; ++ + static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3228-dw-hdmi", + .data = &rk3228_hdmi_drv_data +@@ -541,6 +2815,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3568-dw-hdmi", + .data = &rk3568_hdmi_drv_data + }, ++ { .compatible = "rockchip,rk3588-dw-hdmi", ++ .data = &rk3588_hdmi_drv_data ++ }, + {}, + }; + MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); +@@ -550,44 +2827,103 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + { + struct platform_device *pdev = to_platform_device(dev); + struct dw_hdmi_plat_data *plat_data; +- const struct of_device_id *match; + struct drm_device *drm = data; + struct drm_encoder *encoder; + struct rockchip_hdmi *hdmi; ++ struct rockchip_hdmi *secondary; + int ret; ++ u32 val; + + if (!pdev->dev.of_node) + return -ENODEV; + +- hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); ++ hdmi = platform_get_drvdata(pdev); + if (!hdmi) + return -ENOMEM; + +- match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); +- plat_data = devm_kmemdup(&pdev->dev, match->data, +- sizeof(*plat_data), GFP_KERNEL); +- if (!plat_data) +- return -ENOMEM; ++ plat_data = hdmi->plat_data; ++ hdmi->drm_dev = drm; + +- hdmi->dev = &pdev->dev; +- hdmi->plat_data = plat_data; +- hdmi->chip_data = plat_data->phy_data; + plat_data->phy_data = hdmi; +- plat_data->priv_data = hdmi; +- encoder = &hdmi->encoder.encoder; ++ plat_data->get_input_bus_format = ++ dw_hdmi_rockchip_get_input_bus_format; ++ plat_data->get_output_bus_format = ++ dw_hdmi_rockchip_get_output_bus_format; ++ plat_data->get_enc_in_encoding = ++ dw_hdmi_rockchip_get_enc_in_encoding; ++ plat_data->get_enc_out_encoding = ++ dw_hdmi_rockchip_get_enc_out_encoding; ++ plat_data->get_quant_range = ++ dw_hdmi_rockchip_get_quant_range; ++ plat_data->get_hdr_property = ++ dw_hdmi_rockchip_get_hdr_property; ++ plat_data->get_hdr_blob = ++ dw_hdmi_rockchip_get_hdr_blob; ++ plat_data->get_color_changed = ++ dw_hdmi_rockchip_get_color_changed; ++ // plat_data->get_edid_dsc_info = ++ // dw_hdmi_rockchip_get_edid_dsc_info; ++ // plat_data->get_next_hdr_data = ++ // dw_hdmi_rockchip_get_next_hdr_data; ++ plat_data->get_link_cfg = dw_hdmi_rockchip_get_link_cfg; ++ plat_data->set_grf_cfg = rk3588_set_grf_cfg; ++ // plat_data->convert_to_split_mode = drm_mode_convert_to_split_mode; ++ // plat_data->convert_to_origin_mode = drm_mode_convert_to_origin_mode; ++ ++ plat_data->property_ops = &dw_hdmi_rockchip_property_ops; ++ ++ secondary = rockchip_hdmi_find_by_id(dev->driver, !hdmi->id); ++ /* If don't enable hdmi0 and hdmi1, we don't enable split mode */ ++ if (hdmi->chip_data->split_mode && secondary) { + +- encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); +- rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, +- dev->of_node, 0, 0); ++ /* ++ * hdmi can only attach bridge and init encoder/connector in the ++ * last bind hdmi in split mode, or hdmi->hdmi_qp will not be initialized ++ * and plat_data->left/right will be null pointer. we must check if split ++ * mode is on and determine the sequence of hdmi bind. ++ */ ++ if (device_property_read_bool(dev, "split-mode") || ++ device_property_read_bool(secondary->dev, "split-mode")) { ++ plat_data->split_mode = true; ++ secondary->plat_data->split_mode = true; ++ if (!secondary->plat_data->first_screen) ++ plat_data->first_screen = true; ++ } ++ ++ if (device_property_read_bool(dev, "user-split-mode") || ++ device_property_read_bool(secondary->dev, "user-split-mode")) { ++ hdmi->user_split_mode = true; ++ secondary->user_split_mode = true; ++ } ++ } ++ ++ if (!plat_data->first_screen) { ++ encoder = &hdmi->encoder.encoder; ++ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); ++ rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, ++ dev->of_node, 0, 0); ++ /* ++ * If we failed to find the CRTC(s) which this encoder is ++ * supposed to be connected to, it's because the CRTC has ++ * not been registered yet. Defer probing, and hope that ++ * the required CRTC is added later. ++ */ ++ if (encoder->possible_crtcs == 0) ++ return -EPROBE_DEFER; ++ ++ drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); ++ // [CC:] consider using drmm_simple_encoder_alloc() ++ drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); ++ } ++ ++ if (!plat_data->max_tmdsclk) ++ hdmi->max_tmdsclk = 594000; ++ else ++ hdmi->max_tmdsclk = plat_data->max_tmdsclk; + +- /* +- * If we failed to find the CRTC(s) which this encoder is +- * supposed to be connected to, it's because the CRTC has +- * not been registered yet. Defer probing, and hope that +- * the required CRTC is added later. +- */ +- if (encoder->possible_crtcs == 0) +- return -EPROBE_DEFER; ++ ++ hdmi->unsupported_yuv_input = plat_data->unsupported_yuv_input; ++ hdmi->unsupported_deep_color = plat_data->unsupported_deep_color; + + ret = rockchip_hdmi_parse_dt(hdmi); + if (ret) { +@@ -596,34 +2932,44 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + return ret; + } + +- hdmi->phy = devm_phy_optional_get(dev, "hdmi"); +- if (IS_ERR(hdmi->phy)) { +- ret = PTR_ERR(hdmi->phy); +- if (ret != -EPROBE_DEFER) +- DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); ++ ret = clk_prepare_enable(hdmi->aud_clk); ++ if (ret) { ++ dev_err(hdmi->dev, "Failed to enable HDMI aud_clk: %d\n", ret); + return ret; + } + +- ret = regulator_enable(hdmi->avdd_0v9); ++ ret = clk_prepare_enable(hdmi->hpd_clk); + if (ret) { +- DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); +- goto err_avdd_0v9; ++ dev_err(hdmi->dev, "Failed to enable HDMI hpd_clk: %d\n", ret); ++ return ret; + } + +- ret = regulator_enable(hdmi->avdd_1v8); ++ ret = clk_prepare_enable(hdmi->hclk_vo1); + if (ret) { +- DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); +- goto err_avdd_1v8; ++ dev_err(hdmi->dev, "Failed to enable HDMI hclk_vo1: %d\n", ret); ++ return ret; + } + +- ret = clk_prepare_enable(hdmi->ref_clk); ++ ret = clk_prepare_enable(hdmi->earc_clk); + if (ret) { +- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", +- ret); +- goto err_clk; ++ dev_err(hdmi->dev, "Failed to enable HDMI earc_clk: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(hdmi->hdmitx_ref); ++ if (ret) { ++ dev_err(hdmi->dev, "Failed to enable HDMI hdmitx_ref: %d\n", ++ ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(hdmi->pclk); ++ if (ret) { ++ dev_err(hdmi->dev, "Failed to enable HDMI pclk: %d\n", ret); ++ return ret; + } + +- if (hdmi->chip_data == &rk3568_chip_data) { ++ if (hdmi->chip_data->ddc_en_reg == RK3568_GRF_VO_CON1) { + regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, + HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | + RK3568_HDMI_SCLIN_MSK, +@@ -631,12 +2977,131 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + RK3568_HDMI_SCLIN_MSK)); + } + +- drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); +- drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); ++ if (hdmi->is_hdmi_qp) { ++ if (!hdmi->id) { ++ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | ++ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | ++ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | ++ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); ++ ++ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, ++ RK3588_SET_HPD_PATH_MASK); ++ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); ++ ++ val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, ++ RK3588_HDMI0_GRANT_SEL); ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); ++ } else { ++ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | ++ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | ++ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | ++ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); ++ ++ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, ++ RK3588_SET_HPD_PATH_MASK); ++ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); ++ ++ val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, ++ RK3588_HDMI1_GRANT_SEL); ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); ++ } ++ } + +- platform_set_drvdata(pdev, hdmi); ++ ret = clk_prepare_enable(hdmi->hclk_vio); ++ if (ret) { ++ dev_err(hdmi->dev, "Failed to enable HDMI hclk_vio: %d\n", ++ ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(hdmi->hclk_vop); ++ if (ret) { ++ dev_err(hdmi->dev, "Failed to enable HDMI hclk_vop: %d\n", ++ ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(hdmi->ref_clk); ++ if (ret) { ++ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", ++ ret); ++ goto err_clk; ++ } ++ ++ ret = regulator_enable(hdmi->avdd_0v9); ++ if (ret) { ++ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); ++ goto err_avdd_0v9; ++ } ++ ++ ret = regulator_enable(hdmi->avdd_1v8); ++ if (ret) { ++ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); ++ goto err_avdd_1v8; ++ } ++ ++ if (!hdmi->id) ++ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK); ++ else ++ val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, RK3588_HDMI1_HPD_INT_MSK); ++ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); ++ ++ if (hdmi->is_hdmi_qp) { ++ hdmi->hpd_irq = platform_get_irq(pdev, 4); ++ if (hdmi->hpd_irq < 0) ++ return hdmi->hpd_irq; ++ ++ ret = devm_request_threaded_irq(hdmi->dev, hdmi->hpd_irq, ++ rockchip_hdmi_hardirq, ++ rockchip_hdmi_irq, ++ IRQF_SHARED, "dw-hdmi-qp-hpd", ++ hdmi); ++ if (ret) ++ return ret; ++ } ++ ++ hdmi->phy = devm_phy_optional_get(dev, "hdmi"); ++ if (IS_ERR(hdmi->phy)) { ++ hdmi->phy = devm_phy_optional_get(dev, "hdmi_phy"); ++ if (IS_ERR(hdmi->phy)) { ++ ret = PTR_ERR(hdmi->phy); ++ if (ret != -EPROBE_DEFER) ++ DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); ++ return ret; ++ } ++ } ++ ++ if (hdmi->is_hdmi_qp) { ++ // [CC:] do proper error handling, e.g. clk_disable_unprepare ++ hdmi->hdmi_qp = dw_hdmi_qp_bind(pdev, &hdmi->encoder.encoder, plat_data); ++ ++ if (IS_ERR(hdmi->hdmi_qp)) { ++ ret = PTR_ERR(hdmi->hdmi_qp); ++ drm_encoder_cleanup(&hdmi->encoder.encoder); ++ } ++ ++ // if (plat_data->connector) { ++ // hdmi->sub_dev.connector = plat_data->connector; ++ // hdmi->sub_dev.of_node = dev->of_node; ++ // rockchip_drm_register_sub_dev(&hdmi->sub_dev); ++ // } ++ ++ if (plat_data->split_mode && secondary) { ++ if (device_property_read_bool(dev, "split-mode")) { ++ plat_data->right = secondary->hdmi_qp; ++ secondary->plat_data->left = hdmi->hdmi_qp; ++ } else { ++ plat_data->left = secondary->hdmi_qp; ++ secondary->plat_data->right = hdmi->hdmi_qp; ++ } ++ } ++ ++ return ret; ++ } + +- hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); ++ hdmi->hdmi = dw_hdmi_bind(pdev, &hdmi->encoder.encoder, plat_data); + + /* + * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), +@@ -647,11 +3112,24 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + goto err_bind; + } + ++ // if (plat_data->connector) { ++ // hdmi->sub_dev.connector = plat_data->connector; ++ // hdmi->sub_dev.of_node = dev->of_node; ++ // rockchip_drm_register_sub_dev(&hdmi->sub_dev); ++ // } ++ + return 0; + + err_bind: +- drm_encoder_cleanup(encoder); ++ drm_encoder_cleanup(&hdmi->encoder.encoder); ++ clk_disable_unprepare(hdmi->aud_clk); + clk_disable_unprepare(hdmi->ref_clk); ++ clk_disable_unprepare(hdmi->hclk_vop); ++ clk_disable_unprepare(hdmi->hpd_clk); ++ clk_disable_unprepare(hdmi->hclk_vo1); ++ clk_disable_unprepare(hdmi->earc_clk); ++ clk_disable_unprepare(hdmi->hdmitx_ref); ++ clk_disable_unprepare(hdmi->pclk); + err_clk: + regulator_disable(hdmi->avdd_1v8); + err_avdd_1v8: +@@ -665,9 +3143,29 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, + { + struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); + +- dw_hdmi_unbind(hdmi->hdmi); ++ if (hdmi->is_hdmi_qp) { ++ cancel_delayed_work(&hdmi->work); ++ flush_workqueue(hdmi->workqueue); ++ } ++ ++ // if (hdmi->sub_dev.connector) ++ // rockchip_drm_unregister_sub_dev(&hdmi->sub_dev); ++ // ++ if (hdmi->is_hdmi_qp) ++ dw_hdmi_qp_unbind(hdmi->hdmi_qp); ++ else ++ dw_hdmi_unbind(hdmi->hdmi); ++ + drm_encoder_cleanup(&hdmi->encoder.encoder); ++ ++ clk_disable_unprepare(hdmi->aud_clk); + clk_disable_unprepare(hdmi->ref_clk); ++ clk_disable_unprepare(hdmi->hclk_vop); ++ clk_disable_unprepare(hdmi->hpd_clk); ++ clk_disable_unprepare(hdmi->hclk_vo1); ++ clk_disable_unprepare(hdmi->earc_clk); ++ clk_disable_unprepare(hdmi->hdmitx_ref); ++ clk_disable_unprepare(hdmi->pclk); + + regulator_disable(hdmi->avdd_1v8); + regulator_disable(hdmi->avdd_0v9); +@@ -680,30 +3178,142 @@ static const struct component_ops dw_hdmi_rockchip_ops = { + + static int dw_hdmi_rockchip_probe(struct platform_device *pdev) + { ++ struct rockchip_hdmi *hdmi; ++ const struct of_device_id *match; ++ struct dw_hdmi_plat_data *plat_data; ++ int id; ++ ++ hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); ++ if (!hdmi) ++ return -ENOMEM; ++ ++ id = of_alias_get_id(pdev->dev.of_node, "hdmi"); ++ if (id < 0) ++ id = 0; ++ ++ hdmi->id = id; ++ hdmi->dev = &pdev->dev; ++ ++ match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); ++ plat_data = devm_kmemdup(&pdev->dev, match->data, ++ sizeof(*plat_data), GFP_KERNEL); ++ if (!plat_data) ++ return -ENOMEM; ++ ++ plat_data->id = hdmi->id; ++ hdmi->plat_data = plat_data; ++ hdmi->chip_data = plat_data->phy_data; ++ hdmi->is_hdmi_qp = plat_data->is_hdmi_qp; ++ ++ if (hdmi->is_hdmi_qp) { ++ hdmi->workqueue = create_workqueue("hpd_queue"); ++ INIT_DELAYED_WORK(&hdmi->work, repo_hpd_event); ++ } ++ ++ platform_set_drvdata(pdev, hdmi); ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_get_sync(&pdev->dev); ++ + return component_add(&pdev->dev, &dw_hdmi_rockchip_ops); + } + ++static void dw_hdmi_rockchip_shutdown(struct platform_device *pdev) ++{ ++ struct rockchip_hdmi *hdmi = dev_get_drvdata(&pdev->dev); ++ ++ if (!hdmi) ++ return; ++ ++ if (hdmi->is_hdmi_qp) { ++ cancel_delayed_work(&hdmi->work); ++ flush_workqueue(hdmi->workqueue); ++ dw_hdmi_qp_suspend(hdmi->dev, hdmi->hdmi_qp); ++ } else { ++ dw_hdmi_suspend(hdmi->hdmi); ++ } ++ pm_runtime_put_sync(&pdev->dev); ++} ++ + static void dw_hdmi_rockchip_remove(struct platform_device *pdev) + { ++ struct rockchip_hdmi *hdmi = dev_get_drvdata(&pdev->dev); ++ + component_del(&pdev->dev, &dw_hdmi_rockchip_ops); ++ pm_runtime_disable(&pdev->dev); ++ ++ if (hdmi->is_hdmi_qp) ++ destroy_workqueue(hdmi->workqueue); ++} ++ ++static int __maybe_unused dw_hdmi_rockchip_suspend(struct device *dev) ++{ ++ struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); ++ ++ if (hdmi->is_hdmi_qp) ++ dw_hdmi_qp_suspend(dev, hdmi->hdmi_qp); ++ else ++ dw_hdmi_suspend(hdmi->hdmi); ++ ++ pm_runtime_put_sync(dev); ++ ++ return 0; + } + + static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev) + { + struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); ++ u32 val; + +- dw_hdmi_resume(hdmi->hdmi); ++ if (hdmi->is_hdmi_qp) { ++ if (!hdmi->id) { ++ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | ++ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | ++ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | ++ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); ++ ++ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, ++ RK3588_SET_HPD_PATH_MASK); ++ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); ++ ++ val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, ++ RK3588_HDMI0_GRANT_SEL); ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); ++ } else { ++ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | ++ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | ++ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | ++ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); ++ ++ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, ++ RK3588_SET_HPD_PATH_MASK); ++ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); ++ ++ val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, ++ RK3588_HDMI1_GRANT_SEL); ++ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); ++ } ++ ++ dw_hdmi_qp_resume(dev, hdmi->hdmi_qp); ++ drm_helper_hpd_irq_event(hdmi->drm_dev); ++ } else { ++ dw_hdmi_resume(hdmi->hdmi); ++ } ++ pm_runtime_get_sync(dev); + + return 0; + } + + static const struct dev_pm_ops dw_hdmi_rockchip_pm = { +- SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume) ++ SET_SYSTEM_SLEEP_PM_OPS(dw_hdmi_rockchip_suspend, ++ dw_hdmi_rockchip_resume) + }; + + struct platform_driver dw_hdmi_rockchip_pltfm_driver = { + .probe = dw_hdmi_rockchip_probe, + .remove_new = dw_hdmi_rockchip_remove, ++ .shutdown = dw_hdmi_rockchip_shutdown, + .driver = { + .name = "dwhdmi-rockchip", + .pm = &dw_hdmi_rockchip_pm, +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index 111111111111..222222222222 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -6,12 +6,14 @@ + #ifndef __DW_HDMI__ + #define __DW_HDMI__ + ++#include + #include + + struct drm_display_info; + struct drm_display_mode; + struct drm_encoder; + struct dw_hdmi; ++struct dw_hdmi_qp; + struct platform_device; + + /** +@@ -92,6 +94,13 @@ enum dw_hdmi_phy_type { + DW_HDMI_PHY_VENDOR_PHY = 0xfe, + }; + ++struct dw_hdmi_audio_tmds_n { ++ unsigned long tmds; ++ unsigned int n_32k; ++ unsigned int n_44k1; ++ unsigned int n_48k; ++}; ++ + struct dw_hdmi_mpll_config { + unsigned long mpixelclock; + struct { +@@ -112,6 +121,15 @@ struct dw_hdmi_phy_config { + u16 vlev_ctr; /* voltage level control */ + }; + ++struct dw_hdmi_link_config { ++ bool dsc_mode; ++ bool frl_mode; ++ int frl_lanes; ++ int rate_per_lane; ++ int hcactive; ++ u8 pps_payload[128]; ++}; ++ + struct dw_hdmi_phy_ops { + int (*init)(struct dw_hdmi *hdmi, void *data, + const struct drm_display_info *display, +@@ -123,14 +141,52 @@ struct dw_hdmi_phy_ops { + void (*setup_hpd)(struct dw_hdmi *hdmi, void *data); + }; + ++struct dw_hdmi_qp_phy_ops { ++ int (*init)(struct dw_hdmi_qp *hdmi, void *data, ++ struct drm_display_mode *mode); ++ void (*disable)(struct dw_hdmi_qp *hdmi, void *data); ++ enum drm_connector_status (*read_hpd)(struct dw_hdmi_qp *hdmi, ++ void *data); ++ void (*update_hpd)(struct dw_hdmi_qp *hdmi, void *data, ++ bool force, bool disabled, bool rxsense); ++ void (*setup_hpd)(struct dw_hdmi_qp *hdmi, void *data); ++ void (*set_mode)(struct dw_hdmi_qp *dw_hdmi, void *data, ++ u32 mode_mask, bool enable); ++}; ++ ++struct dw_hdmi_property_ops { ++ void (*attach_properties)(struct drm_connector *connector, ++ unsigned int color, int version, ++ void *data); ++ void (*destroy_properties)(struct drm_connector *connector, ++ void *data); ++ int (*set_property)(struct drm_connector *connector, ++ struct drm_connector_state *state, ++ struct drm_property *property, ++ u64 val, ++ void *data); ++ int (*get_property)(struct drm_connector *connector, ++ const struct drm_connector_state *state, ++ struct drm_property *property, ++ u64 *val, ++ void *data); ++}; ++ + struct dw_hdmi_plat_data { + struct regmap *regm; + ++ //[CC:] not in dowstream + unsigned int output_port; + ++ unsigned long input_bus_format; + unsigned long input_bus_encoding; ++ unsigned int max_tmdsclk; ++ int id; + bool use_drm_infoframe; + bool ycbcr_420_allowed; ++ bool unsupported_yuv_input; ++ bool unsupported_deep_color; ++ bool is_hdmi_qp; + + /* + * Private data passed to all the .mode_valid() and .configure_phy() +@@ -139,6 +195,7 @@ struct dw_hdmi_plat_data { + void *priv_data; + + /* Platform-specific mode validation (optional). */ ++ //[CC:] downstream changed "struct dw_hdmi *hdmi" to "struct drm_connector *connector" + enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data, + const struct drm_display_info *info, + const struct drm_display_mode *mode); +@@ -150,18 +207,50 @@ struct dw_hdmi_plat_data { + + /* Vendor PHY support */ + const struct dw_hdmi_phy_ops *phy_ops; ++ const struct dw_hdmi_qp_phy_ops *qp_phy_ops; + const char *phy_name; + void *phy_data; + unsigned int phy_force_vendor; + ++ /* split mode */ ++ bool split_mode; ++ bool first_screen; ++ struct dw_hdmi_qp *left; ++ struct dw_hdmi_qp *right; ++ + /* Synopsys PHY support */ + const struct dw_hdmi_mpll_config *mpll_cfg; ++ const struct dw_hdmi_mpll_config *mpll_cfg_420; + const struct dw_hdmi_curr_ctrl *cur_ctr; + const struct dw_hdmi_phy_config *phy_config; + int (*configure_phy)(struct dw_hdmi *hdmi, void *data, + unsigned long mpixelclock); + + unsigned int disable_cec : 1; ++ ++ //[CC:] 7b29b5f29585 ("drm/rockchip: dw_hdmi: Support HDMI 2.0 YCbCr 4:2:0") ++ unsigned long (*get_input_bus_format)(void *data); ++ unsigned long (*get_output_bus_format)(void *data); ++ unsigned long (*get_enc_in_encoding)(void *data); ++ unsigned long (*get_enc_out_encoding)(void *data); ++ ++ unsigned long (*get_quant_range)(void *data); ++ struct drm_property *(*get_hdr_property)(void *data); ++ struct drm_property_blob *(*get_hdr_blob)(void *data); ++ bool (*get_color_changed)(void *data); ++ int (*get_yuv422_format)(struct drm_connector *connector, ++ struct edid *edid); ++ int (*get_edid_dsc_info)(void *data, struct edid *edid); ++ int (*get_next_hdr_data)(void *data, struct edid *edid, ++ struct drm_connector *connector); ++ struct dw_hdmi_link_config *(*get_link_cfg)(void *data); ++ void (*set_grf_cfg)(void *data); ++ void (*convert_to_split_mode)(struct drm_display_mode *mode); ++ void (*convert_to_origin_mode)(struct drm_display_mode *mode); ++ ++ /* Vendor Property support */ ++ const struct dw_hdmi_property_ops *property_ops; ++ struct drm_connector *connector; + }; + + struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, +@@ -172,6 +261,7 @@ struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, + struct drm_encoder *encoder, + const struct dw_hdmi_plat_data *plat_data); + ++void dw_hdmi_suspend(struct dw_hdmi *hdmi); + void dw_hdmi_resume(struct dw_hdmi *hdmi); + + void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); +@@ -205,6 +295,17 @@ enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, + void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, + bool force, bool disabled, bool rxsense); + void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); ++void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi); ++void dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val); ++bool dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi); ++int dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi); ++ ++void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi); ++struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, ++ struct drm_encoder *encoder, ++ struct dw_hdmi_plat_data *plat_data); ++void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi); ++void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi); + + bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi); + +-- +Armbian + diff --git a/kernel.patches/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch b/kernel.patches/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch new file mode 100644 index 0000000..4c0ad9d --- /dev/null +++ b/kernel.patches/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch @@ -0,0 +1,25 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: ColorfulRhino +Date: Wed, 12 Jun 2024 12:17:18 +0200 +Subject: Fix HDMI controller patch at + drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c + +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +@@ -5,6 +5,7 @@ + * Algea Cao + */ + #include ++#include + #include + #include + #include +-- +Armbian + diff --git a/kernel.patches/0170-drm-rockchip-vop2-add-clocks-reset-support.patch b/kernel.patches/0170-drm-rockchip-vop2-add-clocks-reset-support.patch new file mode 100644 index 0000000..68ee38e --- /dev/null +++ b/kernel.patches/0170-drm-rockchip-vop2-add-clocks-reset-support.patch @@ -0,0 +1,190 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Fri, 3 May 2024 14:27:39 -0400 +Subject: vop2: Add clock resets support + +At the end of initialization, each VP clock needs to be reset before +they can be used. + +Failing to do so can put the VOP in an undefined state where the +generated HDMI signal is either lost or not matching the selected mode. + +Signed-off-by: Detlev Casanova +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 30 ++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +index 111111111111..222222222222 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -159,6 +160,7 @@ struct vop2_win { + struct vop2_video_port { + struct drm_crtc crtc; + struct vop2 *vop2; ++ struct reset_control *dclk_rst; + struct clk *dclk; + unsigned int id; + const struct vop2_video_port_data *data; +@@ -2064,6 +2066,26 @@ static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name) + return NULL; + } + ++static int vop2_clk_reset(struct vop2_video_port *vp) ++{ ++ struct reset_control *rstc = vp->dclk_rst; ++ struct vop2 *vop2 = vp->vop2; ++ int ret; ++ ++ if (!rstc) ++ return 0; ++ ++ ret = reset_control_assert(rstc); ++ if (ret < 0) ++ drm_warn(vop2->drm, "failed to assert reset\n"); ++ udelay(10); ++ ret = reset_control_deassert(rstc); ++ if (ret < 0) ++ drm_warn(vop2->drm, "failed to deassert reset\n"); ++ ++ return ret; ++} ++ + static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_state *state) + { +@@ -2233,6 +2255,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, + + vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); + ++ vop2_clk_reset(vp); ++ + drm_crtc_vblank_on(crtc); + + vop2_unlock(vop2); +@@ -2920,6 +2944,12 @@ static int vop2_create_crtcs(struct vop2 *vop2) + vp->data = vp_data; + + snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); ++ vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, dclk_name); ++ if (IS_ERR(vp->dclk_rst)) { ++ drm_err(vop2->drm, "failed to get %s reset\n", dclk_name); ++ return PTR_ERR(vp->dclk_rst); ++ } ++ + vp->dclk = devm_clk_get(vop2->dev, dclk_name); + if (IS_ERR(vp->dclk)) { + drm_err(vop2->drm, "failed to get %s\n", dclk_name); +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Fri, 3 May 2024 14:28:12 -0400 +Subject: arm64: dts: rockchip: Add VOP clock resets for rk3588s + +This adds the needed clock resets for all rk3588(s) based SOCs. + +Signed-off-by: Detlev Casanova +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1429,6 +1429,14 @@ vop: vop@fdd90000 { + "pclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; ++ resets = <&cru SRST_D_VOP0>, ++ <&cru SRST_D_VOP1>, ++ <&cru SRST_D_VOP2>, ++ <&cru SRST_D_VOP3>; ++ reset-names = "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3"; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Mon, 6 May 2024 13:54:01 -0400 +Subject: dt-bindings: display: vop2: Add VP clock resets + +Add the documentation for VOP2 video ports reset clocks. +One reset can be set per video port. + +Signed-off-by: Detlev Casanova +--- + Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 27 ++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +index 111111111111..222222222222 100644 +--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml ++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +@@ -65,6 +65,22 @@ properties: + - const: dclk_vp3 + - const: pclk_vop + ++ resets: ++ minItems: 3 ++ items: ++ - description: Pixel clock reset for video port 0. ++ - description: Pixel clock reset for video port 1. ++ - description: Pixel clock reset for video port 2. ++ - description: Pixel clock reset for video port 3. ++ ++ reset-names: ++ minItems: 3 ++ items: ++ - const: dclk_vp0 ++ - const: dclk_vp1 ++ - const: dclk_vp2 ++ - const: dclk_vp3 ++ + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: +@@ -128,6 +144,11 @@ allOf: + clock-names: + minItems: 7 + ++ resets: ++ minItems: 4 ++ reset-names: ++ minItems: 4 ++ + ports: + required: + - port@0 +@@ -183,6 +204,12 @@ examples: + "dclk_vp0", + "dclk_vp1", + "dclk_vp2"; ++ resets = <&cru SRST_VOP0>, ++ <&cru SRST_VOP1>, ++ <&cru SRST_VOP2>; ++ reset-names = "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2"; + power-domains = <&power RK3568_PD_VO>; + iommus = <&vop_mmu>; + vop_out: ports { +-- +Armbian + diff --git a/kernel.patches/0801-wireless-add-bcm43752.patch b/kernel.patches/0801-wireless-add-bcm43752.patch new file mode 100644 index 0000000..0085fdf --- /dev/null +++ b/kernel.patches/0801-wireless-add-bcm43752.patch @@ -0,0 +1,74 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Wed, 28 Feb 2024 20:59:15 +0100 +Subject: net: wireless: brcmfmac: Add support for AP6275P + +This module features BCM43752A2 chipset. The firmware requires +randomness seeding, so enabled it. + +Signed-off-by: Ondrej Jirman +--- + drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c | 5 ++++- + drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 2 ++ + 2 files changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c +index 111111111111..222222222222 100644 +--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c +@@ -70,6 +70,7 @@ BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie"); + BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie"); + BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie"); + BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie"); ++BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-pcie"); + + /* firmware config files */ + MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt"); +@@ -104,6 +105,7 @@ static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { + BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C), + BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C), + BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), ++ BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752), + BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */ + BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */ + BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */ +@@ -1720,7 +1722,7 @@ static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, + memcpy_toio(devinfo->tcm + address, nvram, nvram_len); + brcmf_fw_nvram_free(nvram); + +- if (devinfo->otp.valid) { ++ if (devinfo->otp.valid || devinfo->ci->chip == BRCM_CC_43752_CHIP_ID) { + size_t rand_len = BRCMF_RANDOM_SEED_LENGTH; + struct brcmf_random_seed_footer footer = { + .length = cpu_to_le32(rand_len), +@@ -2700,6 +2702,7 @@ static const struct pci_device_id brcmf_pcie_devid_table[] = { + BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA), + BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC), + BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW), ++ BRCMF_PCIE_DEVICE(BRCM_PCIE_43752_DEVICE_ID, WCC), + BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC), + BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC), + BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC), +diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h +index 111111111111..222222222222 100644 +--- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h ++++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h +@@ -52,6 +52,7 @@ + #define BRCM_CC_43664_CHIP_ID 43664 + #define BRCM_CC_43666_CHIP_ID 43666 + #define BRCM_CC_4371_CHIP_ID 0x4371 ++#define BRCM_CC_43752_CHIP_ID 43752 + #define BRCM_CC_4377_CHIP_ID 0x4377 + #define BRCM_CC_4378_CHIP_ID 0x4378 + #define BRCM_CC_4387_CHIP_ID 0x4387 +@@ -94,6 +95,7 @@ + #define BRCM_PCIE_4366_5G_DEVICE_ID 0x43c5 + #define BRCM_PCIE_4371_DEVICE_ID 0x440d + #define BRCM_PCIE_43596_DEVICE_ID 0x4415 ++#define BRCM_PCIE_43752_DEVICE_ID 0x449d + #define BRCM_PCIE_4377_DEVICE_ID 0x4488 + #define BRCM_PCIE_4378_DEVICE_ID 0x4425 + #define BRCM_PCIE_4387_DEVICE_ID 0x4433 +-- +Armbian + diff --git a/kernel.patches/0802-wireless-add-clk-property.patch b/kernel.patches/0802-wireless-add-clk-property.patch new file mode 100644 index 0000000..193f989 --- /dev/null +++ b/kernel.patches/0802-wireless-add-clk-property.patch @@ -0,0 +1,51 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Wed, 28 Feb 2024 21:09:51 +0100 +Subject: net: wireless: brcmfmac: Add optional 32k clock enable support + +WiFi modules often require 32kHz clock to function. Add support to +enable the clock to pcie driver. + +Signed-off-by: Ondrej Jirman +--- + drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c +index 111111111111..222222222222 100644 +--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c +@@ -3,6 +3,7 @@ + * Copyright (c) 2014 Broadcom Corporation + */ + ++#include + #include + #include + #include +@@ -2413,6 +2414,7 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) + struct brcmf_pciedev *pcie_bus_dev; + struct brcmf_core *core; + struct brcmf_bus *bus; ++ struct clk *clk; + + if (!id) { + id = pci_match_id(brcmf_pcie_devid_table, pdev); +@@ -2424,6 +2426,14 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) + + brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device); + ++ clk = devm_clk_get_optional_enabled(&pdev->dev, "32k"); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ if (clk) { ++ dev_info(&pdev->dev, "enabling 32kHz clock\n"); ++ clk_set_rate(clk, 32768); ++ } ++ + ret = -ENOMEM; + devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); + if (devinfo == NULL) +-- +Armbian + diff --git a/kernel.patches/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch b/kernel.patches/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch new file mode 100644 index 0000000..326476f --- /dev/null +++ b/kernel.patches/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch @@ -0,0 +1,37 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: amazingfate +Date: Wed, 27 Dec 2023 15:03:57 +0800 +Subject: arm64: dts: rock-5b: Slow down emmc to hs200 and add tsadc node + +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -371,8 +371,7 @@ &sdhci { + no-sdio; + no-sd; + non-removable; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; ++ mmc-hs200-1_8v; + status = "okay"; + }; + +@@ -412,6 +411,10 @@ &sdio { + status = "okay"; + }; + ++&tsadc { ++ status = "okay"; ++}; ++ + &uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; +-- +Armbian + diff --git a/kernel.patches/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch b/kernel.patches/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch new file mode 100644 index 0000000..bcf1f94 --- /dev/null +++ b/kernel.patches/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch @@ -0,0 +1,52 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: lanefu +Date: Sat, 20 Jan 2024 17:16:20 +0000 +Subject: rock-5b enable SPI flash in device tree + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts + +Signed-off-by: lanefu +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 27 ++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -421,6 +421,33 @@ &uart6 { + status = "okay"; + }; + ++&sfc { ++ status = "okay"; ++ ++ spi_flash: spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-max-frequency = <50000000>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <4>; ++ status = "okay"; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ loader@0 { ++ label = "loader"; ++ reg = <0x0 0x1000000>; ++ }; ++ }; ++ }; ++ ++}; ++ + &spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; +-- +Armbian + diff --git a/kernel.patches/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch b/kernel.patches/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch new file mode 100644 index 0000000..618d12d --- /dev/null +++ b/kernel.patches/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch @@ -0,0 +1,67 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Mon, 15 Jan 2024 22:51:17 +0200 +Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5b + +Add the necessary DT changes to enable HDMI0 on Rock 5B. + +Signed-off-by: Cristian Ciocaltea +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 ++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -185,6 +186,20 @@ &gpu { + status = "okay"; + }; + ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +@@ -837,3 +852,18 @@ &usb_host1_xhci { + &usb_host2_xhci { + status = "okay"; + }; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; +-- +Armbian + diff --git a/kernel.patches/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch b/kernel.patches/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch new file mode 100644 index 0000000..3361d14 --- /dev/null +++ b/kernel.patches/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch @@ -0,0 +1,41 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Fri, 3 Nov 2023 20:05:05 +0200 +Subject: arm64: dts: rockchip: Make use of HDMI0 PHY PLL on rock-5b + +The initial vop2 support for rk3588 in mainline is not able to handle +all display modes supported by connected displays, e.g. +2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. + +Additionally, it doesn't cope with non-integer refresh rates like 59.94, +29.97, 23.98, etc. + +Make use of the HDMI0 PHY PLL to support the additional display modes. + +Note this requires commit "drm/rockchip: vop2: Improve display modes +handling on rk3588", which needs a rework to be upstreamable. + +Signed-off-by: Cristian Ciocaltea +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -186,6 +186,11 @@ &gpu { + status = "okay"; + }; + ++&display_subsystem { ++ clocks = <&hdptxphy_hdmi0>; ++ clock-names = "hdmi0_phy_pll"; ++}; ++ + &hdmi0 { + status = "okay"; + }; +-- +Armbian + diff --git a/kernel.patches/1015-board-rock5b-automatic-fan-control.patch b/kernel.patches/1015-board-rock5b-automatic-fan-control.patch new file mode 100644 index 0000000..9947550 --- /dev/null +++ b/kernel.patches/1015-board-rock5b-automatic-fan-control.patch @@ -0,0 +1,68 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alexey Charkov +Date: Mon, 6 May 2024 13:36:35 +0400 +Subject: arm64: dts: rockchip: enable automatic fan control on Rock 5B + +This links the PWM fan on Radxa Rock 5B as an active cooling device +managed automatically by the thermal subsystem, with a target SoC +temperature of 65C and a minimum-spin interval from 55C to 65C to +ensure airflow when the system gets warm + +Helped-by: Dragan Simic +Reviewed-by: Dragan Simic +Signed-off-by: Alexey Charkov +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 +++++++++- + 1 file changed, 29 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -53,7 +53,7 @@ led_rgb_b { + + fan: pwm-fan { + compatible = "pwm-fan"; +- cooling-levels = <0 95 145 195 255>; ++ cooling-levels = <0 120 150 180 210 240 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; +@@ -299,6 +299,34 @@ i2s0_8ch_p0_0: endpoint { + }; + }; + ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map1 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ map2 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; +-- +Armbian + diff --git a/kernel.patches/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch b/kernel.patches/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch new file mode 100644 index 0000000..e26dc7a --- /dev/null +++ b/kernel.patches/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch @@ -0,0 +1,57 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Tue, 27 Feb 2024 16:04:42 +0300 +Subject: Add HDMI and VOP2 to Rock 5A + +--- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 30 ++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -5,6 +5,7 @@ + #include + #include + #include ++#include + #include "rk3588s.dtsi" + + / { +@@ -765,3 +766,32 @@ &usb_host1_ohci { + &usb_host2_xhci { + status = "okay"; + }; ++ ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; +-- +Armbian + diff --git a/kernel.patches/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch b/kernel.patches/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch new file mode 100644 index 0000000..da231f6 --- /dev/null +++ b/kernel.patches/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch @@ -0,0 +1,36 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: amazingfate +Date: Thu, 28 Mar 2024 00:41:34 +0800 +Subject: arch: arm64: dts: enable gpu node for rock-5a + +--- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -281,6 +281,11 @@ &gmac1_rgmii_clk + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ + &mdio1 { + rgmii_phy1: ethernet-phy@1 { + /* RTL8211F */ +@@ -434,6 +439,7 @@ rk806_dvs3_null: dvs3-null-pins { + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; ++ regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; +-- +Armbian + diff --git a/kernel.patches/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch b/kernel.patches/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch new file mode 100644 index 0000000..32653f4 --- /dev/null +++ b/kernel.patches/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch @@ -0,0 +1,265 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Thu, 16 Nov 2023 18:15:09 +0300 +Subject: arm64: dts: Add missing nodes to Orange Pi 5 Plus + +--- + arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 182 +++++++++- + 1 file changed, 181 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -158,6 +159,20 @@ daicodec: simple-audio-card,codec { + }; + }; + ++ wlan-rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ bluetooth-rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-bluetooth"; ++ radio-type = "bluetooth"; ++ shutdown-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ }; ++ + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; +@@ -199,6 +214,18 @@ vcc5v0_sys: vcc5v0-sys-regulator { + regulator-max-microvolt = <5000000>; + }; + ++ vbus5v0_typec: vbus5v0-typec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vbus5v0_typec"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec5v_pwren>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ + vcc5v0_usb20: vcc5v0-usb20-regulator { + compatible = "regulator-fixed"; + enable-active-high; +@@ -311,6 +338,53 @@ hym8563: rtc@51 { + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; ++ ++ usbc0: usb-typec@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc0_int>; ++ vbus-supply = <&vbus5v0_typec>; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ data-role = "dual"; ++ power-role = "dual"; ++ try-power-role = "source"; ++ op-sink-microwatt = <1000000>; ++ sink-pdos = ; ++ source-pdos = ; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usbc0_hs: endpoint { ++ remote-endpoint = <&usb_host0_xhci_drd_sw>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ usbc0_ss: endpoint { ++ remote-endpoint = <&usbdp_phy0_typec_ss>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ usbc0_sbu: endpoint { ++ remote-endpoint = <&usbdp_phy0_typec_sbu>; ++ }; ++ }; ++ }; ++ }; ++ }; + }; + + &i2c7 { +@@ -385,7 +459,7 @@ &pcie3x4 { + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +@@ -408,6 +482,14 @@ hp_detect: hp-detect { + }; + + usb { ++ typec5v_pwren: typec5v-pwren { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ usbc0_int: usbc0-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ + vcc5v0_usb20_en: vcc5v0-usb20-en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; +@@ -803,6 +885,22 @@ &tsadc { + status = "okay"; + }; + ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +@@ -831,6 +929,35 @@ &uart9 { + status = "okay"; + }; + ++&usbdp_phy0 { ++ orientation-switch; ++ mode-switch; ++ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; ++ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ svid = <0xff01>; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy0_typec_ss: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_ss>; ++ }; ++ ++ usbdp_phy0_typec_sbu: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&usbc0_sbu>; ++ }; ++ }; ++}; ++ ++&usbdp_phy1 { ++ rockchip,dp-lane-mux = <2 3>; ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + }; +@@ -839,6 +966,20 @@ &usb_host0_ohci { + status = "okay"; + }; + ++&usb_host0_xhci { ++ dr_mode = "otg"; ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ usb_host0_xhci_drd_sw: endpoint { ++ remote-endpoint = <&usbc0_hs>; ++ }; ++ }; ++}; ++ + &usb_host1_ehci { + status = "okay"; + }; +@@ -846,3 +987,42 @@ &usb_host1_ehci { + &usb_host1_ohci { + status = "okay"; + }; ++ ++&usb_host1_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; +-- +Armbian + diff --git a/kernel.patches/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch b/kernel.patches/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch new file mode 100644 index 0000000..bd33b59 --- /dev/null +++ b/kernel.patches/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch @@ -0,0 +1,39 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: amazingfate +Date: Thu, 28 Mar 2024 16:07:18 +0800 +Subject: arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5a + +--- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -115,6 +115,10 @@ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + }; + }; + ++&combphy0_ps { ++ status = "okay"; ++}; ++ + &combphy2_psu { + status = "okay"; + }; +@@ -299,6 +303,11 @@ rgmii_phy1: ethernet-phy@1 { + }; + }; + ++&pcie2x1l2 { ++ status = "okay"; ++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; ++}; ++ + &pinctrl { + leds { + io_led: io-led { +-- +Armbian + diff --git a/kernel.patches/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch b/kernel.patches/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch new file mode 100644 index 0000000..8ee1725 --- /dev/null +++ b/kernel.patches/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch @@ -0,0 +1,64 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jianfeng Liu +Date: Thu, 6 Jun 2024 23:28:01 +0800 +Subject: arm64: dts: rockchip: Add HDMI support to ArmSoM Sige7 + +--- + arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 30 ++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -164,6 +165,20 @@ &gpu { + status = "okay"; + }; + ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +@@ -723,3 +738,18 @@ &usb_host1_xhci { + dr_mode = "host"; + status = "okay"; + }; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; +-- +Armbian + diff --git a/kernel.patches/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch b/kernel.patches/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch new file mode 100644 index 0000000..a577074 --- /dev/null +++ b/kernel.patches/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch @@ -0,0 +1,39 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jianfeng Liu +Date: Thu, 6 Jun 2024 23:29:39 +0800 +Subject: arm64: dts: rockchip: Add ap6275p wireless support to ArmSoM Sige7 + +--- + arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 16 ++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +@@ -283,6 +283,22 @@ &pcie2x1l0 { + &pcie2x1l1 { + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; ++ ++ pcie@0,0 { ++ reg = <0x300000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ device_type = "pci"; ++ bus-range = <0x30 0x3f>; ++ ++ wifi: wifi@0,0 { ++ compatible = "pci14e4,449d"; ++ reg = <0x310000 0 0 0 0>; ++ clocks = <&hym8563>; ++ clock-names = "32k"; ++ }; ++ }; + }; + + /* phy0 - left ethernet port */ +-- +Armbian + diff --git a/kernel.patches/1040-board-khadas-edge2-add-nodes.patch b/kernel.patches/1040-board-khadas-edge2-add-nodes.patch new file mode 100644 index 0000000..1cd96d1 --- /dev/null +++ b/kernel.patches/1040-board-khadas-edge2-add-nodes.patch @@ -0,0 +1,325 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Mon, 12 Feb 2024 17:35:13 +0300 +Subject: arm64: dts: rockchip: Add USB-C to Khadas Edge 2 + +Khadas Edge 2 has 2x Type-C port. One just supports PD and +controlled by MCU. The other one supports PD, DP Alt mode and DRD. This +commit adds support for DRD. + +Signed-off-by: Muhammed Efe Cetin +--- + arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 120 ++++++++++ + 1 file changed, 120 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +@@ -6,6 +6,7 @@ + #include + #include + #include ++#include + #include "rk3588s.dtsi" + + / { +@@ -76,6 +77,18 @@ blue_led: led-2 { + }; + }; + ++ vbus5v0_typec: vbus5v0-typec-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vbus5v0_typec"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ vin-supply = <&vcc5v0_sys>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec5v_pwren>; ++ }; ++ + vcc3v3_pcie_wl: vcc3v3-pcie-wl-regulator { + compatible = "regulator-fixed"; + enable-active-high; +@@ -224,6 +237,56 @@ regulator-state-mem { + &i2c2 { + status = "okay"; + ++ usbc0: usb-typec@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc0_int>; ++ vbus-supply = <&vbus5v0_typec>; ++ status = "okay"; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ data-role = "dual"; ++ power-role = "dual"; ++ try-power-role = "source"; ++ op-sink-microwatt = <1000000>; ++ sink-pdos = ; ++ source-pdos = ; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usbc0_orien_sw: endpoint { ++ remote-endpoint = <&usbdp_phy0_orientation_switch>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ usbc0_role_sw: endpoint { ++ remote-endpoint = <&dwc3_0_role_switch>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ dp_altmode_mux: endpoint { ++ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; +@@ -256,6 +319,16 @@ vcc5v0_host_en: vcc5v0-host-en { + }; + }; + ++ usb-typec { ++ usbc0_int: usbc0-int { ++ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ typec5v_pwren: typec5v-pwren { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; +@@ -681,6 +754,15 @@ &uart9 { + status = "okay"; + }; + ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++ + &u2phy2 { + status = "okay"; + }; +@@ -707,6 +789,44 @@ &usb_host0_ohci { + status = "okay"; + }; + ++&usbdp_phy0 { ++ orientation-switch; ++ mode-switch; ++ svid = <0xff01>; ++ sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; ++ sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy0_orientation_switch: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_orien_sw>; ++ }; ++ ++ usbdp_phy0_dp_altmode_mux: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dp_altmode_mux>; ++ }; ++ }; ++}; ++ ++&usb_host0_xhci { ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dwc3_0_role_switch: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_role_sw>; ++ }; ++ }; ++}; ++ + &usb_host1_ehci { + status = "okay"; + }; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Mon, 12 Feb 2024 17:35:13 +0300 +Subject: arm64: dts: rockchip: Add bluetooth rfkill to Khadas Edge 2 + +--- + arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +@@ -116,6 +116,15 @@ vcc5v0_host: vcc5v0-host-regulator { + vin-supply = <&vcc5v0_sys>; + }; + ++ bluetooth-rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-bluetooth"; ++ radio-type = "bluetooth"; ++ shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_reset_pin>; ++ }; ++ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Mon, 19 Feb 2024 23:32:11 +0300 +Subject: arm64: dts: rockchip: Add HDMI & VOP2 to Khadas Edge 2 + +--- + arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 36 ++++++++++ + 1 file changed, 36 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + #include "rk3588s.dtsi" + + / { +@@ -823,6 +824,7 @@ usbdp_phy0_dp_altmode_mux: endpoint@1 { + }; + + &usb_host0_xhci { ++ dr-mode = "otg"; + usb-role-switch; + status = "okay"; + +@@ -847,3 +849,37 @@ &usb_host1_ohci { + &usb_host2_xhci { + status = "okay"; + }; ++ ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdptxphy_hdmi0 { ++ status = "okay"; ++}; ++ ++&display_subsystem { ++ clocks = <&hdptxphy_hdmi0>; ++ clock-names = "hdmi0_phy_pll"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Sat, 2 Mar 2024 19:13:59 +0300 +Subject: arm64: dts: rockchip: Add AP6275P wireless support to Khadas Edge 2 + +--- + arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 17 ++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +@@ -366,6 +366,23 @@ &pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_wl>; + status = "okay"; ++ ++ pcie@0,0 { ++ reg = <0x400000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ device_type = "pci"; ++ bus-range = <0x40 0x4f>; ++ ++ wifi: wifi@0,0 { ++ compatible = "pci14e4,449d"; ++ reg = <0x410000 0 0 0 0>; ++ clocks = <&hym8563>; ++ clock-names = "32k"; ++ }; ++ }; ++ + }; + + &pwm11 { +-- +Armbian + diff --git a/kernel.patches/1041-board-khadas-edge2-mcu.patch b/kernel.patches/1041-board-khadas-edge2-mcu.patch new file mode 100644 index 0000000..985f0b3 --- /dev/null +++ b/kernel.patches/1041-board-khadas-edge2-mcu.patch @@ -0,0 +1,441 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Wed, 6 Mar 2024 00:09:25 +0300 +Subject: mfd: khadas-mcu: add Edge2 registers + +--- + drivers/mfd/khadas-mcu.c | 8 +++- + include/linux/mfd/khadas-mcu.h | 24 ++++++++++ + 2 files changed, 30 insertions(+), 2 deletions(-) + +diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c +index 111111111111..222222222222 100644 +--- a/drivers/mfd/khadas-mcu.c ++++ b/drivers/mfd/khadas-mcu.c +@@ -26,6 +26,10 @@ static bool khadas_mcu_reg_volatile(struct device *dev, unsigned int reg) + case KHADAS_MCU_CHECK_USER_PASSWD_REG: + case KHADAS_MCU_WOL_INIT_START_REG: + case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG: ++ case KHADAS_MCU_LED_ON_RAM_REG: ++ case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2: ++ case KHADAS_MCU_WDT_EN_REG: ++ case KHADAS_MCU_SYS_RST_REG: + return true; + default: + return false; +@@ -69,14 +73,14 @@ static const struct regmap_config khadas_mcu_regmap_config = { + .reg_bits = 8, + .reg_stride = 1, + .val_bits = 8, +- .max_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG, ++ .max_register = KHADAS_MCU_SYS_RST_REG, + .volatile_reg = khadas_mcu_reg_volatile, + .writeable_reg = khadas_mcu_reg_writeable, + .cache_type = REGCACHE_MAPLE, + }; + + static struct mfd_cell khadas_mcu_fan_cells[] = { +- /* VIM1/2 Rev13+ and VIM3 only */ ++ /* VIM1/2 Rev13+, VIM3 and Edge2 only */ + { .name = "khadas-mcu-fan-ctrl", }, + }; + +diff --git a/include/linux/mfd/khadas-mcu.h b/include/linux/mfd/khadas-mcu.h +index 111111111111..222222222222 100644 +--- a/include/linux/mfd/khadas-mcu.h ++++ b/include/linux/mfd/khadas-mcu.h +@@ -35,26 +35,45 @@ + #define KHADAS_MCU_FACTORY_TEST_REG 0x16 /* R */ + #define KHADAS_MCU_BOOT_MODE_REG 0x20 /* RW */ + #define KHADAS_MCU_BOOT_EN_WOL_REG 0x21 /* RW */ ++#define KHADAS_MCU_BOOT_EN_DCIN_REG_V2 0x21 /* RW */ + #define KHADAS_MCU_BOOT_EN_RTC_REG 0x22 /* RW */ + #define KHADAS_MCU_BOOT_EN_EXP_REG 0x23 /* RW */ ++#define KHADAS_MCU_LED_MODE_ON_REG_V2 0x23 /* RW */ ++#define KHADAS_MCU_LED_MODE_OFF_REG_V2 0x24 /* RW */ + #define KHADAS_MCU_BOOT_EN_IR_REG 0x24 /* RW */ + #define KHADAS_MCU_BOOT_EN_DCIN_REG 0x25 /* RW */ ++#define KHADAS_MCU_RGB_ON_R_REG 0x25 /* RW */ ++#define KHADAS_MCU_RGB_ON_G_REG 0x26 /* RW */ + #define KHADAS_MCU_BOOT_EN_KEY_REG 0x26 /* RW */ ++#define KHADAS_MCU_RGB_ON_B_REG 0x27 /* RW */ + #define KHADAS_MCU_KEY_MODE_REG 0x27 /* RW */ ++#define KHADAS_MCU_RGB_OFF_R_REG 0x28 /* RW */ + #define KHADAS_MCU_LED_MODE_ON_REG 0x28 /* RW */ ++#define KHADAS_MCU_RGB_OFF_G_REG 0x29 /* RW */ + #define KHADAS_MCU_LED_MODE_OFF_REG 0x29 /* RW */ ++#define KHADAS_MCU_RGB_OFF_B_REG 0x2a /* RW */ + #define KHADAS_MCU_SHUTDOWN_NORMAL_REG 0x2c /* RW */ + #define KHADAS_MCU_MAC_SWITCH_REG 0x2d /* RW */ ++#define KHADAS_MCU_REST_CONF_REG 0x2e /* RW */ + #define KHADAS_MCU_MCU_SLEEP_MODE_REG 0x2e /* RW */ ++#define KHADAS_MCU_BOOT_EN_IR_REG_V2 0x2f /* RW */ + #define KHADAS_MCU_IR_CODE1_0_REG 0x2f /* RW */ + #define KHADAS_MCU_IR_CODE1_1_REG 0x30 /* RW */ ++#define KHADAS_MCU_IR1_CUST1_REG 0x30 /* RW */ + #define KHADAS_MCU_IR_CODE1_2_REG 0x31 /* RW */ ++#define KHADAS_MCU_IR1_CUST2_REG 0x31 /* RW */ + #define KHADAS_MCU_IR_CODE1_3_REG 0x32 /* RW */ ++#define KHADAS_MCU_IR1_ORDER1_REG 0x32 /* RW */ + #define KHADAS_MCU_USB_PCIE_SWITCH_REG 0x33 /* RW */ ++#define KHADAS_MCU_IR1_ORDER2_REG 0x33 /* RW */ ++#define KHADAS_MCU_IR2_CUST1_REG 0x34 /* RW */ + #define KHADAS_MCU_IR_CODE2_0_REG 0x34 /* RW */ + #define KHADAS_MCU_IR_CODE2_1_REG 0x35 /* RW */ ++#define KHADAS_MCU_IR2_CUST2_REG 0x35 /* RW */ + #define KHADAS_MCU_IR_CODE2_2_REG 0x36 /* RW */ ++#define KHADAS_MCU_IR2_ORDER1_REG 0x36 /* RW */ + #define KHADAS_MCU_IR_CODE2_3_REG 0x37 /* RW */ ++#define KHADAS_MCU_IR2_ORDER2_REG 0x36 /* RW */ + #define KHADAS_MCU_PASSWD_USER_0_REG 0x40 /* RW */ + #define KHADAS_MCU_PASSWD_USER_1_REG 0x41 /* RW */ + #define KHADAS_MCU_PASSWD_USER_2_REG 0x42 /* RW */ +@@ -69,6 +88,10 @@ + #define KHADAS_MCU_SHUTDOWN_NORMAL_STATUS_REG 0x86 /* RO */ + #define KHADAS_MCU_WOL_INIT_START_REG 0x87 /* WO */ + #define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG 0x88 /* WO */ ++#define KHADAS_MCU_LED_ON_RAM_REG 0x89 /* WO */ ++#define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2 0x8A /* WO */ ++#define KHADAS_MCU_WDT_EN_REG 0x8B /* WO */ ++#define KHADAS_MCU_SYS_RST_REG 0x91 /* WO */ + + enum { + KHADAS_BOARD_VIM1 = 0x1, +@@ -76,6 +99,7 @@ enum { + KHADAS_BOARD_VIM3, + KHADAS_BOARD_EDGE = 0x11, + KHADAS_BOARD_EDGE_V, ++ KHADAS_BOARD_EDGE2, + }; + + /** +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Wed, 6 Mar 2024 00:09:58 +0300 +Subject: mfd: khadas-mcu: drop unused code + +--- + drivers/mfd/khadas-mcu.c | 11 ---------- + 1 file changed, 11 deletions(-) + +diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c +index 111111111111..222222222222 100644 +--- a/drivers/mfd/khadas-mcu.c ++++ b/drivers/mfd/khadas-mcu.c +@@ -84,10 +84,6 @@ static struct mfd_cell khadas_mcu_fan_cells[] = { + { .name = "khadas-mcu-fan-ctrl", }, + }; + +-static struct mfd_cell khadas_mcu_cells[] = { +- { .name = "khadas-mcu-user-mem", }, +-}; +- + static int khadas_mcu_probe(struct i2c_client *client) + { + struct device *dev = &client->dev; +@@ -109,13 +105,6 @@ static int khadas_mcu_probe(struct i2c_client *client) + return ret; + } + +- ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, +- khadas_mcu_cells, +- ARRAY_SIZE(khadas_mcu_cells), +- NULL, 0, NULL); +- if (ret) +- return ret; +- + if (of_property_present(dev->of_node, "#cooling-cells")) + return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, + khadas_mcu_fan_cells, +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Wed, 6 Mar 2024 00:13:10 +0300 +Subject: thermal: khadas_mcu_fan: add support for Khadas Edge 2 + +--- + drivers/thermal/khadas_mcu_fan.c | 77 +++++++++- + 1 file changed, 73 insertions(+), 4 deletions(-) + +diff --git a/drivers/thermal/khadas_mcu_fan.c b/drivers/thermal/khadas_mcu_fan.c +index 111111111111..222222222222 100644 +--- a/drivers/thermal/khadas_mcu_fan.c ++++ b/drivers/thermal/khadas_mcu_fan.c +@@ -15,10 +15,16 @@ + #include + + #define MAX_LEVEL 3 ++#define MAX_SPEED 0x64 + + struct khadas_mcu_fan_ctx { + struct khadas_mcu *mcu; + unsigned int level; ++ ++ unsigned int fan_max_level; ++ unsigned int fan_register; ++ unsigned int *fan_cooling_levels; ++ + struct thermal_cooling_device *cdev; + }; + +@@ -26,9 +32,21 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx, + unsigned int level) + { + int ret; ++ unsigned int write_level = level; ++ ++ if (level > ctx->fan_max_level) ++ return -EINVAL; ++ ++ if (ctx->fan_cooling_levels != NULL) { ++ write_level = ctx->fan_cooling_levels[level]; ++ ++ if (write_level > MAX_SPEED) ++ return -EINVAL; ++ } ++ ++ ret = regmap_write(ctx->mcu->regmap, ctx->fan_register, ++ write_level); + +- ret = regmap_write(ctx->mcu->regmap, KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG, +- level); + if (ret) + return ret; + +@@ -40,7 +58,9 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx, + static int khadas_mcu_fan_get_max_state(struct thermal_cooling_device *cdev, + unsigned long *state) + { +- *state = MAX_LEVEL; ++ struct khadas_mcu_fan_ctx *ctx = cdev->devdata; ++ ++ *state = ctx->fan_max_level; + + return 0; + } +@@ -61,7 +81,7 @@ khadas_mcu_fan_set_cur_state(struct thermal_cooling_device *cdev, + { + struct khadas_mcu_fan_ctx *ctx = cdev->devdata; + +- if (state > MAX_LEVEL) ++ if (state > ctx->fan_max_level) + return -EINVAL; + + if (state == ctx->level) +@@ -76,6 +96,48 @@ static const struct thermal_cooling_device_ops khadas_mcu_fan_cooling_ops = { + .set_cur_state = khadas_mcu_fan_set_cur_state, + }; + ++// Khadas Edge 2 sets fan level by passing fan speed(0-100). So we need different logic here like pwm-fan cooling-levels. ++// This is optional and just necessary for Edge 2. ++static int khadas_mcu_fan_get_cooling_data_edge2(struct khadas_mcu_fan_ctx *ctx, struct device *dev) { ++ struct device_node *np = ctx->mcu->dev->of_node; ++ int num, i, ret; ++ ++ if (!of_property_present(np, "cooling-levels")) ++ return 0; ++ ++ ret = of_property_count_u32_elems(np, "cooling-levels"); ++ if (ret <= 0) { ++ dev_err(dev, "Wrong data!\n"); ++ return ret ? : -EINVAL; ++ } ++ ++ num = ret; ++ ctx->fan_cooling_levels = devm_kcalloc(dev, num, sizeof(u32), ++ GFP_KERNEL); ++ if (!ctx->fan_cooling_levels) ++ return -ENOMEM; ++ ++ ret = of_property_read_u32_array(np, "cooling-levels", ++ ctx->fan_cooling_levels, num); ++ if (ret) { ++ dev_err(dev, "Property 'cooling-levels' cannot be read!\n"); ++ return ret; ++ } ++ ++ for (i = 0; i < num; i++) { ++ if (ctx->fan_cooling_levels[i] > MAX_SPEED) { ++ dev_err(dev, "PWM fan state[%d]:%d > %d\n", i, ++ ctx->fan_cooling_levels[i], MAX_SPEED); ++ return -EINVAL; ++ } ++ } ++ ++ ctx->fan_max_level = num - 1; ++ ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2; ++ ++ return 0; ++} ++ + static int khadas_mcu_fan_probe(struct platform_device *pdev) + { + struct khadas_mcu *mcu = dev_get_drvdata(pdev->dev.parent); +@@ -90,6 +152,13 @@ static int khadas_mcu_fan_probe(struct platform_device *pdev) + ctx->mcu = mcu; + platform_set_drvdata(pdev, ctx); + ++ ctx->fan_max_level = MAX_LEVEL; ++ ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG; ++ ++ ret = khadas_mcu_fan_get_cooling_data_edge2(ctx, dev); ++ if (ret) ++ return ret; ++ + cdev = devm_thermal_of_cooling_device_register(dev->parent, + dev->parent->of_node, "khadas-mcu-fan", ctx, + &khadas_mcu_fan_cooling_ops); +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Wed, 6 Mar 2024 00:14:58 +0300 +Subject: dt-bindings: mfd: khadas-mcu: add cooling-levels property + +--- + Documentation/devicetree/bindings/mfd/khadas,mcu.yaml | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml +index 111111111111..222222222222 100644 +--- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml ++++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml +@@ -11,7 +11,7 @@ maintainers: + + description: | + Khadas embeds a microcontroller on their VIM and Edge boards adding some +- system feature as PWM Fan control (for VIM2 rev14 or VIM3), User memory ++ system feature as PWM Fan control (for VIM2 rev14, VIM3, Edge2), User memory + storage, IR/Key resume control, system power LED control and more. + + properties: +@@ -22,6 +22,11 @@ properties: + "#cooling-cells": # Only needed for boards having FAN control feature + const: 2 + ++ cooling-levels: ++ description: Max speed of PWM fan. This property is necessary for Khadas Edge 2. ++ items: ++ maximum: 100 ++ + reg: + maxItems: 1 + +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Wed, 6 Mar 2024 00:17:58 +0300 +Subject: arm64: dts: rockchip: Add MCU to Khadas Edge 2 + +--- + arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +@@ -304,6 +304,13 @@ hym8563: rtc@51 { + clock-output-names = "hym8563"; + wakeup-source; + }; ++ ++ khadas_mcu: system-controller@18 { ++ compatible = "khadas,mcu"; ++ reg = <0x18>; ++ cooling-levels = <0 50 72 100>; ++ #cooling-cells = <2>; ++ }; + }; + + &pinctrl { +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Mon, 25 Mar 2024 22:41:26 +0300 +Subject: arm64: dts: rockchip: Add automatic fan control to Khadas Edge 2 + +--- + arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 56 ++++++++++ + 1 file changed, 56 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +@@ -313,6 +313,62 @@ khadas_mcu: system-controller@18 { + }; + }; + ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <45000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <55000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ package_fan2: package-fan2 { ++ temperature = <60000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ package_fan3: package-fan3 { ++ temperature = <70000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&package_fan0>; ++ cooling-device = <&khadas_mcu 0 1>; ++ contribution = <1024>; ++ }; ++ ++ map1 { ++ trip = <&package_fan1>; ++ cooling-device = <&khadas_mcu 1 2>; ++ contribution = <1024>; ++ }; ++ ++ map2 { ++ trip = <&package_fan2>; ++ cooling-device = <&khadas_mcu 2 3>; ++ contribution = <1024>; ++ }; ++ ++ map3 { ++ trip = <&package_fan3>; ++ cooling-device = <&khadas_mcu 3 THERMAL_NO_LIMIT>; ++ contribution = <1024>; ++ }; ++ }; ++}; ++ + &pinctrl { + vdd_sd { + vdd_sd_en: vdd-sd-en { +-- +Armbian + diff --git a/kernel.patches/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch b/kernel.patches/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch new file mode 100644 index 0000000..6b842c0 --- /dev/null +++ b/kernel.patches/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch @@ -0,0 +1,38 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ricardo Pardini +Date: Thu, 6 Jun 2024 23:00:05 +0200 +Subject: arm64: dts: rockchip: Add NanoPC T6 SPI Flash + +Signed-off-by: Ricardo Pardini +--- + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 14 ++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts +@@ -576,6 +576,20 @@ &sdmmc { + status = "okay"; + }; + ++&sfc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fspim1_pins>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-max-frequency = <50000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ + &spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; +-- +Armbian + diff --git a/rk3328-rock64.dtb b/rk3328-rock64.dtb deleted file mode 100644 index e70c49b..0000000 Binary files a/rk3328-rock64.dtb and /dev/null differ diff --git a/rk3588-friendlyelec-cm3588-nas.dtb b/rk3588-friendlyelec-cm3588-nas.dtb new file mode 100644 index 0000000..d7952ec Binary files /dev/null and b/rk3588-friendlyelec-cm3588-nas.dtb differ diff --git a/u-boot-rockchip.bin b/u-boot-rockchip.bin index 4c26ab8..b06472a 100644 Binary files a/u-boot-rockchip.bin and b/u-boot-rockchip.bin differ diff --git a/boot.cmd b/uboot.patches/boot.cmd similarity index 94% rename from boot.cmd rename to uboot.patches/boot.cmd index 8b00af3..04693e4 100644 --- a/boot.cmd +++ b/uboot.patches/boot.cmd @@ -16,7 +16,7 @@ setexpr.s bootargs *${ramdisk_addr_r} echo "Boot args: ${bootargs}" # Load dtb -setenv fdtfile rk3328-rock64.dtb +setenv fdtfile rk3588-friendlyelec-cm3588-nas.dtb load ${devtype} ${devnum}:${bootpart} ${fdt_addr_r} ${fdtfile} # ... and set fdt addr to it. fdt addr ${fdt_addr_r} diff --git a/uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin b/uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin new file mode 100644 index 0000000..6aaaaa1 Binary files /dev/null and b/uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin differ diff --git a/vmlinuz b/vmlinuz index 64b9bd2..b90c3de 100644 Binary files a/vmlinuz and b/vmlinuz differ