From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Mon, 15 Jan 2024 22:47:41 +0200 Subject: arm64: dts: rockchip: Add HDMI0 bridge to rk3588 Add DT node for the HDMI0 bridge found on RK3588 SoC. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 55 ++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1516,6 +1516,61 @@ i2s9_8ch: i2s@fddfc000 { status = "disabled"; }; + hdmi0: hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x0 0xfde80000 0x0 0x20000>; + interrupts = , + , + , + , + ; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMIHDP0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_I2S5_8CH_TX>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru HCLK_VO1>; + clock-names = "pclk", + "hpd", + "earc", + "hdmitx_ref", + "aud", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "hclk_vo1"; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; + reset-names = "ref", "hdp"; + power-domains = <&power RK3588_PD_VO1>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda>; + reg-io-width = <4>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + phys = <&hdptxphy_hdmi0>; + phy-names = "hdmi"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi0_in: port@0 { + reg = <0>; + }; + + hdmi0_out: port@1 { + reg = <1>; + }; + }; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; -- Armbian