Update uboot

Fix final uboot location Remove unnecessary dtb copies
Undo quirks
2026-01-19 23:11:27 -08:00 · 2026-01-19 23:09:50 -08:00 · 2026-01-19 19:38:31 -08:00 · 2026-01-19 19:31:46 -08:00 · 2026-01-19 18:45:47 -08:00 · 2026-01-19 18:41:18 -08:00
101 changed files with 31607 additions and 25729 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -0,0 +1,12 @@
+/_build/lib
+/_build/vmlinuz
+/_build/vmlinuz.config
+/_build/u-boot-rockchip.bin
+/_build/dtbs
+/_build/*.dtb
+/_build/gokr-rebuild*
+/_build/overlays
+/_build/Dockerfile
+/_build/src_build
+/_build/*.tar.gz
+/_build/*.tar.xz
--- a/cmd/gokr-build-kernel/config.txt
+++ b/cmd/gokr-build-kernel/config.txt
@@ -1,13 +1,45 @@
 CONFIG_IPV6=y
-CONFIG_DYNAMIC_DEBUG=y
+# Compile in debug logging
+# CONFIG_DYNAMIC_DEBUG=y
+
+# Speed up boot and processing in general
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_DEBUG_KERNEL=n
+
+# Syn flood protection. Configurable in /proc
+CONFIG_SYN_COOKIES=y
+
+# I use btrfs
+CONFIG_BTRFS_FS=y
+CONFIG_BTRFS_FS_POSIX_ACL=y
+
+# NTFS
+CONFIG_NTFS3_FS=y
+
+CONFIG_XFS_FS=y
+CONFIG_BCACHE=y
+
+# Energy efficiency over performance
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y

 # For Squashfs (root file system):
 CONFIG_SQUASHFS=y
 CONFIG_SQUASHFS_FILE_CACHE=y
+CONFIG_SQUASHFS_XATTR=y
 CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_ZSTD=y
 CONFIG_SQUASHFS_ZLIB=y
 CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3

+# Support video decoding
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_ROCKCHIP_IEP=y
+CONFIG_VIDEO_ROCKCHIP_VDEC=y
+
+# I added the patch for it
+CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG=y
+
+CONFIG_DRM=y
 # For a console on HDMI:
 # # TODO: the simpledrm driver just does not work for me. the ASRock logo never disappears from HDMI
 # # [    0.364059] [drm] Initialized simpledrm 1.0.0 20200625 for simple-framebuffer.0 on minor 0
@@ -35,36 +67,178 @@ CONFIG_FUSE_FS=y
 CONFIG_NETFILTER_NETLINK_QUEUE=y
 CONFIG_XFRM_USER=y

-# For nftables:
-CONFIG_NF_TABLES=y
+# Enable the RK3588 CPU
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_CPU_RK3588=y
+
+# Enable all the ROCKCHIP options TODO are some of these even used???
+CONFIG_CRYPTO_DEV_ROCKCHIP2=y
+CONFIG_CRYPTO_DEV_ROCKCHIP=y
+CONFIG_HW_RANDOM_ROCKCHIP=y
+CONFIG_MFD_RK8XX_I2C=y
+CONFIG_MFD_RK8XX_SPI=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+CONFIG_NVMEM_ROCKCHIP_OTP=y
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PHY_ROCKCHIP_DP=y
+CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
+CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_ROCKCHIP_SFC=y
+CONFIG_VIDEO_ROCKCHIP_VDEC2=y
+
+# Rockchip MMC
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+# Fan control?
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FAN53200=y
+
+# Not Needed???
+CONFIG_RTC_DRV_RK808=y
+# CM3588 RTC driver
+CONFIG_RTC_DRV_HYM8563=y
+
+# Shouldn't this be done elsewhere?
+CONFIG_CMDLINE="console=ttyAMA0"
+
+# This is what friendlyelec has
+CONFIG_HZ_300=y
+
+# Quad core CPU
+CONFIG_NR_CPUS=8
+
+# Power button
+CONFIG_PINCTRL_RK805=y
+CONFIG_INPUT_RK805_PWRKEY=y
+
+# Needed to ensure DWMAC_ROCKCHIP is built, which is needed for Ethernet..... probabl
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+
+# cm3588 ethernet driver
+CONFIG_REALTEK_PHY=y
+CONFIG_R8169=y
+CONFIG_R8169_LEDS=y
+
+# Try to enable HDMI out
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_ROCKCHIP_VOP2=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_HDMI_QP=y
+CONFIG_DRM_PANTHOR=y
+# Needed for V4L
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_ROCKCHIP_VDEC=y
+CONFIG_VIDEO_ROCKCHIP_RGA=y
+CONFIG_VIDEO_HANTRO=y
+CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+
+#Maybe needed
+CONFIG_VIDEO_MUX=y
+CONFIG_VIDEO_ROCKCHIP_ISP1=y
+CONFIG_VIDEO_ROCKCHIP_IEP=y
+
+# USB Stuff??
+CONFIG_TYPEC=y
+CONFIG_USB_DWC3_ULPI=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
+
+# Possibly used for gpu acceleration
+CONFIG_DMABUF_HEAPS=y
+CONFIG_DMABUF_HEAPS_SYSTEM=y
+CONFIG_DMABUF_HEAPS_CMA=y
+
+
+# Try to enable sound
+CONFIG_SND_SOC_RT5616=y
+
+# For podman:
+
+CONFIG_OVERLAY_FS=y
+CONFIG_VETH=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_BRIDGE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NF_FLOW_TABLE=y
+CONFIG_NF_FLOW_TABLE_INET=y
+CONFIG_NF_LOG_SYSLOG=y
+CONFIG_NF_MASQUERADE=y
+CONFIG_NF_NAT=y
 CONFIG_NF_NAT_IPV4=y
+CONFIG_NF_NAT_MASQUERADE=y
 CONFIG_NF_NAT_MASQUERADE_IPV4=y
-CONFIG_NFT_PAYLOAD=y
-CONFIG_NFT_EXTHDR=y
-CONFIG_NFT_META=y
-CONFIG_NFT_CT=y
-CONFIG_NFT_RBTREE=y
-CONFIG_NFT_HASH=y
-CONFIG_NFT_COUNTER=y
-CONFIG_NFT_LOG=y
-CONFIG_NFT_LIMIT=y
-CONFIG_NFT_NAT=y
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_TABLES=y
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_CHAIN_NAT_IPV4=y
+CONFIG_NFT_CHAIN_ROUTE_IPV4=y
+CONFIG_NFT_CHAIN_ROUTE_IPV6=y
 CONFIG_NFT_COMPAT=y
+CONFIG_NFT_COUNTER=y
+CONFIG_NFT_CT=y
+CONFIG_NFT_DUP_IPV4=y
+CONFIG_NFT_DUP_IPV6=y
+CONFIG_NFT_EXTHDR=y
+CONFIG_NFT_FIB_INET=y
+CONFIG_NFT_FIB_IPV4=y
+CONFIG_NFT_FIB_IPV6=y
+CONFIG_NFT_FIB_NETDEV=y
+CONFIG_NFT_HASH=y
+CONFIG_NFT_LIMIT=y
+CONFIG_NFT_LOG=y
 CONFIG_NFT_MASQ=y
 CONFIG_NFT_MASQ_IPV4=y
+CONFIG_NFT_META=y
+CONFIG_NFT_NAT=y
+CONFIG_NFT_OBJREF=y
+CONFIG_NFT_PAYLOAD=y
+CONFIG_NFT_RBTREE=y
 CONFIG_NFT_REDIR=y
 CONFIG_NFT_REJECT=y
-CONFIG_NF_TABLES_IPV4=y
+CONFIG_NFT_REJECT_INET=y
 CONFIG_NFT_REJECT_IPV4=y
-CONFIG_NFT_CHAIN_ROUTE_IPV4=y
-CONFIG_NFT_CHAIN_NAT_IPV4=y
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_CHAIN_ROUTE_IPV6=y
-CONFIG_NFT_OBJREF=y
-CONFIG_NFT_DUP_IPV4=y
-CONFIG_NFT_FIB_IPV4=y
-CONFIG_NFT_DUP_IPV6=y
-CONFIG_NFT_FIB_IPV6=y
+CONFIG_NFT_REJECT_NETDEV=y

 # Explicitly disable nftables helper modules to prevent NAT slipstreaming attacks:
 # https://samy.pl/slipstream/
@@ -92,26 +266,6 @@ CONFIG_NVME_MULTIPATH=y
 CONFIG_NVME_HWMON=y
 CONFIG_NVME_TARGET_PASSTHRU=y

-# For https://www.fs.com/products/75602.html and https://www.fs.com/products/75603.html network cards:
-CONFIG_I40E=y
-
-# For Intel E810 series network cards:
-CONFIG_ICE=y
-
-# For Broadcom 57414 10/25 Gbit/s network card:
-CONFIG_BNXT=y
-
-# For Mellanox ConnectX-4 25 Gbit/s network cards:
-CONFIG_MLX5_EN=y
-CONFIG_MLX5_CORE=y
-CONFIG_MLX5_CORE_EN=y
-CONFIG_MLX5_INFINIBAND=n
-
-# For apu2c4 ethernet ports
-CONFIG_IGB=y
-
-# For Intel I225 ethernet ports (ASRock B550 Taichi):
-CONFIG_IGC=y

 # For /proc/config.gz
 CONFIG_IKCONFIG=y
@@ -120,8 +274,6 @@ CONFIG_IKCONFIG_PROC=y
 # For kexec
 CONFIG_KEXEC_FILE=y

-# For apu2c4 watchdog
-CONFIG_SP5100_TCO=y

 # For WireGuard
 CONFIG_NET_UDP_TUNNEL=y
@@ -133,46 +285,33 @@ CONFIG_NET_SCH_TBF=y
 # For measuring CPU temperature:
 CONFIG_SENSORS_K10TEMP=y

-# For measuring non-CPU temperature and fan speeds: Crashes on cm3588
-# CONFIG_SENSORS_NCT6683=y
-
-# For Corsair Commander Pro fan controller:
-CONFIG_SENSORS_CORSAIR_CPRO=y
-
 # For iproute2’s ss(8):
-CONFIG_INET_DIAG=y
+# CONFIG_INET_DIAG=y
+# CONFIG_UNIX_DIAG=y
+# CONFIG_PACKET_DIAG=y # ss

 # For macvlan ethernet devices:
 CONFIG_MACVLAN=y

 # For virtio drivers (for qemu):
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_RING=y
+#CONFIG_VIRTIO_PCI=y
+#CONFIG_VIRTIO_BALLOON=y
+#CONFIG_VIRTIO_BLK=y
+#CONFIG_VIRTIO_NET=y
+#CONFIG_VIRTIO=y
+#CONFIG_VIRTIO_RING=y
 # For watchdog within qemu:
-CONFIG_I6300ESB_WDT=y
+#CONFIG_I6300ESB_WDT=y

 # For running KVM-accelerated qemu VMs:
-CONFIG_KVM=y
-CONFIG_KVM_INTEL=y
-CONFIG_KVM_AMD=y
-CONFIG_KVM_AMD_SEV=y
+#CONFIG_KVM=y
+#CONFIG_KVM_INTEL=y
+#CONFIG_KVM_AMD=y
+#CONFIG_KVM_AMD_SEV=y

 # For bridge ethernet devices:
 CONFIG_BRIDGE=y

-CONFIG_EFIVAR_FS=y
-
-# For Ryzen CPUs:
-CONFIG_X86_AMD_PLATFORM_DEVICE=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_X86_POWERNOW_K8=y
-CONFIG_X86_AMD_FREQ_SENSITIVITY=y
-
 # Include hardware interrupt CPU usage in /proc/stat CPU time reporting:
 CONFIG_IRQ_TIME_ACCOUNTING=y

@@ -185,19 +324,7 @@ CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_BPF=y
 CONFIG_SOCK_CGROUP_DATA=y
 CONFIG_NET_SOCK_MSG=y
-# For podman:
-CONFIG_OVERLAY_FS=y
-CONFIG_BRIDGE=y
-CONFIG_VETH=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_IP_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_NETFILTER_XT_NAT=y
-CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
-CONFIG_NETFILTER_XT_MARK=y
-CONFIG_CGROUP_PIDS=y
+

 # Enable TCP BBR as default congestion control
 CONFIG_TCP_CONG_BBR=y
@@ -239,271 +366,31 @@ CONFIG_WERROR=n
 CONFIG_KERNEL_ZSTD=y

 # For qemu -M microvm quick boots:
-CONFIG_VIRTIO_MMIO=y
+#CONFIG_VIRTIO_MMIO=y

-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_XEN_VIRTIO=y
-CONFIG_VIRTIO_IOMMU=y
+# Relevant for rk3588????
+# CONFIG_HW_RANDOM_VIRTIO=y
+# CONFIG_XEN_VIRTIO=y
+# CONFIG_VIRTIO_IOMMU=y

+# for easy sandboxing with go-landlock
+CONFIG_SECURITY_LANDLOCK=y
+
+# ???????
 CONFIG_IPV6_MULTIPLE_TABLES=y
 CONFIG_NF_SOCKET_IPV6=y
 CONFIG_NETLINK_DIAG=y
 CONFIG_INET_DIAG_DESTROY=y

-# More AWS stuff:
-CONFIG_ENA_ETHERNET=y
-CONFIG_RANDOM_TRUST_CPU=y
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-
-# For older AWS:
-CONFIG_XEN=y
-CONFIG_XEN_DOM0=y
-CONFIG_XEN_PRIVILEGED_GUEST=y
-CONFIG_XEN_PVHVM=y
-
-
-# Speed up boot and processing in general
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_DEBUG_KERNEL=n
-
-# Enable the RK3588 CPU
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_CPU_RK3588=y
-
-# Enable all the ROCKCHIP options
-CONFIG_CRYPTO_DEV_ROCKCHIP2=y
-CONFIG_CRYPTO_DEV_ROCKCHIP=y
-CONFIG_HW_RANDOM_ROCKCHIP=y
-CONFIG_MFD_RK8XX_I2C=y
-CONFIG_MFD_RK8XX_SPI=y
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_NVMEM_ROCKCHIP_EFUSE=y
-CONFIG_NVMEM_ROCKCHIP_OTP=y
-CONFIG_PCIE_ROCKCHIP_HOST=y
-CONFIG_PHY_ROCKCHIP_DP=y
-CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
-CONFIG_PHY_ROCKCHIP_EMMC=y
-CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
-CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
-CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
-CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
-CONFIG_PHY_ROCKCHIP_PCIE=y
-CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
-CONFIG_PHY_ROCKCHIP_TYPEC=y
-CONFIG_PHY_ROCKCHIP_USB=y
-CONFIG_PHY_ROCKCHIP_USBDP=y
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_IOMMU=y
-CONFIG_ROCKCHIP_MBOX=y
-CONFIG_ROCKCHIP_PHY=y
-CONFIG_ROCKCHIP_PM_DOMAINS=y
-CONFIG_ROCKCHIP_THERMAL=y
-CONFIG_SND_SOC_RK3328=y
-CONFIG_SPI_ROCKCHIP=y
-CONFIG_SPI_ROCKCHIP_SFC=y
-CONFIG_VIDEO_ROCKCHIP_VDEC2=y
-
-# CM3588 RTC driver
-CONFIG_RTC_DRV_RK808=y
-
-# Shouldn't this be done elsewhere?
-CONFIG_CMDLINE="console=ttyAMA0"
-
-# This is what friendlyelec has
-CONFIG_HZ_300=y
-
-# Quad core CPU
-CONFIG_NR_CPUS=8
-
-# Power button
-CONFIG_PINCTRL_RK805=y
-CONFIG_INPUT_RK805_PWRKEY=y
-
-# Needed to ensure DWMAC_ROCKCHIP is built, which is needed for Ethernet
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_ROCKCHIP=y
-
-# Ethernet driver
-CONFIG_REALTEK_PHY=y
-CONFIG_R8169=y
-
-# Try to enable HDMI out
-CONFIG_DRM_ROCKCHIP=y
-
-
-# Try to enable sound
-CONFIG_SND_SOC_ROCKCHIP=y
-CONFIG_SND_SOC_ROCKCHIP_DLP_PCM=y
-CONFIG_SND_SOC_ROCKCHIP_I2S=y
-CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
-CONFIG_SND_SOC_ROCKCHIP_PDM=y
-CONFIG_SND_SOC_ROCKCHIP_SAI=y
-CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
-CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=y
-CONFIG_SND_SOC_ROCKCHIP_VAD=y
-CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
-CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
-CONFIG_SND_SOC_ROCKCHIP_RT5645=y
-CONFIG_SND_SOC_ROCKCHIP_HDMI=y
-
-
-CONFIG_OVERLAY_FS=y
-CONFIG_OVERLAY_FS_INDEX=y
-
-
-# # disable other arches
-# CONFIG_ARCH_ACTIONS=n
-# CONFIG_ARCH_AIROHA=n
-# CONFIG_ARCH_ALPINE=n
-# CONFIG_ARCH_APPLE=n
-# CONFIG_ARCH_BCM2835=n
-# CONFIG_ARCH_BCM=n
-# CONFIG_ARCH_BCM_IPROC=n
-# CONFIG_ARCH_BCMBCA=n
-# CONFIG_ARCH_BERLIN=n
-# CONFIG_ARCH_BRCMSTB=n
-# CONFIG_ARCH_EXYNOS=n
-# CONFIG_ARCH_HISI=n
-# CONFIG_ARCH_INTEL_SOCFPGA=n
-# CONFIG_ARCH_K3=n
-# CONFIG_ARCH_KEEMBAY=n
-# CONFIG_ARCH_LAYERSCAPE=n
-# CONFIG_ARCH_LG1K=n
-# CONFIG_ARCH_MA35=n
-# CONFIG_ARCH_MEDIATEK=n
-# CONFIG_ARCH_MESON=n
-# CONFIG_ARCH_MVEBU=n
-# CONFIG_ARCH_MXC=n
-# CONFIG_ARCH_NPCM=n
-# CONFIG_ARCH_NXP=n
-# CONFIG_ARCH_QCOM=n
-# CONFIG_ARCH_R8A774A1=n
-# CONFIG_ARCH_R8A774B1=n
-# CONFIG_ARCH_R8A774C0=n
-# CONFIG_ARCH_R8A774E1=n
-# CONFIG_ARCH_R8A77951=n
-# CONFIG_ARCH_R8A77960=n
-# CONFIG_ARCH_R8A77961=n
-# CONFIG_ARCH_R8A77965=n
-# CONFIG_ARCH_R8A77970=n
-# CONFIG_ARCH_R8A77980=n
-# CONFIG_ARCH_R8A77990=n
-# CONFIG_ARCH_R8A77995=n
-# CONFIG_ARCH_R8A779A0=n
-# CONFIG_ARCH_R8A779F0=n
-# CONFIG_ARCH_R8A779G0=n
-# CONFIG_ARCH_R8A779H0=n
-# CONFIG_ARCH_R9A07G043=n
-# CONFIG_ARCH_R9A07G044=n
-# CONFIG_ARCH_R9A07G054=n
-# CONFIG_ARCH_R9A08G045=n
-# CONFIG_ARCH_R9A09G011=n
-# CONFIG_ARCH_R9A09G057=n
-# CONFIG_ARCH_REALTEK=n
-# CONFIG_ARCH_RENESAS=n
-# CONFIG_ARCH_S32=n
-# CONFIG_ARCH_SEATTLE=n
-# CONFIG_ARCH_SPARX5=n
-# CONFIG_ARCH_SPRD=n
-# CONFIG_ARCH_STM32=n
-# CONFIG_ARCH_SUNXI=n
-# CONFIG_ARCH_SYNQUACER=n
-# CONFIG_ARCH_TEGRA=n
-# CONFIG_ARCH_TEGRA_132_SOC=n
-# CONFIG_ARCH_TEGRA_186_SOC=n
-# CONFIG_ARCH_TEGRA_194_SOC=n
-# CONFIG_ARCH_TEGRA_210_SOC=n
-# CONFIG_ARCH_TEGRA_234_SOC=n
-# CONFIG_ARCH_TESLA_FSD=n
-# CONFIG_ARCH_THUNDER2=n
-# CONFIG_ARCH_THUNDER=n
-# CONFIG_ARCH_UNIPHIER=n
-# CONFIG_ARCH_VEXPRESS=n
-# CONFIG_ARCH_VISCONTI=n
-# CONFIG_ARCH_XGENE=n
-# CONFIG_ARCH_ZYNQMP=n
-
-# CONFIG_GOOGLE_FIRMWARE=n
-
-# CONFIG_ATA=n
-
-# CONFIG_MD=n
-
-
-# CONFIG_NET_VENDOR_3COM=n
-# CONFIG_NET_VENDOR_ADAPTEC=n
-# CONFIG_NET_VENDOR_AGERE=n
-# CONFIG_NET_VENDOR_ALACRITECH=n
-# CONFIG_NET_VENDOR_ALTEON=n
-# CONFIG_NET_VENDOR_AMAZON=n
-# CONFIG_NET_VENDOR_AMD=n
-# CONFIG_NET_VENDOR_AQUANTIA=n
-# CONFIG_NET_VENDOR_ARC=n
-# CONFIG_NET_VENDOR_ASIX=n
-# CONFIG_NET_VENDOR_ATHEROS=n
-# CONFIG_NET_VENDOR_CADENCE=n
-# CONFIG_NET_VENDOR_CAVIUM=n
-# CONFIG_NET_VENDOR_CHELSIO=n
-# CONFIG_NET_VENDOR_CISCO=n
-# CONFIG_NET_VENDOR_CORTINA=n
-# CONFIG_NET_VENDOR_DAVICOM=n
-# CONFIG_NET_VENDOR_DEC=n
-# CONFIG_NET_VENDOR_DLINK=n
-# CONFIG_NET_VENDOR_EMULEX=n
-# CONFIG_NET_VENDOR_ENGLEDER=n
-# CONFIG_NET_VENDOR_EZCHIP=n
-# CONFIG_NET_VENDOR_FUNGIBLE=n
-# CONFIG_NET_VENDOR_GOOGLE=n
-# CONFIG_NET_VENDOR_HISILICON=n
-# CONFIG_NET_VENDOR_HUAWEI=n
-# CONFIG_NET_VENDOR_I825XX=n
-# CONFIG_NET_VENDOR_INTEL=n
-# CONFIG_NET_VENDOR_ADI=n
-# CONFIG_NET_VENDOR_LITEX=n
-# CONFIG_NET_VENDOR_MARVELL=n
-# CONFIG_NET_VENDOR_MELLANOX=n
-# CONFIG_NET_VENDOR_MICREL=n
-# CONFIG_NET_VENDOR_MICROCHIP=n
-# CONFIG_NET_VENDOR_MICROSEMI=n
-# CONFIG_NET_VENDOR_MICROSOFT=n
-# CONFIG_NET_VENDOR_MnRI=n
-# CONFIG_NET_VENDOR_NI=n
-# CONFIG_NET_VENDOR_NATSEMI=n
-# CONFIG_NET_VENDOR_NETERION=n
-# CONFIG_NET_VENDOR_NETRONOME=n
-# CONFIG_NET_VENDOR_8390=n
-# CONFIG_NET_VENDOR_NVIDIA=n
-# CONFIG_NET_VENDOR_OKI=n
-# CONFIG_NET_VENDOR_PACKET_ENGINES=n
-# CONFIG_NET_VENDOR_PENSANDO=n
-# CONFIG_NET_VENDOR_QLOGIC=n
-# CONFIG_NET_VENDOR_BROCADE=n
-# CONFIG_NET_VENDOR_QUALCOMM=n
-# CONFIG_NET_VENDOR_RDC=n
-# CONFIG_NET_VENDOR_BROADCOM=n
-# CONFIG_NET_VENDOR_RENESAS=n
-# CONFIG_NET_VENDOR_ROCKER=n
-# CONFIG_NET_VENDOR_SAMSUNG=n
-# CONFIG_NET_VENDOR_SEEQ=n
-# CONFIG_NET_VENDOR_SILAN=n
-# CONFIG_NET_VENDOR_SIS=n
-# CONFIG_NET_VENDOR_SOLARFLARE=n
-# CONFIG_NET_VENDOR_SMSC=n
-# CONFIG_NET_VENDOR_SOCIONEXT=n
-# CONFIG_NET_VENDOR_STMICRO=n
-# CONFIG_NET_VENDOR_SUN=n
-# CONFIG_NET_VENDOR_SnNOPSnS=n
-# CONFIG_NET_VENDOR_TEHUTI=n
-# CONFIG_NET_VENDOR_TI=n
-# CONFIG_NET_VENDOR_VERTEXCOM=n
-# CONFIG_NET_VENDOR_VIA=n
-# CONFIG_NET_VENDOR_WANGXUN=n
-# CONFIG_NET_VENDOR_WIZNET=n
-# CONFIG_NET_VENDOR_XILINX=n
-
-
+# Serial port drivers
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_MKISS=y
+CONFIG_6PACK=y
+CONFIG_BPQETHER=y
+CONFIG_BAYCOM_SER_FDX=y
+CONFIG_BAYCOM_SER_HDX=y
+CONFIG_YAM=y
--- a/_build/patch/0001-gokrazy-logo.patch
+++ b/_build/patch/0001-gokrazy-logo.patch
@@ -0,0 +1,958 @@
+From a4ee8244175776f1f98b7f00bc9b0f3980a174d2 Mon Sep 17 00:00:00 2001
+From: Michael Stapelberg <michael@stapelberg.de>
+Date: Sun, 13 Jun 2021 09:20:06 +0200
+Subject: [PATCH] gokrazy logo
+
+---
+ drivers/video/logo/Kconfig                  |   4 +
+ drivers/video/logo/Makefile                 |   1 +
+ drivers/video/logo/logo.c                   |   4 +
+ drivers/video/logo/logo_gokrazy_clut224.ppm | 883 ++++++++++++++++++++
+ include/linux/linux_logo.h                  |   1 +
+ 5 files changed, 893 insertions(+)
+ create mode 100644 drivers/video/logo/logo_gokrazy_clut224.ppm
+
+diff --git a/drivers/video/logo/Kconfig b/drivers/video/logo/Kconfig
+index 6d6f8c087..360a970f7 100644
+--- a/drivers/video/logo/Kconfig
+++ b/drivers/video/logo/Kconfig
+@@ -68,4 +68,8 @@ config LOGO_SUPERH_CLUT224
+ 	depends on SUPERH
+ 	default y
+ 
+config LOGO_GOKRAZY_CLUT224
+	bool "224-color gokrazy Linux logo"
+	default y
+
+ endif # LOGO
+diff --git a/drivers/video/logo/Makefile b/drivers/video/logo/Makefile
+index 895c60b84..7500454e2 100644
+--- a/drivers/video/logo/Makefile
+++ b/drivers/video/logo/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_LOGO_SUN_CLUT224)		+= logo_sun_clut224.o
+ obj-$(CONFIG_LOGO_SUPERH_MONO)		+= logo_superh_mono.o
+ obj-$(CONFIG_LOGO_SUPERH_VGA16)		+= logo_superh_vga16.o
+ obj-$(CONFIG_LOGO_SUPERH_CLUT224)	+= logo_superh_clut224.o
+obj-$(CONFIG_LOGO_GOKRAZY_CLUT224)	+= logo_gokrazy_clut224.o
+ 
+ obj-$(CONFIG_SPU_BASE)			+= logo_spe_clut224.o
+ 
+diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c
+index 141f15a9a..60a0efba6 100644
+--- a/drivers/video/logo/logo.c
+++ b/drivers/video/logo/logo.c
+@@ -99,6 +99,10 @@ const struct linux_logo * __ref fb_find_logo(int depth)
+ #ifdef CONFIG_LOGO_SUPERH_CLUT224
+ 		/* SuperH Linux logo */
+ 		logo = &logo_superh_clut224;
+#endif
+#ifdef CONFIG_LOGO_GOKRAZY_CLUT224
+		/* gokrazy Linux logo */
+		logo = &logo_gokrazy_clut224;
+ #endif
+ 	}
+ 	return logo;
+diff --git a/drivers/video/logo/logo_gokrazy_clut224.ppm b/drivers/video/logo/logo_gokrazy_clut224.ppm
+new file mode 100644
+index 000000000..1276e5de0
+--- /dev/null
+++ b/drivers/video/logo/logo_gokrazy_clut224.ppm
+@@ -0,0 +1,883 @@
+P3
+80 80
+255
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 9 11 13 1 1 1 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 88 116 137 154 204 239 133 177 207 0 0 0 0 0 0 0 0 0 
+0 0 0 1 1 1 11 14 16 29 36 40 33 44 52 33 44 52 28 37 43 19 25 29 
+3 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 149 198 233 4 5 6 37 49 58 0 0 0 2 3 3 50 66 77 
+124 164 193 155 206 242 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 146 195 229 101 134 158 24 29 35 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 21 28 33 0 0 0 7 9 11 101 134 158 155 206 242 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 143 191 223 55 74 86 1 1 1 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 1 2 2 79 105 124 155 206 242 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 146 195 229 55 74 86 
+0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 18 24 29 144 191 225 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+140 187 219 22 29 34 0 0 0 0 0 0 0 0 0 0 0 0 7 9 11 37 49 58 
+19 25 29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+18 24 29 155 206 242 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 64 85 99 0 0 0 1 1 1 86 114 134 156 207 243 156 207 243 
+156 207 243 127 169 198 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 4 5 
+134 179 211 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 13 16 19 112 148 174 146 195 229 40 53 62 4 5 6 
+11 14 16 124 164 193 33 44 52 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 4 4 3 25 27 28 19 20 21 51 51 49 
+28 31 33 52 60 64 134 179 211 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 125 165 194 83 109 127 64 85 99 
+67 88 102 96 127 150 139 184 216 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 146 195 229 154 205 240 9 11 13 0 0 0 5 6 7 
+92 123 144 156 207 243 45 60 71 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 25 27 28 75 77 77 203 203 203 255 255 255 255 255 255 
+255 255 255 158 158 159 31 38 44 155 206 242 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 139 184 216 54 66 76 19 20 21 100 104 104 134 134 134 
+129 129 129 75 77 77 9 11 13 69 90 105 150 200 234 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 114 152 178 0 0 0 4 5 6 138 183 215 
+146 195 229 152 201 236 5 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 19 18 17 140 140 140 255 255 255 255 255 255 255 255 255 255 255 255 
+255 255 255 255 255 255 52 60 64 113 150 176 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 134 179 211 19 20 21 117 118 118 245 245 245 255 255 255 255 255 255 
+255 255 255 255 255 255 232 232 232 75 77 77 35 45 52 148 196 231 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 142 188 221 5 6 7 35 45 52 
+108 143 169 10 13 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 1 1 1 16 17 18 40 42 45 247 247 247 255 255 255 255 255 255 255 255 255 
+255 255 255 255 255 255 117 118 118 79 105 124 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 150 199 233 29 33 36 158 158 159 255 255 255 255 255 255 255 255 255 255 255 255 
+255 255 255 255 255 255 255 255 255 253 253 253 99 87 96 57 72 83 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 112 148 174 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 158 158 159 147 147 147 211 211 211 255 255 255 255 255 255 255 255 255 
+255 255 255 255 255 255 134 134 134 74 98 115 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 86 114 134 83 85 87 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 
+255 255 255 255 255 255 255 255 255 255 255 255 245 245 245 29 30 31 122 163 191 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 10 13 16 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 10 10 8 19 20 21 242 242 242 255 255 255 255 255 255 255 255 255 
+255 255 255 255 255 255 83 85 87 94 124 145 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 33 42 48 203 203 203 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 
+232 232 232 129 129 129 116 117 118 207 207 207 255 255 255 140 140 140 69 90 105 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 76 102 120 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 5 5 5 7 6 5 158 158 159 255 255 255 255 255 255 255 255 255 255 255 255 
+255 255 255 240 240 240 14 15 15 137 182 213 156 207 243 156 207 243 156 207 243 156 207 243 
+152 201 236 11 14 16 253 253 253 255 255 255 255 255 255 255 255 255 255 255 255 240 240 240 
+29 30 31 0 0 0 2 2 2 16 17 18 207 207 207 203 203 203 40 53 62 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 144 191 225 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 40 42 45 242 242 242 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 
+255 255 255 117 118 118 54 71 82 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+144 191 225 25 27 28 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 166 171 172 
+0 0 0 0 0 0 147 147 147 211 211 211 116 117 118 220 220 220 31 38 44 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+5 7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 22 21 19 254 254 254 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 
+176 181 183 16 17 18 138 183 215 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+154 205 240 16 17 18 251 251 251 255 255 255 255 255 255 255 255 255 255 255 255 166 171 172 
+0 0 0 0 0 0 53 54 55 75 77 77 129 129 129 203 203 203 45 57 65 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+24 29 35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 22 21 19 158 158 159 255 255 255 255 255 255 255 255 255 211 211 211 59 61 63 
+7 9 11 62 82 96 67 88 102 62 82 96 116 154 180 156 207 243 156 207 243 156 207 243 
+156 207 243 52 60 64 193 186 178 255 255 255 255 255 255 255 255 255 255 255 255 247 247 247 
+53 54 55 0 0 0 0 0 0 29 30 31 232 232 232 129 129 129 81 108 126 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+28 37 43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 14 15 15 40 42 45 59 61 63 29 33 36 7 8 8 98 92 84 
+185 178 162 147 146 137 0 0 0 0 0 0 11 13 13 29 33 36 50 66 77 104 138 162 
+156 207 243 110 145 170 63 63 70 254 254 254 255 255 255 255 255 255 255 255 255 255 255 255 
+251 251 251 176 181 183 166 171 172 242 242 242 240 240 240 29 30 31 142 188 221 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+31 41 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 55 74 86 142 188 221 128 170 200 118 156 184 66 73 78 222 196 161 
+222 196 161 222 196 161 185 178 162 147 146 137 193 186 178 222 196 161 185 178 162 59 61 63 
+51 68 80 154 204 239 57 72 83 116 117 118 255 255 255 255 255 255 255 255 255 255 255 255 
+255 255 255 255 255 255 255 255 255 247 247 247 66 73 78 94 124 145 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+13 18 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 110 145 170 156 207 243 156 207 243 120 159 187 100 104 104 222 196 161 
+222 196 161 185 178 162 185 178 162 219 196 162 222 196 161 222 196 161 222 196 161 219 196 162 
+42 42 39 94 124 145 150 199 233 54 66 76 83 85 87 232 232 232 255 255 255 255 255 255 
+255 255 255 255 255 255 207 207 207 53 54 55 83 109 127 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+2 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 1 1 1 143 191 223 156 207 243 156 207 243 154 204 239 40 53 62 66 73 78 
+28 31 33 123 135 144 121 126 131 76 84 87 185 178 162 222 196 161 222 196 161 222 196 161 
+100 104 104 72 95 112 156 207 243 156 207 243 104 138 162 31 38 44 63 63 70 100 104 104 
+100 104 104 40 46 51 52 60 64 120 159 187 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 140 187 219 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 2 2 2 3 2 2 68 61 51 34 30 25 10 8 7 
+0 0 0 7 9 11 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 86 114 134 
+1 2 2 245 245 245 148 159 163 176 181 183 0 0 0 75 77 77 162 154 141 147 146 137 
+10 10 8 108 143 169 156 207 243 156 207 243 156 207 243 156 207 243 134 179 211 116 154 180 
+118 156 184 148 196 231 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 84 111 130 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 8 7 6 121 107 87 222 196 161 185 163 134 9 8 6 
+0 0 0 28 39 45 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 138 183 214 
+2 3 3 166 171 172 148 159 163 123 135 144 0 0 0 0 0 0 0 0 0 0 0 0 
+28 37 43 154 205 240 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 28 37 43 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 9 7 6 121 107 87 222 196 161 212 188 154 3 3 3 
+0 0 0 59 78 92 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+54 71 85 3 4 5 21 28 33 33 42 48 0 0 0 0 0 0 0 0 0 0 0 0 
+84 111 130 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 2 3 3 
+0 0 0 0 0 0 5 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 3 3 3 68 60 49 222 196 161 222 196 161 21 20 18 
+0 0 0 81 108 126 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 154 204 239 
+67 88 102 0 0 0 45 49 57 88 71 86 33 42 48 0 0 0 0 0 0 0 0 0 
+112 148 174 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 127 169 198 0 0 0 
+7 7 5 27 25 20 83 74 61 18 17 14 6 6 4 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 194 172 141 222 196 161 136 119 98 
+8 8 6 104 138 162 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 88 116 137 
+95 74 90 63 63 70 201 82 107 181 84 109 204 82 107 115 90 91 3 4 5 0 0 0 
+113 150 176 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 69 92 108 0 0 0 
+1 1 1 194 172 141 222 196 161 205 181 149 27 25 20 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 68 60 49 220 194 160 222 196 161 
+46 40 33 120 161 189 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 33 42 48 
+201 82 107 88 71 86 181 84 109 95 74 90 204 82 107 204 82 107 115 90 91 0 0 0 
+122 163 191 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 28 39 45 6 6 4 
+68 61 51 222 196 161 222 196 161 222 196 161 106 94 77 9 8 6 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 5 83 74 61 214 189 155 
+34 30 25 130 172 202 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 22 29 34 
+201 82 107 139 97 99 181 84 109 20 25 29 139 97 99 204 82 107 139 97 99 19 25 29 
+152 201 236 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 137 182 213 86 114 134 8 8 6 46 40 33 
+205 181 149 222 196 161 222 196 161 222 196 161 83 74 61 6 6 4 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 7 6 21 20 18 
+13 12 10 134 179 211 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 62 82 96 
+95 74 90 181 84 109 88 71 86 37 49 58 4 5 6 24 29 35 33 42 48 128 170 200 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 79 104 122 14 15 15 68 61 51 145 128 105 220 194 160 
+222 196 161 222 196 161 222 196 161 194 172 141 7 6 5 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+2 2 2 139 184 216 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 152 201 236 
+86 114 134 54 71 82 96 127 150 156 207 243 154 204 239 150 199 233 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 45 49 57 196 177 151 222 196 161 222 196 161 222 196 161 
+222 196 161 222 196 161 194 172 141 27 25 20 9 7 6 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+1 2 2 142 188 221 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 57 72 83 162 154 141 222 196 161 222 196 161 222 196 161 
+194 172 141 106 94 77 7 6 5 7 7 5 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 140 187 219 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 138 183 214 40 42 45 51 51 49 60 59 51 21 20 18 
+12 11 8 10 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 1 1 139 184 216 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 51 68 80 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 1 1 138 183 214 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 51 68 80 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+1 1 1 134 179 211 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 45 57 65 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+1 2 2 128 170 200 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 40 53 62 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+2 2 3 124 164 193 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 51 68 80 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+2 2 3 118 156 184 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 69 92 108 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+1 1 1 113 150 176 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 92 123 144 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 96 127 150 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 120 161 189 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 69 92 108 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 152 201 236 1 2 2 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 37 49 58 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 18 24 29 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 7 9 11 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 55 74 86 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 1 130 172 202 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 101 134 158 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 69 92 108 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 120 161 189 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 11 14 16 154 205 240 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 116 154 180 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 108 143 169 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 96 127 150 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 21 28 33 155 206 242 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 51 68 80 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 1 79 105 124 76 102 120 79 105 124 134 179 211 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 13 16 19 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 11 9 8 18 17 14 90 80 66 68 61 51 5 7 7 
+118 156 184 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 125 165 194 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 14 11 10 76 70 63 214 189 155 222 196 161 222 196 161 110 101 88 
+8 10 11 150 199 233 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 37 49 58 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 34 30 25 220 194 160 222 196 161 222 196 161 222 196 161 217 192 158 
+11 9 8 88 116 137 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 127 169 198 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 46 40 33 214 189 155 222 196 161 222 196 161 222 196 161 222 196 161 
+76 70 63 24 29 35 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 154 204 239 13 18 22 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 13 12 10 21 20 18 136 119 98 220 194 160 222 196 161 222 196 161 
+121 107 87 8 7 6 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 59 78 92 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 14 11 10 106 94 77 222 196 161 222 196 161 
+145 128 105 2 2 1 142 188 221 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 84 111 130 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 4 3 185 163 134 222 196 161 
+121 107 87 7 6 5 1 1 1 45 57 65 128 170 200 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 72 95 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 5 5 21 20 18 83 74 61 
+14 11 10 4 4 3 0 0 0 0 0 0 0 0 0 13 18 22 74 98 115 138 183 215 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 142 188 221 
+28 37 43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+10 13 16 54 71 85 113 150 176 149 198 233 156 207 243 156 207 243 156 207 243 156 207 243 
+156 207 243 156 207 243 156 207 243 156 207 243 156 207 243 142 184 214 76 84 87 8 7 6 
+4 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 9 11 13 37 49 58 59 78 92 74 98 115 
+88 116 137 92 123 144 79 104 122 50 66 77 9 11 13 1 1 1 46 40 33 145 128 105 
+106 94 77 5 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 106 94 77 222 196 161 222 196 161 
+222 196 161 106 94 77 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 145 128 105 222 196 161 222 196 161 
+222 196 161 222 196 161 90 80 66 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 6 6 4 106 94 77 222 196 161 222 196 161 
+222 196 161 222 196 161 212 188 154 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 46 40 33 110 101 88 
+145 128 105 205 181 149 185 163 134 5 5 3 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 11 8 
+11 9 8 0 0 0 0 0 0 3 2 2 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+
+diff --git a/include/linux/linux_logo.h b/include/linux/linux_logo.h
+index d4d5b93ef..777fd6686 100644
+--- a/include/linux/linux_logo.h
+++ b/include/linux/linux_logo.h
+@@ -45,6 +45,7 @@ extern const struct linux_logo logo_superh_mono;
+ extern const struct linux_logo logo_superh_vga16;
+ extern const struct linux_logo logo_superh_clut224;
+ extern const struct linux_logo logo_spe_clut224;
+extern const struct linux_logo logo_gokrazy_clut224;
+ 
+ extern const struct linux_logo *fb_find_logo(int depth);
+ #ifdef CONFIG_FB_LOGO_EXTRA
+-- 
+2.31.1
+
--- a/_build/patch/drv-spi-spidev-remove-warnings.patch
+++ b/_build/patch/drv-spi-spidev-remove-warnings.patch
@@ -0,0 +1,33 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: John Doe <john.doe@somewhere.on.planet>
+Date: Wed, 14 Aug 2024 16:33:07 +0000
+Subject: rockchip64: edge: 6.10.5 drv:spi:spidev remove warnings
+
+Signed-off-by: John Doe <john.doe@somewhere.on.planet>
+---
+ drivers/spi/spidev.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 111111111111..222222222222 100644
+--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
+@@ -703,6 +703,7 @@ static const struct class spidev_class = {
+  * spidev_dt_ids array below. Both arrays are kept in the same ordering.
+  */
+ static const struct spi_device_id spidev_spi_ids[] = {
+	{ .name = "spi-dev" },
+ 	{ .name = /* abb */ "spi-sensor" },
+ 	{ .name = /* cisco */ "spi-petra" },
+ 	{ .name = /* dh */ "dhcom-board" },
+@@ -736,6 +737,7 @@ static int spidev_of_check(struct device *dev)
+ }
+ 
+ static const struct of_device_id spidev_dt_ids[] = {
+	{ .compatible = "armbian,spi-dev", .data = &spidev_of_check },
+ 	{ .compatible = "abb,spi-sensor", .data = &spidev_of_check },
+ 	{ .compatible = "cisco,spi-petra", .data = &spidev_of_check },
+ 	{ .compatible = "dh,dhcom-board", .data = &spidev_of_check },
+-- 
+Armbian
+
--- a/_build/patch/general-add-hdmi-mks-ips50-resolutions.patch
+++ b/_build/patch/general-add-hdmi-mks-ips50-resolutions.patch
@@ -0,0 +1,83 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Maxim Medvedev <redrathnure@gmail.com>
+Date: Mon, 1 Jan 2024 21:50:10 +0000
+Subject: HDMI EDID records for 800x480 resolution (a MKS IPS50 screen and
+ similar)
+
+---
+ drivers/gpu/drm/drm_edid.c                    | 12 +++++++++-
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c |  1 +
+ drivers/video/hdmi.c                          |  2 ++
+ include/linux/hdmi.h                          |  1 +
+ 4 files changed, 15 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
+@@ -1561,6 +1561,16 @@ static const struct drm_display_mode edid_cea_modes_193[] = {
+ 		   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
+ 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ 	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
+	/* 220 - 800x480@60Hz 5:3 */
+	{ DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30240, 800, 850,
+		   920, 960, 0, 480, 510, 513, 525, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_5_3, },
+	/* 221 - 800x480@60Hz 5:3, MKS IPS50 */
+	{ DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30240, 800, 850,
+		   950, 960, 0, 480, 510, 513, 525, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+	  .picture_aspect_ratio = HDMI_PICTURE_ASPECT_5_3, },
+ };
+ 
+ /*
+@@ -4236,7 +4246,7 @@ static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
+ static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
+ {
+ 	BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
+-	BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
+	BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 221);
+ 
+ 	if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
+ 		return &edid_cea_modes_1[vic - 1];
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index 111111111111..222222222222 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -295,6 +295,7 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
+ 	{ 25175000,  31468750,  1,   41, 0, 3, 3,  1, 3, 3,  4, 0, 0xf5554f},
+ 	{ 27000000,  27000000,  1,   36, 0, 3, 3,  1, 2, 3,  4, 0,      0x0},
+ 	{ 27000000,  33750000,  1,   45, 0, 3, 3,  1, 3, 3,  4, 0,      0x0},
+	{ 30240000,  30240000,  5,  504, 3, 2, 2, 20, 4, 2,  2, 0,      0x0}, // Non standard screens like MKS IPS50
+ 	{ 31500000,  31500000,  1,   42, 0, 3, 3,  1, 2, 3,  4, 0,      0x0},
+ 	{ 31500000,  39375000,  1,  105, 1, 3, 3, 10, 0, 3,  4, 0,      0x0},
+ 	{ 33750000,  33750000,  1,   45, 0, 3, 3,  1, 2, 3,  4, 0,      0x0},
+diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
+index 111111111111..222222222222 100644
+--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
+@@ -1087,6 +1087,8 @@ hdmi_picture_aspect_get_name(enum hdmi_picture_aspect picture_aspect)
+ 		return "64:27";
+ 	case HDMI_PICTURE_ASPECT_256_135:
+ 		return "256:135";
+	case HDMI_PICTURE_ASPECT_5_3:
+		return "5:3";
+ 	case HDMI_PICTURE_ASPECT_RESERVED:
+ 		return "Reserved";
+ 	}
+diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
+index 111111111111..222222222222 100644
+--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
+@@ -108,6 +108,7 @@ enum hdmi_picture_aspect {
+ 	HDMI_PICTURE_ASPECT_16_9,
+ 	HDMI_PICTURE_ASPECT_64_27,
+ 	HDMI_PICTURE_ASPECT_256_135,
+	HDMI_PICTURE_ASPECT_5_3,
+ 	HDMI_PICTURE_ASPECT_RESERVED,
+ };
+ 
+-- 
+Armbian
+
--- a/_build/patch/general-add-pll-hdmi-timings.patch
+++ b/_build/patch/general-add-pll-hdmi-timings.patch
@@ -0,0 +1,155 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: paolo <paolo.sabatino@gmail.com>
+Date: Sun, 17 Jan 2021 10:20:21 +0000
+Subject: [ARCHEOLOGY] Adding pll hdmi timing to rockchip64-dev too
+
+> X-Git-Archeology: > recovered message: > Fixed rk3328 mali node, shortening memory range to 0x30000 as per-stated in official documentation
+> X-Git-Archeology: - Revision 3a037e899b06452043e23cd2a17f40fe1a932c5f: https://github.com/armbian/build/commit/3a037e899b06452043e23cd2a17f40fe1a932c5f
+> X-Git-Archeology:   Date: Sun, 17 Jan 2021 10:20:21 +0000
+> X-Git-Archeology:   From: paolo <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: Adding pll hdmi timing to rockchip64-dev too
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 71 ++++++++++
+ 1 file changed, 71 insertions(+)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index 111111111111..222222222222 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -465,6 +465,77 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
+ 	{594000000, 297000000,  1,   99, 0, 1, 1,  1, 0, 1,  1, 0,      0x0},
+ 	{594000000, 371250000,  4,  495, 0, 3, 1,  1, 3, 0,  0, 1,      0x0},
+ 	{594000000, 594000000,  1,   99, 0, 2, 0,  1, 0, 1,  1, 0,      0x0},
+	{ 25175000,  25175000, 30, 1007, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{ 31500000,  31500000,  1,   21, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{ 33750000,  33750000,  1,   45, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{ 35500000,  35500000,  3,   71, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{ 36000000,  36000000,  1,   12, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{ 49500000,  49500000,  1,   33, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{ 50000000,  50000000,  3,   50, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{ 56250000,  56250000,  1,   75, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{ 65000000,  65000000,  3,   65, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{ 68250000,  68250000,  1,   91, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{ 71000000,  71000000,  3,   71, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{ 72000000,  72000000,  1,   24, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{ 73250000,  73250000,  3,  293, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{ 75000000,  75000000,  1,   25, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{ 78750000,  78750000,  1,  105, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{ 79500000,  79500000,  1,   53, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{ 83500000,  83500000,  3,  167, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{ 85500000,  85500000,  1,   57, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{ 88750000,  88750000,  3,  355, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{ 94500000,  94500000,  1,   63, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{101000000, 101000000,  3,  101, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{102250000, 102250000,  3,  409, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{106500000, 106500000,  1,   71, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{108000000, 108000000,  1,   36, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{115500000, 115500000,  1,   77, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{117500000, 117500000,  3,  235, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{119000000, 119000000,  3,  119, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{121750000, 121750000,  3,  487, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{122500000, 122500000,  3,  245, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{135000000, 135000000,  1,   45, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{136750000, 136750000,  3,  547, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{140250000, 140250000,  1,  187, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{146250000, 146250000,  1,  195, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{148250000, 148250000,  3,  593, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{154000000, 154000000,  3,  154, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{156000000, 156000000,  1,   52, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{156750000, 156750000,  1,  209, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{157000000, 157000000,  3,  157, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{157500000, 157500000,  1,  105, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{162000000, 162000000,  1,   54, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{175500000, 175500000,  1,  117, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{179500000, 179500000,  3,  359, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{182750000, 182750000,  3,  731, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{187000000, 187000000,  3,  187, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{187250000, 187250000,  3,  749, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{189000000, 189000000,  1,   63, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{193250000, 193250000,  3,  773, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{202500000, 202500000,  1,  135, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{204750000, 204750000,  1,  273, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{208000000, 208000000,  3,  208, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{214750000, 214750000,  3,  859, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{218250000, 218250000,  1,  291, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{229500000, 229500000,  1,  153, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{234000000, 234000000,  1,   78, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{241500000, 241500000,  1,  161, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{245250000, 245250000,  1,  327, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{245500000, 245500000,  3,  491, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{261000000, 261000000,  1,   87, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{268250000, 268250000,  3, 1073, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{268500000, 268500000,  1,  179, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{281250000, 281250000,  1,  375, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{288000000, 288000000,  1,   96, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{312250000, 312250000,  3, 1249, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{317000000, 317000000,  3,  317, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+	{333250000, 333250000,  3, 1333, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{348500000, 348500000,  3,  697, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{356500000, 356500000,  3,  713, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{380500000, 380500000,  3,  761, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+	{443250000, 443250000,  1,  591, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{505250000, 505250000,  3, 2021, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+	{552750000, 552750000,  1,  737, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ 	{ /* sentinel */ }
+ };
+ 
+-- 
+Armbian
+
--- a/_build/patch/general-cryptov1-trng.patch
+++ b/_build/patch/general-cryptov1-trng.patch
@@ -0,0 +1,302 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 14 Jan 2024 11:53:20 +0100
+Subject: rockchip64: add TRNG to existing crypto v1 driver
+
+ original patch source: https://patchwork.kernel.org/project/linux-rockchip/patch/20230707115242.3411259-1-clabbe@baylibre.com/
+---
+ drivers/crypto/Kconfig                           |  8 +
+ drivers/crypto/rockchip/Makefile                 |  1 +
+ drivers/crypto/rockchip/rk3288_crypto.c          | 18 +-
+ drivers/crypto/rockchip/rk3288_crypto.h          | 18 ++
+ drivers/crypto/rockchip/rk3288_crypto_ahash.c    |  2 +
+ drivers/crypto/rockchip/rk3288_crypto_skcipher.c |  2 +
+ drivers/crypto/rockchip/rk3288_crypto_trng.c     | 92 ++++++++++
+ 7 files changed, 140 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
+@@ -707,6 +707,14 @@ config CRYPTO_DEV_ROCKCHIP
+ 	  This driver interfaces with the hardware crypto accelerator.
+ 	  Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
+ 
+config CRYPTO_DEV_ROCKCHIP_TRNG
+	bool "Support for Rockchip TRNG"
+	depends on CRYPTO_DEV_ROCKCHIP
+	select HW_RANDOM
+	help
+	  Select this option if you want to provide kernel-side support for
+	  the True Random Number Generator found in the Crypto IP.
+
+ config CRYPTO_DEV_ROCKCHIP_DEBUG
+ 	bool "Enable Rockchip crypto stats"
+ 	depends on CRYPTO_DEV_ROCKCHIP
+diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/crypto/rockchip/Makefile
+++ b/drivers/crypto/rockchip/Makefile
+@@ -3,3 +3,4 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o
+ rk_crypto-objs := rk3288_crypto.o \
+ 		  rk3288_crypto_skcipher.o \
+ 		  rk3288_crypto_ahash.o
+rk_crypto-$(CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG) += rk3288_crypto_trng.o
+diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c
+index 111111111111..222222222222 100644
+--- a/drivers/crypto/rockchip/rk3288_crypto.c
+++ b/drivers/crypto/rockchip/rk3288_crypto.c
+@@ -47,15 +47,18 @@ static const struct rk_variant rk3288_variant = {
+ 	.num_clks = 4,
+ 	.rkclks = {
+ 		{ "sclk", 150000000},
+-	}
+	},
+	.trng = false,
+ };
+ 
+ static const struct rk_variant rk3328_variant = {
+ 	.num_clks = 3,
+	.trng = false,
+ };
+ 
+ static const struct rk_variant rk3399_variant = {
+ 	.num_clks = 3,
+	.trng = true,
+ };
+ 
+ static int rk_crypto_get_clks(struct rk_crypto_info *dev)
+@@ -201,6 +204,10 @@ static int rk_crypto_debugfs_show(struct seq_file *seq, void *v)
+ 		seq_printf(seq, "%s %s requests: %lu\n",
+ 			   dev_driver_string(dd->dev), dev_name(dd->dev),
+ 			   dd->nreq);
+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG
+		seq_printf(seq, "HWRNG: %lu %lu\n",
+			   dd->hwrng_stat_req, dd->hwrng_stat_bytes);
+#endif
+ 	}
+ 	spin_unlock(&rocklist.lock);
+ 
+@@ -395,6 +402,10 @@ static int rk_crypto_probe(struct platform_device *pdev)
+ 			dev_err(dev, "Fail to register crypto algorithms");
+ 			goto err_register_alg;
+ 		}
+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG
+		if (crypto_info->variant->trng)
+			rk3288_hwrng_register(crypto_info);
+#endif
+ 
+ 		register_debugfs(crypto_info);
+ 	}
+@@ -425,6 +436,11 @@ static void rk_crypto_remove(struct platform_device *pdev)
+ #ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG
+ 		debugfs_remove_recursive(rocklist.dbgfs_dir);
+ #endif
+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG
+		if (crypto_tmp->variant->trng)
+			rk3288_hwrng_unregister(crypto_tmp);
+#endif
+
+ 		rk_crypto_unregister();
+ 	}
+ 	rk_crypto_pm_exit(crypto_tmp);
+diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h
+index 111111111111..222222222222 100644
+--- a/drivers/crypto/rockchip/rk3288_crypto.h
+++ b/drivers/crypto/rockchip/rk3288_crypto.h
+@@ -11,6 +11,7 @@
+ #include <crypto/sha1.h>
+ #include <crypto/sha2.h>
+ #include <linux/dma-mapping.h>
+#include <linux/hw_random.h>
+ #include <linux/interrupt.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/scatterlist.h>
+@@ -180,6 +181,16 @@
+ #define RK_CRYPTO_HASH_DOUT_6		0x01a4
+ #define RK_CRYPTO_HASH_DOUT_7		0x01a8
+ 
+#define RK_CRYPTO_TRNG_CTRL		0x0200
+#define RK_CRYPTO_OSC_ENABLE		BIT(16)
+#define RK_CRYPTO_TRNG_DOUT_0		0x0204
+/* sample < 1000 lead to 100% failure on rngtest,
+ * using more than 1200 does not increase success.
+ */
+#define RK_CRYPTO_RNG_SAMPLE		1200
+
+#define RK_CRYPTO_MAX_TRNG_BYTE		32
+
+ #define CRYPTO_READ(dev, offset)		  \
+ 		readl_relaxed(((dev)->reg + (offset)))
+ #define CRYPTO_WRITE(dev, offset, val)	  \
+@@ -209,6 +220,7 @@ struct rk_clks {
+ struct rk_variant {
+ 	int num_clks;
+ 	struct rk_clks rkclks[RK_MAX_CLKS];
+	bool trng;
+ };
+ 
+ struct rk_crypto_info {
+@@ -219,11 +231,15 @@ struct rk_crypto_info {
+ 	struct reset_control		*rst;
+ 	void __iomem			*reg;
+ 	int				irq;
+	struct mutex			lock;
+	struct hwrng			hwrng;
+ 	const struct rk_variant *variant;
+ 	unsigned long nreq;
+ 	struct crypto_engine *engine;
+ 	struct completion complete;
+ 	int status;
+	unsigned long hwrng_stat_req;
+	unsigned long hwrng_stat_bytes;
+ };
+ 
+ /* the private variable of hash */
+@@ -283,3 +299,5 @@ extern struct rk_crypto_tmp rk_ahash_md5;
+ 
+ struct rk_crypto_info *get_rk_crypto(void);
+ #endif
+int rk3288_hwrng_register(struct rk_crypto_info *rk);
+void rk3288_hwrng_unregister(struct rk_crypto_info *rk);
+diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c
+index 111111111111..222222222222 100644
+--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c
+++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c
+@@ -298,6 +298,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq)
+ 		goto theend;
+ 	}
+ 
+	mutex_lock(&rkc->lock);
+ 	rk_ahash_reg_init(areq, rkc);
+ 
+ 	while (sg) {
+@@ -332,6 +333,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq)
+ 	}
+ 
+ theend:
+	mutex_unlock(&rkc->lock);
+ 	pm_runtime_put_autosuspend(rkc->dev);
+ 
+ 	rk_hash_unprepare(engine, breq);
+diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
+index 111111111111..222222222222 100644
+--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
+++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
+@@ -363,6 +363,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req)
+ 			}
+ 		}
+ 		err = 0;
+		mutex_unlock(&rkc->lock);
+ 		rk_cipher_hw_init(rkc, areq);
+ 		if (ivsize) {
+ 			if (ivsize == DES_BLOCK_SIZE)
+@@ -378,6 +379,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req)
+ 		crypto_dma_start(rkc, sgs, sgd, todo / 4);
+ 		wait_for_completion_interruptible_timeout(&rkc->complete,
+ 							  msecs_to_jiffies(2000));
+		mutex_unlock(&rkc->lock);
+ 		if (!rkc->status) {
+ 			dev_err(rkc->dev, "DMA timeout\n");
+ 			err = -EFAULT;
+diff --git a/drivers/crypto/rockchip/rk3288_crypto_trng.c b/drivers/crypto/rockchip/rk3288_crypto_trng.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
+++ b/drivers/crypto/rockchip/rk3288_crypto_trng.c
+@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rk3288_crypto_trng.c - hardware cryptographic offloader for rockchip
+ *
+ * Copyright (C) 2022-2023 Corentin Labbe <clabbe@baylibre.com>
+ *
+ * This file handle the TRNG
+ */
+#include "rk3288_crypto.h"
+#include <linux/hw_random.h>
+#include <linux/iopoll.h>
+#include <linux/pm_runtime.h>
+
+static int rk3288_trng_read(struct hwrng *hwrng, void *data, size_t max, bool wait)
+{
+	struct rk_crypto_info *rk;
+	unsigned int todo;
+	int err = 0;
+	int i;
+	u32 v;
+
+	rk = container_of(hwrng, struct rk_crypto_info, hwrng);
+
+	todo = min_t(size_t, max, RK_CRYPTO_MAX_TRNG_BYTE);
+
+#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG
+	rk->hwrng_stat_req++;
+	rk->hwrng_stat_bytes += todo;
+#endif
+
+	err = pm_runtime_resume_and_get(rk->dev);
+	if (err < 0)
+		goto err_pm;
+
+	mutex_lock(&rk->lock);
+
+#define HIWORD_UPDATE(val, mask, shift) \
+			((val) << (shift) | (mask) << ((shift) + 16))
+	v = RK_CRYPTO_OSC_ENABLE | RK_CRYPTO_RNG_SAMPLE;
+	CRYPTO_WRITE(rk, RK_CRYPTO_TRNG_CTRL, v);
+
+	v = HIWORD_UPDATE(RK_CRYPTO_TRNG_START, RK_CRYPTO_TRNG_START, 0);
+	CRYPTO_WRITE(rk, RK_CRYPTO_CTRL, v);
+	wmb();
+
+	err = readl_poll_timeout(rk->reg + RK_CRYPTO_CTRL, v,
+				 !(v & RK_CRYPTO_TRNG_START),
+				 100, 2000);
+	if (err) {
+		dev_err(rk->dev, "HWRNG read timeout");
+		goto readfail;
+	}
+
+	for (i = 0; i < todo / 4; i++) {
+		v = readl(rk->reg + RK_CRYPTO_TRNG_DOUT_0 + i * 4);
+		put_unaligned_le32(v, data + i * 4);
+	}
+
+	err = todo;
+
+	v = HIWORD_UPDATE(0, RK_CRYPTO_TRNG_START, 0);
+	CRYPTO_WRITE(rk, RK_CRYPTO_CTRL, v);
+
+readfail:
+	mutex_unlock(&rk->lock);
+
+	pm_runtime_put(rk->dev);
+
+err_pm:
+	return err;
+}
+
+int rk3288_hwrng_register(struct rk_crypto_info *rk)
+{
+	int ret;
+
+	dev_info(rk->dev, "Register TRNG with sample=%d\n", RK_CRYPTO_RNG_SAMPLE);
+
+	rk->hwrng.name = "Rockchip rk3288 TRNG";
+	rk->hwrng.read = rk3288_trng_read;
+	rk->hwrng.quality = 300;
+
+	ret = hwrng_register(&rk->hwrng);
+	if (ret)
+		dev_err(rk->dev, "Fail to register the TRNG\n");
+	return ret;
+}
+
+void rk3288_hwrng_unregister(struct rk_crypto_info *rk)
+{
+	hwrng_unregister(&rk->hwrng);
+}
+-- 
+Armbian
+
--- a/_build/patch/general-disable-mtu-validation.patch
+++ b/_build/patch/general-disable-mtu-validation.patch
@@ -0,0 +1,51 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Wed, 21 Jul 2021 20:59:39 +0000
+Subject: Disable MTU validation
+
+This patch reverts: https://github.com/torvalds/linux/commit/eaf4fac478077d4ed57cbca2c044c4b58a96bd98
+
+It works around following issues:
+ - no way to change MTU (tx_fifo_size is reported as 0 for Rockchip's dwmac)
+
+Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
+Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ----------
+ 1 file changed, 12 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+index 111111111111..222222222222 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -5846,27 +5846,15 @@ static void stmmac_set_rx_mode(struct net_device *dev)
+ static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
+ {
+ 	struct stmmac_priv *priv = netdev_priv(dev);
+-	int txfifosz = priv->plat->tx_fifo_size;
+ 	struct stmmac_dma_conf *dma_conf;
+ 	const int mtu = new_mtu;
+ 	int ret;
+ 
+-	if (txfifosz == 0)
+-		txfifosz = priv->dma_cap.tx_fifo_size;
+-
+-	txfifosz /= priv->plat->tx_queues_to_use;
+-
+ 	if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
+ 		netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
+ 		return -EINVAL;
+ 	}
+ 
+-	new_mtu = STMMAC_ALIGN(new_mtu);
+-
+-	/* If condition true, FIFO is too small or MTU too large */
+-	if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
+-		return -EINVAL;
+-
+ 	if (netif_running(dev)) {
+ 		netdev_dbg(priv->dev, "restarting interface to change its MTU\n");
+ 		/* Try to allocate the new DMA conf with the new mtu */
+-- 
+Armbian
+
--- a/_build/patch/general-drm-rockchip-Set-dma-mask-to-64-bit.patch
+++ b/_build/patch/general-drm-rockchip-Set-dma-mask-to-64-bit.patch
@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: SuperKali <hello@superkali.me>
+Date: Fri, 7 Mar 2025 15:06:42 +0000
+Subject: drm/rockchip: Set dma mask to 64 bit
+
+The vop mmu support translate physical address upper 4 GB to iova
+below 4 GB. So set dma mask to 64 bit to indicate we support address
+> 4GB.
+
+This can avoid warnging message like this on some boards with DDR
+> 4 GB:
+
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 130 (slots)
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 0 (slots)
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 130 (slots)
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 130 (slots)
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 0 (slots)
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+@@ -472,7 +472,9 @@ static int rockchip_drm_platform_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
+-	return 0;
+	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
+
+	return ret;
+ }
+ 
+ static void rockchip_drm_platform_remove(struct platform_device *pdev)
+-- 
+Armbian
+
--- a/_build/patch/general-fix-es8316-kernel-panic.patch
+++ b/_build/patch/general-fix-es8316-kernel-panic.patch
@@ -0,0 +1,105 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Yannick Adam <yannick.adam@gmail.com>
+Date: Tue, 14 Apr 2020 17:15:09 +0200
+Subject: [ARCHEOLOGY] Enable es8316 on RockPi4 (#1885)
+
+> X-Git-Archeology: - Revision 454038a50d1d24e636626213ad65b3463d632aa0: https://github.com/armbian/build/commit/454038a50d1d24e636626213ad65b3463d632aa0
+> X-Git-Archeology:   Date: Tue, 14 Apr 2020 17:15:09 +0200
+> X-Git-Archeology:   From: Yannick Adam <yannick.adam@gmail.com>
+> X-Git-Archeology:   Subject: Enable es8316 on RockPi4 (#1885)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision bd486c75623e75bdf2bdcaf09dc5a0affe9706c1: https://github.com/armbian/build/commit/bd486c75623e75bdf2bdcaf09dc5a0affe9706c1
+> X-Git-Archeology:   Date: Tue, 14 Apr 2020 20:14:24 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Enable es8316 on RockPi4 for Rockchip64 current too https://github.com/armbian/build/pull/1885
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
+> X-Git-Archeology:   Date: Tue, 11 Jan 2022 15:26:11 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel edge to 5.16 (#3387)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41
+> X-Git-Archeology:   Date: Sun, 20 Mar 2022 22:58:21 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: Adding Pine64 Quartz64a as WIP target (#3539)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c
+> X-Git-Archeology:   Date: Sun, 24 Apr 2022 22:33:47 +0200
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel media edge to 5.17 (#3704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ sound/soc/codecs/es8316.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c
+index 111111111111..222222222222 100644
+--- a/sound/soc/codecs/es8316.c
+++ b/sound/soc/codecs/es8316.c
+@@ -732,7 +732,7 @@ static void es8316_disable_jack_detect(struct snd_soc_component *component)
+ 	snd_soc_component_update_bits(component, ES8316_GPIO_DEBOUNCE,
+ 				      ES8316_GPIO_ENABLE_INTERRUPT, 0);
+ 
+-	if (es8316->jack->status & SND_JACK_MICROPHONE) {
+	if (es8316->jack && (es8316->jack->status & SND_JACK_MICROPHONE)) {
+ 		es8316_disable_micbias_for_mic_gnd_short_detect(component);
+ 		snd_soc_jack_report(es8316->jack, 0, SND_JACK_BTN_0);
+ 	}
+-- 
+Armbian
+
--- a/_build/patch/general-fix-mmc-signal-voltage-before-reboot.patch
+++ b/_build/patch/general-fix-mmc-signal-voltage-before-reboot.patch
@@ -0,0 +1,46 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 17 Feb 2019 22:14:38 +0000
+Subject: mmc: core: set initial signal voltage on power off
+
+Some boards have SD card connectors where the power rail cannot be switched
+off by the driver. If the card has not been power cycled, it may still be
+using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
+will fail to boot from a UHS card that continue to use 1.8V signaling.
+
+Set initial signal voltage in mmc_power_off() to allow re-boot to function.
+
+This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
+same issue have been seen on some Rockchip RK3399 boards.
+
+I am sending this as a RFC because I have no insights into SD/MMC subsystem,
+this change fix a re-boot issue on my boards and does not break emmc/sdio.
+Is this an acceptable workaround? Any advice is appreciated.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/mmc/core/core.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
+index 111111111111..222222222222 100644
+--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
+@@ -1373,6 +1373,14 @@ void mmc_power_off(struct mmc_host *host)
+ 	if (host->ios.power_mode == MMC_POWER_OFF)
+ 		return;
+ 
+	mmc_set_initial_signal_voltage(host);
+
+	/*
+	 * This delay should be sufficient to allow the power supply
+	 * to reach the minimum voltage.
+	 */
+	mmc_delay(host->ios.power_delay_ms);
+
+ 	mmc_pwrseq_power_off(host);
+ 
+ 	host->ios.clock = 0;
+-- 
+Armbian
+
--- a/_build/patch/general-hdmi-clock-fixes.patch
+++ b/_build/patch/general-hdmi-clock-fixes.patch
@@ -0,0 +1,257 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 6 Apr 2024 15:40:30 +0200
+Subject: hdmi timing core changes and fixes
+
+---
+ drivers/clk/rockchip/clk-rk3399.c           | 49 ++++++++--
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c   | 12 +--
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 42 ++++++++
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  7 ++
+ 4 files changed, 97 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
+index 111111111111..222222222222 100644
+--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
+@@ -105,6 +105,39 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
+ 	{ /* sentinel */ },
+ };
+ 
+static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
+	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+	RK3036_PLL_RATE( 594000000, 1, 74, 3, 1, 0,  4194304),  /* vco = 1782000000  fout = 594000000 */
+	RK3036_PLL_RATE( 593406592, 1, 74, 3, 1, 0,  2949838),  /* vco = 1780219777  fout = 593406592.36908 */
+	RK3036_PLL_RATE( 319750000, 1, 79, 6, 1, 0, 15728640),  /* vco = 1918500000  fout = 319750000 */
+	RK3036_PLL_RATE( 297000000, 1, 74, 6, 1, 0,  4194304),  /* vco = 1782000000  fout = 297000000 */
+	RK3036_PLL_RATE( 296703296, 1, 74, 6, 1, 0,  2949838),  /* vco = 1780219777  fout = 296703296.18454 */
+	RK3036_PLL_RATE( 241500000, 1, 60, 6, 1, 0,  6291456),  /* vco = 1449000000  fout = 241500000 */
+	RK3036_PLL_RATE( 162000000, 1, 67, 5, 2, 0,  8388608),  /* vco = 1620000000  fout = 162000000 */
+	RK3036_PLL_RATE( 148500000, 1, 74, 6, 2, 0,  4194304),  /* vco = 1782000000  fout = 148500000*/
+	RK3036_PLL_RATE( 148351648, 1, 74, 6, 2, 0,  2949838),  /* vco = 1780219777  fout = 148351648.09227 */
+	RK3036_PLL_RATE( 136750000, 1, 68, 2, 6, 0,  6291456),  /* vco = 1641000000  fout = 136750000 */
+	RK3036_PLL_RATE( 135000000, 1, 56, 5, 2, 0,  4194304),  /* vco = 1350000000  fout = 135000000 */
+	RK3036_PLL_RATE( 119000000, 1, 59, 6, 2, 0,  8388608),  /* vco = 1428000000  fout = 119000000 */
+	RK3036_PLL_RATE( 108000000, 1, 63, 7, 2, 1,        0),  /* vco = 1512000000  fout = 108000000 */
+	RK3036_PLL_RATE( 106500000, 1, 62, 7, 2, 0,  2097152),  /* vco = 1491000000  fout = 106500000 */
+	RK3036_PLL_RATE(  88750000, 1, 55, 5, 3, 0,  7864320),  /* vco = 1331250000  fout = 88750000 */
+	RK3036_PLL_RATE(  85500000, 1, 57, 4, 4, 1,        0),  /* vco = 1368000000  fout = 85500000 */
+	RK3036_PLL_RATE(  78750000, 1, 59, 6, 3, 0,  1048576),  /* vco = 1417500000  fout = 78750000 */
+	RK3036_PLL_RATE(  74250000, 1, 74, 6, 4, 0,  4194304),  /* vco = 1782000000  fout = 74250000 */
+	RK3036_PLL_RATE(  74175824, 1, 74, 6, 4, 0,  2949838),  /* vco = 1780219777  fout = 74175824.046135 */
+	RK3036_PLL_RATE(  71000000, 1, 71, 6, 4, 1,        0),  /* vco = 1704000000  fout = 71000000 */
+	RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 0,        0),  /* vco = 1560000000  fout = 65000000 */
+	RK3036_PLL_RATE(  59340659, 1, 59, 6, 4, 0,  5715310),  /* vco = 1424175816  fout = 59340659.022331 */
+	RK3036_PLL_RATE(  54000000, 1, 63, 7, 4, 1,        0),  /* vco = 1512000000  fout = 54000000 */
+	RK3036_PLL_RATE(  49500000, 1, 72, 5, 7, 0,  3145728),  /* vco = 1732500000  fout = 49500000 */
+	RK3036_PLL_RATE(  40000000, 1, 70, 7, 6, 1,        0),  /* vco = 1680000000  fout = 40000000 */
+	RK3036_PLL_RATE(  31500000, 1, 55, 7, 6, 0,  2097152),  /* vco = 1323000000  fout = 31500000 */
+	RK3036_PLL_RATE(  27000000, 1, 55, 7, 7, 0,  2097152),  /* vco = 1323000000  fout = 27000000 */
+	RK3036_PLL_RATE(  26973026, 1, 55, 7, 7, 0,  1173214),  /* vco = 1321678296  fout = 26973026.450799 */
+	{ /* sentinel */ },
+};
+
+ /* CRU parents */
+ PNAME(mux_pll_p)				= { "xin24m", "xin32k" };
+ 
+@@ -123,7 +156,7 @@ PNAME(mux_ddrclk_p)				= { "clk_ddrc_lpll_src",
+ PNAME(mux_aclk_cci_p)				= { "cpll_aclk_cci_src",
+ 						    "gpll_aclk_cci_src",
+ 						    "npll_aclk_cci_src",
+-						    "vpll_aclk_cci_src" };
+						    "prevent:vpll" };
+ PNAME(mux_cci_trace_p)				= { "cpll_cci_trace",
+ 						    "gpll_cci_trace" };
+ PNAME(mux_cs_p)					= { "cpll_cs", "gpll_cs",
+@@ -149,10 +182,12 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)	= { "cpll", "gpll", "npll",
+ PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
+ 						    "ppll", "upll", "xin24m" };
+ 
+-PNAME(mux_pll_src_vpll_cpll_gpll_p)		= { "vpll", "cpll", "gpll" };
+-PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)	= { "vpll", "cpll", "gpll",
+PNAME(mux_pll_src_vpll_cpll_gpll_p)		= { "prevent:vpll", "cpll", "gpll" };
+PNAME(vop0_mux_pll_src_vpll_cpll_gpll_p)	= { "vpll", "prevent:cpll", "prevent:gpll" };
+
+PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)	= { "prevent:vpll", "cpll", "gpll",
+ 						    "npll" };
+-PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)		= { "vpll", "cpll", "gpll",
+PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)		= { "prevent:vpll", "cpll", "gpll",
+ 						    "xin24m" };
+ 
+ PNAME(mux_dclk_vop0_p)			= { "dclk_vop0_div",
+@@ -229,7 +264,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
+ 	[npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, RK3399_PLL_CON(40),
+ 		     RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
+ 	[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, RK3399_PLL_CON(48),
+-		     RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
+		     RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
+ };
+ 
+ static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
+@@ -279,7 +314,7 @@ static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
+ 			RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
+ 
+ static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
+-	MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
+	MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ 			RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
+ 
+ static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
+@@ -1162,7 +1197,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ 	GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
+ 			RK3399_CLKGATE_CON(28), 0, GFLAGS),
+ 
+-	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
+	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", vop0_mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ 			RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ 			RK3399_CLKGATE_CON(10), 12, GFLAGS),
+ 
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -70,15 +70,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
+ };
+ 
+ static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
+-	{ 0x2591, 0x1322, 0x074b, 0x0000 },
+-	{ 0x6535, 0x2000, 0x7acc, 0x0200 },
+-	{ 0x6acd, 0x7534, 0x2000, 0x0200 }
+	{ 0x2040, 0x1080, 0x0640, 0x0040 },
+	{ 0xe880, 0x1c00, 0xfb80, 0x0200 },
+	{ 0xed80, 0xf680, 0x1c00, 0x0200 }
+ };
+ 
+ static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
+-	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
+-	{ 0x62f0, 0x2000, 0x7d11, 0x0200 },
+-	{ 0x6756, 0x78ab, 0x2000, 0x0200 }
+	{ 0x2740, 0x0bc0, 0x0400, 0x0040 },
+	{ 0xe680, 0x1c00, 0xfd80, 0x0200 },
+	{ 0xea40, 0xf980, 0x1c00, 0x0200 }
+ };
+ 
+ static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -177,6 +177,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	}
+ };
+ 
+static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = {
+	{
+		30666000, {
+			{ 0x00b7, 0x0000 },
+			{ 0x2157, 0x0000 },
+			{ 0x40f7, 0x0000 },
+		},
+	},  {
+		92000000, {
+			{ 0x00b7, 0x0000 },
+			{ 0x2143, 0x0001 },
+			{ 0x40a3, 0x0001 },
+		},
+	},  {
+		184000000, {
+			{ 0x0073, 0x0001 },
+			{ 0x2146, 0x0002 },
+			{ 0x4062, 0x0002 },
+		},
+	},  {
+		340000000, {
+			{ 0x0052, 0x0003 },
+			{ 0x214d, 0x0003 },
+			{ 0x4065, 0x0003 },
+		},
+	},  {
+		600000000, {
+			{ 0x0041, 0x0003 },
+			{ 0x3b4d, 0x0003 },
+			{ 0x5a65, 0x0003 },
+		},
+	},  {
+		~0UL, {
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
+			{ 0x0000, 0x0000 },
+		},
+	}
+};
+
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ 	/*      pixelclk    bpp8    bpp10   bpp12 */
+ 	{
+@@ -338,6 +378,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
+ 
+ 	dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);
+ 
+	dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);
+
+ 	return phy_power_on(hdmi->phy);
+ }
+ 
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -765,6 +765,7 @@ static const struct vop_intr rk3288_vop_intr = {
+ static const struct vop_data rk3288_vop = {
+ 	.version = VOP_VERSION(3, 1),
+ 	.feature = VOP_FEATURE_OUTPUT_RGB10,
+	.max_output = { 3840, 2160 },
+ 	.intr = &rk3288_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+@@ -872,6 +873,7 @@ static const struct vop_misc rk3368_misc = {
+ 
+ static const struct vop_data rk3368_vop = {
+ 	.version = VOP_VERSION(3, 2),
+	.max_output = { 4096, 2160 },
+ 	.intr = &rk3368_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+@@ -894,6 +896,7 @@ static const struct vop_intr rk3366_vop_intr = {
+ 
+ static const struct vop_data rk3366_vop = {
+ 	.version = VOP_VERSION(3, 4),
+	.max_output = { 4096, 2160 },
+ 	.intr = &rk3366_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+@@ -1047,6 +1050,7 @@ static const struct vop_afbc rk3399_vop_afbc = {
+ static const struct vop_data rk3399_vop_big = {
+ 	.version = VOP_VERSION(3, 5),
+ 	.feature = VOP_FEATURE_OUTPUT_RGB10,
+	.max_output = { 4096, 2160 },
+ 	.intr = &rk3366_vop_intr,
+ 	.common = &rk3399_common,
+ 	.modeset = &rk3288_modeset,
+@@ -1075,6 +1079,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = {
+ 
+ static const struct vop_data rk3399_vop_lit = {
+ 	.version = VOP_VERSION(3, 6),
+	.max_output = { 2560, 1600 },
+ 	.intr = &rk3366_vop_intr,
+ 	.common = &rk3399_common,
+ 	.modeset = &rk3288_modeset,
+@@ -1097,6 +1102,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = {
+ static const struct vop_data rk3228_vop = {
+ 	.version = VOP_VERSION(3, 7),
+ 	.feature = VOP_FEATURE_OUTPUT_RGB10,
+	.max_output = { 4096, 2160 },
+ 	.intr = &rk3366_vop_intr,
+ 	.common = &rk3288_common,
+ 	.modeset = &rk3288_modeset,
+@@ -1169,6 +1175,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = {
+ static const struct vop_data rk3328_vop = {
+ 	.version = VOP_VERSION(3, 8),
+ 	.feature = VOP_FEATURE_OUTPUT_RGB10,
+	.max_output = { 4096, 2160 },
+ 	.intr = &rk3328_vop_intr,
+ 	.common = &rk3328_common,
+ 	.modeset = &rk3328_modeset,
+-- 
+Armbian
+
--- a/_build/patch/general-increase-spdif-dma-burst.patch
+++ b/_build/patch/general-increase-spdif-dma-burst.patch
@@ -0,0 +1,25 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 12 Jan 2025 12:39:03 +0100
+Subject: rockchip: increase SPDIF max burst value to maximum
+
+---
+ sound/soc/rockchip/rockchip_spdif.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c
+index 111111111111..222222222222 100644
+--- a/sound/soc/rockchip/rockchip_spdif.c
+++ b/sound/soc/rockchip/rockchip_spdif.c
+@@ -329,7 +329,7 @@ static int rk_spdif_probe(struct platform_device *pdev)
+ 
+ 	spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
+ 	spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+-	spdif->playback_dma_data.maxburst = 4;
+	spdif->playback_dma_data.maxburst = 8;
+ 
+ 	spdif->dev = &pdev->dev;
+ 	dev_set_drvdata(&pdev->dev, spdif);
+-- 
+Armbian
+
--- a/_build/patch/general-increasing_DMA_block_memory_allocation_to_2048.patch
+++ b/_build/patch/general-increasing_DMA_block_memory_allocation_to_2048.patch
@@ -0,0 +1,140 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Mon, 21 Aug 2017 08:54:53 +0200
+Subject: [ARCHEOLOGY] Increasing DMA block memory allocation to 2048k on all
+ relevant kernels.
+
+> X-Git-Archeology: > recovered message: > https://forum.armbian.com/index.php?/topic/4811-uas-mainline-kernel-coherent-pool-memory-size
+> X-Git-Archeology: - Revision 908bb199ec2defd77f7f05d2016980abf100d627: https://github.com/armbian/build/commit/908bb199ec2defd77f7f05d2016980abf100d627
+> X-Git-Archeology:   Date: Mon, 21 Aug 2017 08:54:53 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Increasing DMA block memory allocation to 2048k on all relevant kernels.
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision a3cf7b74858e1f862db8ca238bd44f6406be6662: https://github.com/armbian/build/commit/a3cf7b74858e1f862db8ca238bd44f6406be6662
+> X-Git-Archeology:   Date: Mon, 21 Aug 2017 17:52:29 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Revert "Increasing DMA block memory allocation to 2048k on all relevant kernels."
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 2be21aad5dc965b3bc67e136a1e1170119d60f74: https://github.com/armbian/build/commit/2be21aad5dc965b3bc67e136a1e1170119d60f74
+> X-Git-Archeology:   Date: Mon, 21 Aug 2017 17:52:48 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Increasing DMA block memory allocation to 2048k on all relevant kernels. https://forum.armbian.com/index.php?/topic/4811-uas-mainline-kernel-coherent-pool-memory-size
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision b3d2bd4864d89ce032344051e6ced2ba9371084b: https://github.com/armbian/build/commit/b3d2bd4864d89ce032344051e6ced2ba9371084b
+> X-Git-Archeology:   Date: Wed, 30 Aug 2017 05:42:08 +0000
+> X-Git-Archeology:   From: Tonymac32 <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: Meson64 Dev increase DMA block memory allocation
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 2c59bb9934b749b5df74d4134cd393dc24fd5160: https://github.com/armbian/build/commit/2c59bb9934b749b5df74d4134cd393dc24fd5160
+> X-Git-Archeology:   Date: Mon, 18 Sep 2017 12:06:30 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Lepotato. Added NEXT, added patches from C2 NEXT, au, config update, removed deprecated patches, ...
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 13e94e58f04be27db51d18b7dac1d15a1864b79e: https://github.com/armbian/build/commit/13e94e58f04be27db51d18b7dac1d15a1864b79e
+> X-Git-Archeology:   Date: Fri, 27 Oct 2017 16:14:21 +0300
+> X-Git-Archeology:   From: zador-blood-stained <zador-blood-stained@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Remove random executable bits from patch files
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 2c08ec8f5a210de35f9482f482ac01ea15381792: https://github.com/armbian/build/commit/2c08ec8f5a210de35f9482f482ac01ea15381792
+> X-Git-Archeology:   Date: Thu, 24 May 2018 13:32:29 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Merge sunxi family into stable
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 7d2f3af08f23049c91c88eec5062613bbfbc85d4: https://github.com/armbian/build/commit/7d2f3af08f23049c91c88eec5062613bbfbc85d4
+> X-Git-Archeology:   Date: Thu, 24 May 2018 15:44:15 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Merging Rockchip family
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 99a34c7be1e342247a981f99c7930ee73c144f3e: https://github.com/armbian/build/commit/99a34c7be1e342247a981f99c7930ee73c144f3e
+> X-Git-Archeology:   Date: Tue, 26 Jun 2018 12:47:49 +0000
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Move Odroid C2 from 4.14.y to 4.16.y, added patch for ethernet, DEV to master, both tested ... not perfect but in a better condition.
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision fcb85f17675990514d8fadc905e6ccc3bded7138: https://github.com/armbian/build/commit/fcb85f17675990514d8fadc905e6ccc3bded7138
+> X-Git-Archeology:   Date: Thu, 28 Jun 2018 08:27:08 +0000
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: Major Amlogic RFC and cleanup
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision c57ebd663cf1b15ad193d4a761f9c044ba3b2acf: https://github.com/armbian/build/commit/c57ebd663cf1b15ad193d4a761f9c044ba3b2acf
+> X-Git-Archeology:   Date: Tue, 17 Jul 2018 16:11:07 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: - attach Odroid XU4 4.14.y back to Hardkernel kernel branch
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision a26ccdee627f1fa27b3285e3840434cddb5aae62: https://github.com/armbian/build/commit/a26ccdee627f1fa27b3285e3840434cddb5aae62
+> X-Git-Archeology:   Date: Wed, 07 Nov 2018 11:11:51 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: [odroid xu4] Drop kernel 3.10.y, default -> offical 4.14.y, next = vanilla 4.19.y http://ix.io/1rcZ & dev = n/a
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision a156fddf8f5bb5a6ac28ffc528ba0ec28ff9df81: https://github.com/armbian/build/commit/a156fddf8f5bb5a6ac28ffc528ba0ec28ff9df81
+> X-Git-Archeology:   Date: Fri, 18 Jan 2019 20:10:35 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: [ odroidxu4 ] Reverting NEXT back to stock 4.14.y due to many troubles, DEV = 4.19.y
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 79c1c2781915c59bd24576af92b9dbe57da24fac: https://github.com/armbian/build/commit/79c1c2781915c59bd24576af92b9dbe57da24fac
+> X-Git-Archeology:   Date: Fri, 17 May 2019 10:46:57 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: [ odroidxu4 dev ] Move to 5.1.y
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3
+> X-Git-Archeology:   Date: Tue, 19 Nov 2019 23:25:39 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Remove K<4, change branches, new features (#1586)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5: https://github.com/armbian/build/commit/4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5
+> X-Git-Archeology:   Date: Wed, 02 Sep 2020 23:22:09 +0200
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switched rockchip64 curent to kernel 5.8.y (#2175)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e4d413b9166e3633b40fb23382fb1045b9d0e315: https://github.com/armbian/build/commit/e4d413b9166e3633b40fb23382fb1045b9d0e315
+> X-Git-Archeology:   Date: Tue, 26 Mar 2024 13:46:35 +0100
+> X-Git-Archeology:   From: Paolo Sabatino <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: bump edge kernel to 6.8
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 69ca2492628b2aae217c33fde921b3840851eb14: https://github.com/armbian/build/commit/69ca2492628b2aae217c33fde921b3840851eb14
+> X-Git-Archeology:   Date: Wed, 05 Jun 2024 22:18:24 +0200
+> X-Git-Archeology:   From: Paolo Sabatino <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: bump edge kernel to 6.9
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 4ae0a958146810117050d0dbd359b99691a0fa0c: https://github.com/armbian/build/commit/4ae0a958146810117050d0dbd359b99691a0fa0c
+> X-Git-Archeology:   Date: Mon, 22 Jul 2024 19:17:52 +0200
+> X-Git-Archeology:   From: Paolo Sabatino <paolo.sabatino@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64: bump edge kernel to 6.10
+> X-Git-Archeology:
+---
+ kernel/dma/pool.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/dma/pool.c b/kernel/dma/pool.c
+index 111111111111..222222222222 100644
+--- a/kernel/dma/pool.c
+++ b/kernel/dma/pool.c
+@@ -189,13 +189,11 @@ static int __init dma_atomic_pool_init(void)
+ 	int ret = 0;
+ 
+ 	/*
+-	 * If coherent_pool was not used on the command line, default the pool
+-	 * sizes to 128KB per 1GB of memory, min 128KB, max MAX_PAGE_ORDER.
+	 * Always use 2MiB as default pool size.
+	 * See: https://forum.armbian.com/topic/4811-uas-mainline-kernel-coherent-pool-memory-size/
+ 	 */
+ 	if (!atomic_pool_size) {
+-		unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
+-		pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
+-		atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
+		atomic_pool_size = SZ_2M;
+ 	}
+ 	INIT_WORK(&atomic_pool_work, atomic_pool_work_fn);
+ 
+-- 
+Armbian
+
--- a/_build/patch/general-pl330-01-fix-periodic-transfers.patch
+++ b/_build/patch/general-pl330-01-fix-periodic-transfers.patch
@@ -0,0 +1,421 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 12 Jan 2025 12:36:50 +0100
+Subject: pl330: fix dma engine periodic transfers
+
+---
+ drivers/dma/pl330.c | 277 +++++++---
+ 1 file changed, 186 insertions(+), 91 deletions(-)
+
+diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
+index 111111111111..222222222222 100644
+--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
+@@ -239,6 +239,7 @@ enum pl330_byteswap {
+ 
+ #define BYTE_TO_BURST(b, ccr)	((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
+ #define BURST_TO_BYTE(c, ccr)	((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
+#define BYTE_MOD_BURST_LEN(b, ccr)	(((b) / BRST_SIZE(ccr)) % BRST_LEN(ccr))
+ 
+ /*
+  * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
+@@ -455,9 +456,6 @@ struct dma_pl330_chan {
+ 	enum dma_data_direction dir;
+ 	struct dma_slave_config slave_config;
+ 
+-	/* for cyclic capability */
+-	bool cyclic;
+-
+ 	/* for runtime pm tracking */
+ 	bool active;
+ };
+@@ -545,6 +543,10 @@ struct dma_pl330_desc {
+ 	unsigned peri:5;
+ 	/* Hook to attach to DMAC's list of reqs with due callback */
+ 	struct list_head rqd;
+
+	/* For cyclic capability */
+	bool cyclic;
+	size_t num_periods;
+ };
+ 
+ struct _xfer_spec {
+@@ -1368,6 +1370,108 @@ static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
+ 	return off;
+ }
+ 
+static int _period(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
+		   unsigned long bursts, const struct _xfer_spec *pxs, int ev)
+{
+	unsigned int lcnt1, ljmp1;
+	int cyc, off = 0, num_dregs = 0;
+	struct _arg_LPEND lpend;
+	struct pl330_xfer *x = &pxs->desc->px;
+
+	if (bursts > 256) {
+		lcnt1 = 256;
+		cyc = bursts / 256;
+	} else {
+		lcnt1 = bursts;
+		cyc = 1;
+	}
+
+	/* loop1 */
+	off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
+	ljmp1 = off;
+	off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
+	lpend.cond = ALWAYS;
+	lpend.forever = false;
+	lpend.loop = 1;
+	lpend.bjump = off - ljmp1;
+	off += _emit_LPEND(dry_run, &buf[off], &lpend);
+
+	/* remainder */
+	lcnt1 = bursts - (lcnt1 * cyc);
+
+	if (lcnt1) {
+		off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
+		ljmp1 = off;
+		off += _bursts(pl330, dry_run, &buf[off], pxs, 1);
+		lpend.cond = ALWAYS;
+		lpend.forever = false;
+		lpend.loop = 1;
+		lpend.bjump = off - ljmp1;
+		off += _emit_LPEND(dry_run, &buf[off], &lpend);
+	}
+
+	num_dregs = BYTE_MOD_BURST_LEN(x->bytes, pxs->ccr);
+
+	if (num_dregs) {
+		off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
+		off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
+	}
+
+	off += _emit_SEV(dry_run, &buf[off], ev);
+
+	return off;
+}
+
+static inline int _loop_cyclic(struct pl330_dmac *pl330, unsigned int dry_run,
+			       u8 buf[], unsigned long bursts,
+			       const struct _xfer_spec *pxs, int ev)
+{
+	int off, periods, residue, i;
+	unsigned int lcnt0, ljmp0, ljmpfe;
+	struct _arg_LPEND lpend;
+	struct pl330_xfer *x = &pxs->desc->px;
+
+	off = 0;
+	ljmpfe = off;
+	lcnt0 = pxs->desc->num_periods;
+	periods = 1;
+
+	while (lcnt0 > 256) {
+		periods++;
+		lcnt0 = pxs->desc->num_periods / periods;
+	}
+
+	residue = pxs->desc->num_periods % periods;
+
+	/* forever loop */
+	off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
+	off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
+
+	/* loop0 */
+	off += _emit_LP(dry_run, &buf[off], 0,  lcnt0);
+	ljmp0 = off;
+
+	for (i = 0; i < periods; i++)
+		off += _period(pl330, dry_run, &buf[off], bursts, pxs, ev);
+
+	lpend.cond = ALWAYS;
+	lpend.forever = false;
+	lpend.loop = 0;
+	lpend.bjump = off - ljmp0;
+	off += _emit_LPEND(dry_run, &buf[off], &lpend);
+
+	for (i = 0; i < residue; i++)
+		off += _period(pl330, dry_run, &buf[off], bursts, pxs, ev);
+
+	lpend.cond = ALWAYS;
+	lpend.forever = true;
+	lpend.loop = 1;
+	lpend.bjump = off - ljmpfe;
+	off +=  _emit_LPEND(dry_run, &buf[off], &lpend);
+
+	return off;
+}
+
+ static inline int _setup_loops(struct pl330_dmac *pl330,
+ 			       unsigned dry_run, u8 buf[],
+ 			       const struct _xfer_spec *pxs)
+@@ -1407,6 +1511,21 @@ static inline int _setup_xfer(struct pl330_dmac *pl330,
+ 	return off;
+ }
+ 
+static inline int _setup_xfer_cyclic(struct pl330_dmac *pl330,
+				     unsigned int dry_run, u8 buf[],
+				     const struct _xfer_spec *pxs, int ev)
+{
+	struct pl330_xfer *x = &pxs->desc->px;
+	u32 ccr = pxs->ccr;
+	unsigned long bursts = BYTE_TO_BURST(x->bytes, ccr);
+	int off = 0;
+
+	/* Setup Loop(s) */
+	off += _loop_cyclic(pl330, dry_run, &buf[off], bursts, pxs, ev);
+
+	return off;
+}
+
+ /*
+  * A req is a sequence of one or more xfer units.
+  * Returns the number of bytes taken to setup the MC for the req.
+@@ -1424,12 +1543,17 @@ static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
+ 	/* DMAMOV CCR, ccr */
+ 	off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
+ 
+-	off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
+	if (!pxs->desc->cyclic) {
+		off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
+ 
+-	/* DMASEV peripheral/event */
+-	off += _emit_SEV(dry_run, &buf[off], thrd->ev);
+-	/* DMAEND */
+-	off += _emit_END(dry_run, &buf[off]);
+		/* DMASEV peripheral/event */
+		off += _emit_SEV(dry_run, &buf[off], thrd->ev);
+		/* DMAEND */
+		off += _emit_END(dry_run, &buf[off]);
+	} else {
+		off += _setup_xfer_cyclic(pl330, dry_run, &buf[off],
+					  pxs, thrd->ev);
+	}
+ 
+ 	return off;
+ }
+@@ -1703,15 +1827,17 @@ static int pl330_update(struct pl330_dmac *pl330)
+ 
+ 			/* Detach the req */
+ 			descdone = thrd->req[active].desc;
+-			thrd->req[active].desc = NULL;
+-
+-			thrd->req_running = -1;
+-
+-			/* Get going again ASAP */
+-			pl330_start_thread(thrd);
+-
+-			/* For now, just make a list of callbacks to be done */
+-			list_add_tail(&descdone->rqd, &pl330->req_done);
+			if (descdone) {
+				if (!descdone->cyclic) {
+					thrd->req[active].desc = NULL;
+					thrd->req_running = -1;
+					/* Get going again ASAP */
+					pl330_start_thread(thrd);
+				}
+
+				/* For now, just make a list of callbacks to be done */
+				list_add_tail(&descdone->rqd, &pl330->req_done);
+			}
+ 		}
+ 	}
+ 
+@@ -2076,12 +2202,25 @@ static void pl330_tasklet(struct tasklet_struct *t)
+ 	spin_lock_irqsave(&pch->lock, flags);
+ 
+ 	/* Pick up ripe tomatoes */
+-	list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
+	list_for_each_entry_safe(desc, _dt, &pch->work_list, node) {
+ 		if (desc->status == DONE) {
+-			if (!pch->cyclic)
+			if (!desc->cyclic) {
+ 				dma_cookie_complete(&desc->txd);
+-			list_move_tail(&desc->node, &pch->completed_list);
+				list_move_tail(&desc->node, &pch->completed_list);
+			} else {
+				struct dmaengine_desc_callback cb;
+
+				desc->status = BUSY;
+				dmaengine_desc_get_callback(&desc->txd, &cb);
+
+				if (dmaengine_desc_callback_valid(&cb)) {
+					spin_unlock_irqrestore(&pch->lock, flags);
+					dmaengine_desc_callback_invoke(&cb, NULL);
+					spin_lock_irqsave(&pch->lock, flags);
+				}
+			}
+ 		}
+	}
+ 
+ 	/* Try to submit a req imm. next to the last completed cookie */
+ 	fill_queue(pch);
+@@ -2107,20 +2246,8 @@ static void pl330_tasklet(struct tasklet_struct *t)
+ 
+ 		dmaengine_desc_get_callback(&desc->txd, &cb);
+ 
+-		if (pch->cyclic) {
+-			desc->status = PREP;
+-			list_move_tail(&desc->node, &pch->work_list);
+-			if (power_down) {
+-				pch->active = true;
+-				spin_lock(&pch->thread->dmac->lock);
+-				pl330_start_thread(pch->thread);
+-				spin_unlock(&pch->thread->dmac->lock);
+-				power_down = false;
+-			}
+-		} else {
+-			desc->status = FREE;
+-			list_move_tail(&desc->node, &pch->dmac->desc_pool);
+-		}
+		desc->status = FREE;
+		list_move_tail(&desc->node, &pch->dmac->desc_pool);
+ 
+ 		dma_descriptor_unmap(&desc->txd);
+ 
+@@ -2168,7 +2295,6 @@ static int pl330_alloc_chan_resources(struct dma_chan *chan)
+ 	spin_lock_irqsave(&pl330->lock, flags);
+ 
+ 	dma_cookie_init(chan);
+-	pch->cyclic = false;
+ 
+ 	pch->thread = pl330_request_channel(pl330);
+ 	if (!pch->thread) {
+@@ -2367,8 +2493,7 @@ static void pl330_free_chan_resources(struct dma_chan *chan)
+ 	pl330_release_channel(pch->thread);
+ 	pch->thread = NULL;
+ 
+-	if (pch->cyclic)
+-		list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
+	list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
+ 
+ 	spin_unlock_irqrestore(&pl330->lock, flags);
+ 	pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
+@@ -2431,7 +2556,7 @@ pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
+ 
+ 	/* Check in pending list */
+ 	list_for_each_entry(desc, &pch->work_list, node) {
+-		if (desc->status == DONE)
+		if (desc->status == DONE && !desc->cyclic)
+ 			transferred = desc->bytes_requested;
+ 		else if (running && desc == running)
+ 			transferred =
+@@ -2516,10 +2641,7 @@ static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
+ 	/* Assign cookies to all nodes */
+ 	while (!list_empty(&last->node)) {
+ 		desc = list_entry(last->node.next, struct dma_pl330_desc, node);
+-		if (pch->cyclic) {
+-			desc->txd.callback = last->txd.callback;
+-			desc->txd.callback_param = last->txd.callback_param;
+-		}
+
+ 		desc->last = false;
+ 
+ 		dma_cookie_assign(&desc->txd);
+@@ -2622,6 +2744,9 @@ static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
+ 	desc->peri = peri_id ? pch->chan.chan_id : 0;
+ 	desc->rqcfg.pcfg = &pch->dmac->pcfg;
+ 
+	desc->cyclic = false;
+	desc->num_periods = 1;
+
+ 	dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
+ 
+ 	return desc;
+@@ -2685,12 +2810,10 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
+ 		size_t period_len, enum dma_transfer_direction direction,
+ 		unsigned long flags)
+ {
+-	struct dma_pl330_desc *desc = NULL, *first = NULL;
+	struct dma_pl330_desc *desc = NULL;
+ 	struct dma_pl330_chan *pch = to_pchan(chan);
+-	struct pl330_dmac *pl330 = pch->dmac;
+-	unsigned int i;
+-	dma_addr_t dst;
+-	dma_addr_t src;
+	dma_addr_t dst = 0;
+	dma_addr_t src = 0;
+ 
+ 	if (len % period_len != 0)
+ 		return NULL;
+@@ -2706,33 +2829,14 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
+ 	if (!pl330_prep_slave_fifo(pch, direction))
+ 		return NULL;
+ 
+-	for (i = 0; i < len / period_len; i++) {
+-		desc = pl330_get_desc(pch);
+-		if (!desc) {
+-			unsigned long iflags;
+-
+-			dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
+-				__func__, __LINE__);
+-
+-			if (!first)
+-				return NULL;
+-
+-			spin_lock_irqsave(&pl330->pool_lock, iflags);
+-
+-			while (!list_empty(&first->node)) {
+-				desc = list_entry(first->node.next,
+-						struct dma_pl330_desc, node);
+-				list_move_tail(&desc->node, &pl330->desc_pool);
+-			}
+-
+-			list_move_tail(&first->node, &pl330->desc_pool);
+-
+-			spin_unlock_irqrestore(&pl330->pool_lock, iflags);
+-
+-			return NULL;
+-		}
+	desc = pl330_get_desc(pch);
+	if (!desc) {
+		dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
+			__func__, __LINE__);
+		return NULL;
+	}
+ 
+-		switch (direction) {
+	switch (direction) {
+ 		case DMA_MEM_TO_DEV:
+ 			desc->rqcfg.src_inc = 1;
+ 			desc->rqcfg.dst_inc = 0;
+@@ -2746,27 +2850,18 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
+ 			dst = dma_addr;
+ 			break;
+ 		default:
+-			break;
+-		}
+-
+-		desc->rqtype = direction;
+-		desc->rqcfg.brst_size = pch->burst_sz;
+-		desc->rqcfg.brst_len = pch->burst_len;
+-		desc->bytes_requested = period_len;
+-		fill_px(&desc->px, dst, src, period_len);
+-
+-		if (!first)
+-			first = desc;
+-		else
+-			list_add_tail(&desc->node, &first->node);
+-
+-		dma_addr += period_len;
+		break;
+ 	}
+ 
+-	if (!desc)
+-		return NULL;
+	desc->rqtype = direction;
+	desc->rqcfg.brst_size = pch->burst_sz;
+	desc->rqcfg.brst_len = pch->burst_len;
+	desc->bytes_requested = len;
+	fill_px(&desc->px, dst, src, period_len);
+ 
+-	pch->cyclic = true;
+	desc->cyclic = true;
+	desc->num_periods = len / period_len;
+	desc->txd.flags = flags;
+ 
+ 	return &desc->txd;
+ }
+-- 
+Armbian
+
--- a/_build/patch/general-pl330-02-add-support-for-interleaved-transfers.patch
+++ b/_build/patch/general-pl330-02-add-support-for-interleaved-transfers.patch
@@ -0,0 +1,261 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 23 Jan 2025 20:23:50 +0100
+Subject: rockchip/64: pl330 - add support for interleaved transfers
+
+original source: https://patchwork.kernel.org/project/linux-rockchip/cover/1712150304-60832-1-git-send-email-sugar.zhang@rock-chips.com/
+---
+ drivers/dma/pl330.c       | 168 +++++++++-
+ include/linux/dmaengine.h |   1 +
+ 2 files changed, 163 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
+index 111111111111..222222222222 100644
+--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
+@@ -543,6 +543,8 @@ struct dma_pl330_desc {
+ 	unsigned peri:5;
+ 	/* Hook to attach to DMAC's list of reqs with due callback */
+ 	struct list_head rqd;
+	/* interleaved size */
+	struct data_chunk sgl;
+ 
+ 	/* For cyclic capability */
+ 	bool cyclic;
+@@ -579,6 +581,22 @@ static inline u32 get_revision(u32 periph_id)
+ 	return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
+ }
+ 
+static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
+		enum pl330_dst da, u16 val)
+{
+	if (dry_run)
+		return SZ_DMAADDH;
+
+	buf[0] = CMD_DMAADDH;
+	buf[0] |= (da << 1);
+	*((__le16 *)&buf[1]) = cpu_to_le16(val);
+
+	PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
+		da == 1 ? "DA" : "SA", val);
+
+	return SZ_DMAADDH;
+}
+
+ static inline u32 _emit_END(unsigned dry_run, u8 buf[])
+ {
+ 	if (dry_run)
+@@ -1189,7 +1207,7 @@ static inline int _ldst_peripheral(struct pl330_dmac *pl330,
+ 				 const struct _xfer_spec *pxs, int cyc,
+ 				 enum pl330_cond cond)
+ {
+-	int off = 0;
+	int off = 0, i = 0, burstn = 1;
+ 
+ 	/*
+ 	 * do FLUSHP at beginning to clear any stale dma requests before the
+@@ -1197,12 +1215,36 @@ static inline int _ldst_peripheral(struct pl330_dmac *pl330,
+ 	 */
+ 	if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
+ 		off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
+
+	if (pxs->desc->sgl.size) {
+		WARN_ON(BYTE_MOD_BURST_LEN(pxs->desc->sgl.size, pxs->ccr));
+		burstn = BYTE_TO_BURST(pxs->desc->sgl.size, pxs->ccr);
+	}
+
+ 	while (cyc--) {
+-		off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
+-		off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
+-			pxs->desc->peri);
+-		off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
+-			pxs->desc->peri);
+		for (i = 0; i < burstn; i++) {
+			off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
+			off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
+				pxs->desc->peri);
+			off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
+				pxs->desc->peri);
+		}
+
+		switch (pxs->desc->rqtype) {
+		case DMA_DEV_TO_MEM:
+			if (pxs->desc->sgl.dst_icg)
+				off += _emit_ADDH(dry_run, &buf[off], DST,
+						  pxs->desc->sgl.dst_icg);
+			break;
+		case DMA_MEM_TO_DEV:
+			if (pxs->desc->sgl.src_icg)
+				off += _emit_ADDH(dry_run, &buf[off], SRC,
+						  pxs->desc->sgl.src_icg);
+			break;
+		default:
+			WARN_ON(1);
+			break;
+		}
+ 	}
+ 
+ 	return off;
+@@ -1483,6 +1525,9 @@ static inline int _setup_loops(struct pl330_dmac *pl330,
+ 		BRST_SIZE(ccr);
+ 	int off = 0;
+ 
+	if (pxs->desc->sgl.size)
+		bursts = x->bytes / pxs->desc->sgl.size;
+
+ 	while (bursts) {
+ 		c = bursts;
+ 		off += _loop(pl330, dry_run, &buf[off], &c, pxs);
+@@ -2743,6 +2788,9 @@ static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
+ 
+ 	desc->peri = peri_id ? pch->chan.chan_id : 0;
+ 	desc->rqcfg.pcfg = &pch->dmac->pcfg;
+	desc->sgl.size = 0;
+	desc->sgl.src_icg = 0;
+	desc->sgl.dst_icg = 0;
+ 
+ 	desc->cyclic = false;
+ 	desc->num_periods = 1;
+@@ -2866,6 +2914,110 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
+ 	return &desc->txd;
+ }
+ 
+static struct dma_async_tx_descriptor *pl330_prep_interleaved_dma(
+	struct dma_chan *chan, struct dma_interleaved_template *xt,
+	unsigned long flags)
+{
+	struct dma_pl330_desc *desc = NULL, *first = NULL;
+	struct dma_pl330_chan *pch = to_pchan(chan);
+	struct pl330_dmac *pl330 = pch->dmac;
+	unsigned int i;
+	dma_addr_t dst;
+	dma_addr_t src;
+	size_t size, src_icg, dst_icg, period_bytes, buffer_bytes, full_period_bytes;
+	size_t nump = 0, numf = 0;
+
+	if (!xt->numf || !xt->sgl[0].size || xt->frame_size != 1)
+		return NULL;
+	nump = xt->nump;
+	numf = xt->numf;
+	size = xt->sgl[0].size;
+	period_bytes = size * nump;
+	buffer_bytes = size * numf;
+
+	if (flags & DMA_PREP_REPEAT && (!nump || (numf % nump)))
+		return NULL;
+
+	src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]);
+	dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]);
+
+	pl330_config_write(chan, &pch->slave_config, xt->dir);
+
+	if (!pl330_prep_slave_fifo(pch, xt->dir))
+		return NULL;
+
+	for (i = 0; i < numf / nump; i++) {
+		desc = pl330_get_desc(pch);
+		if (!desc) {
+			unsigned long iflags;
+
+			dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
+				__func__, __LINE__);
+
+			if (!first)
+				return NULL;
+
+			spin_lock_irqsave(&pl330->pool_lock, iflags);
+
+			while (!list_empty(&first->node)) {
+				desc = list_entry(first->node.next,
+						struct dma_pl330_desc, node);
+				list_move_tail(&desc->node, &pl330->desc_pool);
+			}
+
+			list_move_tail(&first->node, &pl330->desc_pool);
+
+			spin_unlock_irqrestore(&pl330->pool_lock, iflags);
+
+			return NULL;
+		}
+
+		switch (xt->dir) {
+		case DMA_MEM_TO_DEV:
+			desc->rqcfg.src_inc = 1;
+			desc->rqcfg.dst_inc = 0;
+			src = xt->src_start + period_bytes * i;
+			dst = pch->fifo_dma;
+			full_period_bytes = (size + src_icg) * nump;
+			break;
+		case DMA_DEV_TO_MEM:
+			desc->rqcfg.src_inc = 0;
+			desc->rqcfg.dst_inc = 1;
+			src = pch->fifo_dma;
+			dst = xt->dst_start + period_bytes * i;
+			full_period_bytes = (size + dst_icg) * nump;
+			break;
+		default:
+			break;
+		}
+
+		desc->rqtype = xt->dir;
+		desc->rqcfg.brst_size = pch->burst_sz;
+		desc->rqcfg.brst_len = pch->burst_len;
+		desc->bytes_requested = full_period_bytes;
+		desc->sgl.size = size;
+		desc->sgl.src_icg = src_icg;
+		desc->sgl.dst_icg = dst_icg;
+		fill_px(&desc->px, dst, src, period_bytes);
+
+		if (!first)
+			first = desc;
+		else
+			list_add_tail(&desc->node, &first->node);
+	}
+
+	if (!desc)
+		return NULL;
+
+	if (flags & DMA_PREP_REPEAT)
+		desc->cyclic = true;
+
+	dev_dbg(chan->device->dev, "size: %zu, src_icg: %zu, dst_icg: %zu, nump: %zu, numf: %zu\n",
+		size, src_icg, dst_icg, nump, numf);
+
+	return &desc->txd;
+}
+
+ static struct dma_async_tx_descriptor *
+ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
+ 		dma_addr_t src, size_t len, unsigned long flags)
+@@ -3221,12 +3373,16 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
+ 		dma_cap_set(DMA_SLAVE, pd->cap_mask);
+ 		dma_cap_set(DMA_CYCLIC, pd->cap_mask);
+ 		dma_cap_set(DMA_PRIVATE, pd->cap_mask);
+		dma_cap_set(DMA_INTERLEAVE, pd->cap_mask);
+		dma_cap_set(DMA_REPEAT, pd->cap_mask);
+		dma_cap_set(DMA_LOAD_EOT, pd->cap_mask);
+ 	}
+ 
+ 	pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
+ 	pd->device_free_chan_resources = pl330_free_chan_resources;
+ 	pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
+ 	pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
+	pd->device_prep_interleaved_dma = pl330_prep_interleaved_dma;
+ 	pd->device_tx_status = pl330_tx_status;
+ 	pd->device_prep_slave_sg = pl330_prep_slave_sg;
+ 	pd->device_config = pl330_config;
+diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
+index 111111111111..222222222222 100644
+--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
+@@ -156,6 +156,7 @@ struct dma_interleaved_template {
+ 	bool src_sgl;
+ 	bool dst_sgl;
+ 	size_t numf;
+	size_t nump;
+ 	size_t frame_size;
+ 	struct data_chunk sgl[];
+ };
+-- 
+Armbian
+
--- a/_build/patch/general-pl330-04-bigger-mcode-buffer.patch
+++ b/_build/patch/general-pl330-04-bigger-mcode-buffer.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 26 Jan 2025 14:49:18 +0100
+Subject: increase pl330 microcode buffer size
+
+suggestion comes from the scatter/gather functionality as
+proposed here: https://github.com/radxa/kernel/commit/ec0b65dbc59793426b6dc7af06ab6675f4a24940
+---
+ drivers/dma/pl330.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
+index 111111111111..222222222222 100644
+--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
+@@ -247,7 +247,7 @@ enum pl330_byteswap {
+  * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
+  * should be enough for P<->M and M<->M respectively.
+  */
+-#define MCODE_BUFF_PER_REQ	256
+#define MCODE_BUFF_PER_REQ	512
+ 
+ /* Use this _only_ to wait on transient states */
+ #define UNTIL(t, s)	while (!(_state(t) & (s))) cpu_relax();
+-- 
+Armbian
+
--- a/_build/patch/general-pl330-05-fix-unbalanced-power-down.patch
+++ b/_build/patch/general-pl330-05-fix-unbalanced-power-down.patch
@@ -0,0 +1,81 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sugar Zhang <sugar.zhang@rock-chips.com>
+Date: Sat, 26 Mar 2022 18:01:21 +0800
+Subject: dmaengine: pl330: Fix unbalanced runtime PM
+
+This driver use runtime PM autosuspend mechanism to manager clk.
+
+  pm_runtime_use_autosuspend(&adev->dev);
+  pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
+
+So, after ref count reached to zero, it will enter suspend
+after the delay time elapsed.
+
+The unbalanced PM:
+
+* May cause dmac the next start failed.
+* May cause dmac read unexpected state.
+* May cause dmac stall if power down happen at the middle of the transfer.
+  e.g. may lose ack from AXI bus and stall.
+
+Considering the following situation:
+
+      DMA TERMINATE               TASKLET ROUTINE
+            |                            |
+            |                       issue_pending
+            |                            |
+            |                     pch->active = true
+            |                       pm_runtime_get
+  pm_runtime_put(if active)              |
+    pch->active = false                  |
+            |                      work_list empty
+            |                            |
+            |                     pm_runtime_put(force)
+            |                            |
+
+At this point, it's unbalanced(1 get / 2 put).
+
+After this patch:
+
+      DMA TERMINATE               TASKLET ROUTINE
+            |                            |
+            |                       issue_pending
+            |                            |
+            |                     pch->active = true
+            |                       pm_runtime_get
+  pm_runtime_put(if active)              |
+    pch->active = false                  |
+            |                      work_list empty
+            |                            |
+            |                   pm_runtime_put(if active)
+            |                            |
+
+Now, it's balanced(1 get / 1 put).
+
+Fixes:
+commit 5c9e6c2b2ba3 ("dmaengine: pl330: Fix runtime PM support for terminated transfers")
+commit ae43b3289186 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12")
+
+Change-Id: Ib1feb508c16afb4bc9ced0c3660f2b6b4a19c068
+Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
+Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
+---
+ drivers/dma/pl330.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
+index 111111111111..222222222222 100644
+--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
+@@ -2274,7 +2274,7 @@ static void pl330_tasklet(struct tasklet_struct *t)
+ 		spin_lock(&pch->thread->dmac->lock);
+ 		_stop(pch->thread);
+ 		spin_unlock(&pch->thread->dmac->lock);
+-		power_down = true;
+		power_down = pch->active;
+ 		pch->active = false;
+ 	} else {
+ 		/* Make sure the PL330 Channel thread is active */
+-- 
+Armbian
+
--- a/_build/patch/general-pl330-06-fix-buffer-underruns.patch
+++ b/_build/patch/general-pl330-06-fix-buffer-underruns.patch
@@ -0,0 +1,70 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 16 Feb 2025 11:15:55 +0100
+Subject: pl330: fix buffer underrun with cyclic dma
+
+userspace applications (notably, pulseaudio) were
+suffering frequent buffer underruns when cyclic DMA
+was handled by controller itself. This patch fixes
+the buffer underruns avoiding to juggle with the
+descriptor state, keeping it in BUSY state as long
+as it is actual transfer is progressing.
+---
+ drivers/dma/pl330.c | 24 +++++-----
+ 1 file changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
+index 111111111111..222222222222 100644
+--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
+@@ -1737,11 +1737,11 @@ static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
+ 	if (!pch)
+ 		return;
+ 
+-	spin_lock_irqsave(&pch->lock, flags);
+-
+-	desc->status = DONE;
+-
+-	spin_unlock_irqrestore(&pch->lock, flags);
+	if (!desc->cyclic) {
+		spin_lock_irqsave(&pch->lock, flags);
+		desc->status = DONE;
+		spin_unlock_irqrestore(&pch->lock, flags);
+	}
+ 
+ 	tasklet_schedule(&pch->task);
+ }
+@@ -2248,23 +2248,23 @@ static void pl330_tasklet(struct tasklet_struct *t)
+ 
+ 	/* Pick up ripe tomatoes */
+ 	list_for_each_entry_safe(desc, _dt, &pch->work_list, node) {
+-		if (desc->status == DONE) {
+-			if (!desc->cyclic) {
+-				dma_cookie_complete(&desc->txd);
+-				list_move_tail(&desc->node, &pch->completed_list);
+-			} else {
+-				struct dmaengine_desc_callback cb;
+ 
+		if (desc->cyclic) {
+			if (desc->status == BUSY || desc->status == DONE) {
+				struct dmaengine_desc_callback cb;
+ 				desc->status = BUSY;
+ 				dmaengine_desc_get_callback(&desc->txd, &cb);
+-
+ 				if (dmaengine_desc_callback_valid(&cb)) {
+ 					spin_unlock_irqrestore(&pch->lock, flags);
+ 					dmaengine_desc_callback_invoke(&cb, NULL);
+ 					spin_lock_irqsave(&pch->lock, flags);
+ 				}
+ 			}
+		} else if (desc->status == DONE) {
+			dma_cookie_complete(&desc->txd);
+			list_move_tail(&desc->node, &pch->completed_list);
+ 		}
+
+ 	}
+ 
+ 	/* Try to submit a req imm. next to the last completed cookie */
+-- 
+Armbian
+
--- a/_build/patch/general-possibility-of-disabling-rk808-rtc.patch
+++ b/_build/patch/general-possibility-of-disabling-rk808-rtc.patch
@@ -0,0 +1,51 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Sun, 24 Jan 2021 16:14:06 +0100
+Subject: add possibility of disabling rk808-rtc
+
+To disable rk808-rtc driver from loading for specific board
+add the following stanza to rk808 node in device tree:
+
+	rtc {
+		compatible = "rk808-rtc";
+		status = "disabled";
+	}
+
+This is needed for roc-rk3399-pc plus (a.k.a. Station P1).
+Without the change rk808's rtc is initialised and used for time keeping
+although there is another rtc (hym8563) that should be actually used.
+
+Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
+---
+ drivers/mfd/mfd-core.c   | 2 +-
+ drivers/mfd/rk8xx-core.c | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
+index 111111111111..222222222222 100644
+--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
+@@ -209,7 +209,7 @@ static int mfd_add_device(struct device *parent, int id,
+ 
+ match:
+ 		if (!pdev->dev.of_node)
+-			pr_warn("%s: Failed to locate of_node [id: %d]\n",
+			pr_debug("%s: Failed to locate of_node [id: %d]\n",
+ 				cell->name, platform_id);
+ 	}
+ 
+diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c
+index 111111111111..222222222222 100644
+--- a/drivers/mfd/rk8xx-core.c
+++ b/drivers/mfd/rk8xx-core.c
+@@ -134,6 +134,7 @@ static const struct mfd_cell rk818s[] = {
+ 	{ .name = "rk808-regulator", },
+ 	{
+ 		.name = "rk808-rtc",
+		.of_compatible = "rk808-rtc",
+ 		.num_resources = ARRAY_SIZE(rtc_resources),
+ 		.resources = rtc_resources,
+ 	},
+-- 
+Armbian
+
--- a/_build/patch/general-rk808-configurable-switch-voltage-steps.patch
+++ b/_build/patch/general-rk808-configurable-switch-voltage-steps.patch
@@ -0,0 +1,104 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Piotr Szczepanik <piter75@gmail.com>
+Date: Tue, 2 Mar 2021 21:07:22 +0100
+Subject: allows to change the way that BUCK1 and BUCK2 of rk808 PMIC
+
+This patch allows to change the way that BUCK1 and BUCK2 of rk808 PMIC set voltage.
+
+It allows to change the hardcoded max. 100mV per one change
+to any multiple of 12.5mV while keeping the 100mV default.
+
+It was observed that making the steps smaller (eg. 50mV = 4 * 12.5mV)
+makes the NanoPi M4V2 running stable.
+
+One can configure the max number of steps per single change using
+the "max-buck-steps-per-change" property of rk808 node in device tree.
+
+Below example ensures that voltage is not changed in jumps larger than 50mV:
+
+&rk808 {
+	max-buck-steps-per-change = <4>;
+}
+
+Be aware that changing this parameter affects the time taken to switch between
+OPPs of LiTTLE cores of rk3399.
+
+For overclocked LiTTLE cores with base 408MHz @ 0.825V
+and max. 1.5GHz @ 1.2V it will take 7 steps of 50mV (at least 65uS each - caused by i2c),
+the final 25mV step and 1uS to settle: 7 x 65uS + 1uS = 456uS.
+
+With default setting it would be 3 steps of 100mV (at least 65uS each - caused by i2c),
+the final 75mV step and 1uS to settle: 3 x 65uS + 1uS = 196uS.
+
+- rpardini: fix 'client_dev' -> 'dev' (for '->of_node') for 6.5.y
+
+Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
+Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
+---
+ drivers/regulator/rk808-regulator.c | 17 +++++++---
+ 1 file changed, 13 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c
+index 111111111111..222222222222 100644
+--- a/drivers/regulator/rk808-regulator.c
+++ b/drivers/regulator/rk808-regulator.c
+@@ -207,6 +207,7 @@ struct rk8xx_register_bit {
+ 
+ struct rk808_regulator_data {
+ 	struct gpio_desc *dvs_gpio[2];
+	unsigned max_buck_steps_per_change;
+ };
+ 
+ static const struct linear_range rk808_ldo3_voltage_ranges[] = {
+@@ -419,7 +420,8 @@ static int rk808_buck1_2_get_voltage_sel_regmap(struct regulator_dev *rdev)
+ }
+ 
+ static int rk808_buck1_2_i2c_set_voltage_sel(struct regulator_dev *rdev,
+-					     unsigned sel)
+					     unsigned sel,
+					     int max_steps)
+ {
+ 	int ret, delta_sel;
+ 	unsigned int old_sel, tmp, val, mask = rdev->desc->vsel_mask;
+@@ -438,8 +440,8 @@ static int rk808_buck1_2_i2c_set_voltage_sel(struct regulator_dev *rdev,
+ 	 * the risk of overshoot. Put it into a multi-step, can effectively
+ 	 * avoid this problem, a step is 100mv here.
+ 	 */
+-	while (delta_sel > MAX_STEPS_ONE_TIME) {
+-		old_sel += MAX_STEPS_ONE_TIME;
+	while (delta_sel > max_steps) {
+		old_sel += max_steps;
+ 		val = old_sel << (ffs(mask) - 1);
+ 		val |= tmp;
+ 
+@@ -473,12 +475,13 @@ static int rk808_buck1_2_set_voltage_sel(struct regulator_dev *rdev,
+ 	struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev);
+ 	int id = rdev_get_id(rdev);
+ 	struct gpio_desc *gpio = pdata->dvs_gpio[id];
+	int max_steps = pdata->max_buck_steps_per_change;
+ 	unsigned int reg = rdev->desc->vsel_reg;
+ 	unsigned old_sel;
+ 	int ret, gpio_level;
+ 
+ 	if (!gpio)
+-		return rk808_buck1_2_i2c_set_voltage_sel(rdev, sel);
+		return rk808_buck1_2_i2c_set_voltage_sel(rdev, sel, max_steps);
+ 
+ 	gpio_level = gpiod_get_value(gpio);
+ 	if (gpio_level == 0) {
+@@ -1860,6 +1863,12 @@ static int rk808_regulator_dt_parse_pdata(struct device *dev, struct regmap *map
+ 					 gpiod_is_active_low(pdata->dvs_gpio[i]) ? 0 : tmp);
+ 	}
+ 
+	tmp = of_property_read_u32(dev->of_node, "max-buck-steps-per-change", &pdata->max_buck_steps_per_change);
+	if (tmp) {
+		pdata->max_buck_steps_per_change = MAX_STEPS_ONE_TIME;
+	}
+	dev_info(dev, "max buck steps per change: %d\n", pdata->max_buck_steps_per_change);
+
+ dt_parse_end:
+ 	of_node_put(np);
+ 	return ret;
+-- 
+Armbian
+
--- a/_build/patch/general-v4l2-iep-driver.patch
+++ b/_build/patch/general-v4l2-iep-driver.patch
--- a/_build/patch/media-0001-Add-rkvdec-Support-v5.patch
+++ b/_build/patch/media-0001-Add-rkvdec-Support-v5.patch
--- a/_build/patch/media-0002-media-rkvdec-remove-vb2_is_busy-check-in-rkvdec_s_ct.patch
+++ b/_build/patch/media-0002-media-rkvdec-remove-vb2_is_busy-check-in-rkvdec_s_ct.patch
@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+Date: Thu, 4 Sep 2025 15:35:22 +0800
+Subject: media: rkvdec: remove vb2_is_busy check in rkvdec_s_ctrl
+
+This check will case green screen when playing videos with
+chromium. rkvdec driver seems to be the only decoder driver
+that have this check. Further investigation is needed.
+---
+ drivers/media/platform/rockchip/rkvdec/rkvdec.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c
+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c
+@@ -186,7 +186,6 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
+ 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+ 	const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
+ 	enum rkvdec_image_fmt image_fmt;
+-	struct vb2_queue *vq;
+ 
+ 	/* Check if this change requires a capture format reset */
+ 	if (!desc->ops->get_image_fmt)
+@@ -194,11 +193,6 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
+ 
+ 	image_fmt = desc->ops->get_image_fmt(ctx, ctrl);
+ 	if (rkvdec_image_fmt_changed(ctx, image_fmt)) {
+-		vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
+-				     V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+-		if (vb2_is_busy(vq))
+-			return -EBUSY;
+-
+ 		ctx->image_fmt = image_fmt;
+ 		rkvdec_reset_decoded_fmt(ctx);
+ 	}
+-- 
+Armbian
+
--- a/kernel.patches/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch
+++ b/kernel.patches/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch
--- a/_build/patch/media-0003-rk3568-disable-hantro-h264.patch
+++ b/_build/patch/media-0003-rk3568-disable-hantro-h264.patch
@@ -0,0 +1,97 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: amazingfate <liujianfeng1994@gmail.com>
+Date: Sun, 28 Jul 2024 14:35:34 +0800
+Subject: [ARCHEOLOGY] rockchip64-edge: disable hantro g1 h264 decoder on
+ rk356x
+
+> X-Git-Archeology: - Revision d5cb0d6732f7ab06f34ee6ce18ed6bef266c3c4a: https://github.com/armbian/build/commit/d5cb0d6732f7ab06f34ee6ce18ed6bef266c3c4a
+> X-Git-Archeology:   Date: Sun, 28 Jul 2024 14:35:34 +0800
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: rockchip64-edge: disable hantro g1 h264 decoder on rk356x
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi        |  2 +-
+ drivers/media/platform/verisilicon/hantro_drv.c      |  1 -
+ drivers/media/platform/verisilicon/hantro_hw.h       |  1 -
+ drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 21 ++--------
+ 4 files changed, 4 insertions(+), 21 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1242,7 +1242,7 @@ rknn_mmu_2: iommu@fdad9000 {
+ 	};
+ 
+ 	vpu121: video-codec@fdb50000 {
+-		compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
+		compatible = "rockchip,rk3588-vpu121", "rockchip,rk3328-vpu";
+ 		reg = <0x0 0xfdb50000 0x0 0x800>;
+ 		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		interrupt-names = "vdpu";
+diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/verisilicon/hantro_drv.c
+++ b/drivers/media/platform/verisilicon/hantro_drv.c
+@@ -718,7 +718,6 @@ static const struct of_device_id of_hantro_match[] = {
+ 	{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
+ 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
+ 	{ .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
+-	{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
+ 	{ .compatible = "rockchip,rk3588-vepu121", .data = &rk3568_vepu_variant, },
+ 	{ .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, },
+ #endif
+diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/verisilicon/hantro_hw.h
+++ b/drivers/media/platform/verisilicon/hantro_hw.h
+@@ -413,7 +413,6 @@ extern const struct hantro_variant rk3288_vpu_variant;
+ extern const struct hantro_variant rk3328_vpu_variant;
+ extern const struct hantro_variant rk3399_vpu_variant;
+ extern const struct hantro_variant rk3568_vepu_variant;
+-extern const struct hantro_variant rk3568_vpu_variant;
+ extern const struct hantro_variant rk3588_vpu981_variant;
+ extern const struct hantro_variant sama5d4_vdec_variant;
+ extern const struct hantro_variant sunxi_vpu_variant;
+diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+@@ -724,10 +724,9 @@ const struct hantro_variant rk3288_vpu_variant = {
+ 
+ const struct hantro_variant rk3328_vpu_variant = {
+ 	.dec_offset = 0x400,
+-	.dec_fmts = rockchip_vdpu2_dec_fmts,
+-	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
+-	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
+-		 HANTRO_H264_DECODER,
+	.dec_fmts = rk3399_vpu_dec_fmts,
+	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
+	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
+ 	.codec_ops = rk3399_vpu_codec_ops,
+ 	.irqs = rockchip_vdpu2_irqs,
+ 	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
+@@ -771,20 +770,6 @@ const struct hantro_variant rk3568_vepu_variant = {
+ 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
+ };
+ 
+-const struct hantro_variant rk3568_vpu_variant = {
+-	.dec_offset = 0x400,
+-	.dec_fmts = rockchip_vdpu2_dec_fmts,
+-	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
+-	.codec = HANTRO_MPEG2_DECODER |
+-		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
+-	.codec_ops = rk3399_vpu_codec_ops,
+-	.irqs = rockchip_vdpu2_irqs,
+-	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
+-	.init = rockchip_vpu_hw_init,
+-	.clk_names = rockchip_vpu_clk_names,
+-	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
+-};
+-
+ const struct hantro_variant px30_vpu_variant = {
+ 	.enc_offset = 0x0,
+ 	.enc_fmts = rockchip_vpu_enc_fmts,
+-- 
+Armbian
+
--- a/_build/patch/net-ethernet-realtek-add-r8169-LED-configuration-from-OF.patch
+++ b/_build/patch/net-ethernet-realtek-add-r8169-LED-configuration-from-OF.patch
@@ -0,0 +1,49 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: John Doe <john.doe@somewhere.on.planet>
+Date: Sat, 30 Aug 2025 14:20:46 +0800
+Subject: net: ethernet: realtek: add r8169 LED configuration from OF
+
+Signed-off-by: retro98boy <retro98boy@qq.com>
+---
+ drivers/net/ethernet/realtek/r8169_main.c | 11 ++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
+index 111111111111..222222222222 100644
+--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -21,6 +21,7 @@
+ #include <linux/in.h>
+ #include <linux/io.h>
+ #include <linux/ip.h>
+#include <linux/of.h>
+ #include <linux/tcp.h>
+ #include <linux/interrupt.h>
+ #include <linux/dma-mapping.h>
+@@ -2382,6 +2383,15 @@ void r8169_apply_firmware(struct rtl8169_private *tp)
+ 	}
+ }
+ 
+static void rtl8168_led_of_init(struct rtl8169_private *tp)
+{
+	struct device *d = tp_to_dev(tp);
+	u32 val;
+
+	if (!of_property_read_u32(d->of_node, "realtek,led-data", &val))
+		RTL_W16(tp, LED_CTRL, val);
+}
+
+ static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
+ {
+ 	/* Adjust EEE LED frequency */
+@@ -3399,6 +3409,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
+ 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
+ 
+ 	rtl8168_config_eee_mac(tp);
+	rtl8168_led_of_init(tp);
+ 
+ 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
+ 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
+-- 
+Armbian
+
--- a/_build/patch/regulator-add-fan53200-driver.patch
+++ b/_build/patch/regulator-add-fan53200-driver.patch
@@ -0,0 +1,597 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Rock Shen <rock_shen@asus.com>
+Date: Tue, 27 Apr 2021 11:13:25 +0800
+Subject: regulator: add fan53200 regulator driver for Tinkerboard-2
+
+1. Add fan53200 regulator support for vdd_cpu_b & vdd_gpu
+2. By Tinker2 HW design, Vsel gpio pin polarity was reversed, switch
+   sleep_reg & vol_reg at fan53200_voltages_setup_fairchild
+3. Use vsel0 as suspend source, vsel1 as normal source
+
+- rpardini: hammered .probe and probe_type = PROBE_PREFER_ASYNCHRONOUS to
+  work on 6.6.y, after https://lore.kernel.org/all/20230505220218.1239542-1-u.kleine-koenig@pengutronix.de/
+
+Signed-off-by: Rock Shen <rock_shen@asus.com>
+Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
+---
+ arch/arm64/configs/defconfig |   1 +
+ drivers/regulator/Kconfig    |  11 +
+ drivers/regulator/Makefile   |   1 +
+ drivers/regulator/fan53200.c | 520 ++++++++++
+ 4 files changed, 533 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 111111111111..222222222222 100644
+--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
+@@ -810,6 +810,7 @@ CONFIG_REGULATOR_BD9571MWV=y
+ CONFIG_REGULATOR_CROS_EC=y
+ CONFIG_REGULATOR_DA9211=m
+ CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FAN53200=y
+ CONFIG_REGULATOR_GPIO=y
+ CONFIG_REGULATOR_HI6421V530=y
+ CONFIG_REGULATOR_HI655X=y
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+index 111111111111..222222222222 100644
+--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
+@@ -440,6 +440,17 @@ config REGULATOR_FAN53880
+ 	  (PMIC), it is controlled by I2C and provides one BUCK, one BOOST
+ 	  and four LDO outputs.
+ 
+config REGULATOR_FAN53200
+	tristate "Fairchild FAN53200 Regulator"
+	depends on I2C
+	select REGMAP_I2C
+	help
+	  This driver supports Fairchild FAN53200 Digitally Programmable
+	  TinyBuck Regulator. The FAN53200 is a step-down switching voltage
+	  regulator that delivers a digitally programmable output from an
+	  input voltage supply of 2.5V to 5.5V. The output voltage is
+	  programmed through an I2C interface.
+
+ config REGULATOR_GPIO
+ 	tristate "GPIO regulator support"
+ 	depends on GPIOLIB || COMPILE_TEST
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+index 111111111111..222222222222 100644
+--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
+@@ -52,6 +52,7 @@ obj-$(CONFIG_REGULATOR_DBX500_PRCMU) += dbx500-prcmu.o
+ obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
+ obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o
+ obj-$(CONFIG_REGULATOR_FAN53880) += fan53880.o
+obj-$(CONFIG_REGULATOR_FAN53555) += fan53200.o
+ obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o
+ obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o
+ obj-$(CONFIG_REGULATOR_HI6421V530) += hi6421v530-regulator.o
+diff --git a/drivers/regulator/fan53200.c b/drivers/regulator/fan53200.c
+new file mode 100644
+index 000000000000..111111111111
+--- /dev/null
+++ b/drivers/regulator/fan53200.c
+@@ -0,0 +1,520 @@
+/*
+ * FAN53200 Fairchild Digitally Programmable TinyBuck Regulator Driver.
+ *
+ * Supported Part Numbers:
+ * FAN53200UC35X/44X
+ *
+ * Copyright (c) 2021 ASUSTeK Computer Inc.
+ * Rock Shen <rock_shen@asus.com>
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/of_device.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+
+/* Voltage setting */
+#define FAN53200_VSEL0		0x00
+#define FAN53200_VSEL1		0x01
+
+/* Control register */
+#define FAN53200_CONTROL	0x02
+/* IC Type */
+#define FAN53200_ID1		0x03
+/* IC mask version */
+#define FAN53200_ID2		0x04
+
+/* VSEL bit definitions */
+#define VSEL_BUCK_EN	(1 << 7)
+#define VSEL_MODE		(1 << 6)
+#define VSEL_NSEL_MASK	0x3F
+/* Chip ID and Verison */
+#define DIE_ID		0x0F	/* ID1 */
+#define DIE_REV		0x0F	/* ID2 */
+/* Control bit definitions */
+#define CTL_OUTPUT_DISCHG	(1 << 7)
+#define CTL_SLEW_MASK		(0x7 << 4)
+#define CTL_SLEW_SHIFT		4
+#define CTL_RESET			(1 << 2)
+
+#define TCS_VSEL_NSEL_MASK	0x7f
+#define TCS_VSEL0_MODE		(1 << 7)
+#define TCS_VSEL1_MODE		(1 << 6)
+
+#define TCS_SLEW_SHIFT		3
+#define TCS_SLEW_MASK		(0x3 < 3)
+
+#define FAN53200_NVOLTAGES	64	/* Numbers of voltages */
+
+enum fan53200_vendor {
+	FAN53200_VENDOR_FAIRCHILD = 0,
+};
+
+/* VSEL ID */
+enum {
+	FAN53200_VSEL_ID_0 = 0,
+	FAN53200_VSEL_ID_1,
+};
+
+enum {
+	FAN53200_CHIP_ID_00 = 0x8001,
+	FAN53200_CHIP_ID_01 = 0x8101,
+};
+
+struct fan53200_platform_data {
+	struct regulator_init_data *regulator;
+	unsigned int slew_rate;
+	/* Sleep VSEL ID */
+	unsigned int sleep_vsel_id;
+	struct gpio_desc *vsel_gpio;
+};
+
+struct fan53200_device_info {
+	enum fan53200_vendor vendor;
+	struct regmap *regmap;
+	struct device *dev;
+	struct regulator_desc desc;
+	struct regulator_dev *rdev;
+	struct regulator_init_data *regulator;
+	/* IC Type and Rev */
+	int chip_id;
+	int chip_rev;
+	/* Voltage setting register */
+	unsigned int vol_reg;
+	unsigned int sleep_reg;
+	unsigned int mode_reg;
+	unsigned int vol_mask;
+	unsigned int mode_mask;
+	unsigned int slew_reg;
+	unsigned int slew_mask;
+	unsigned int slew_shift;
+	/* Voltage range and step(linear) */
+	unsigned int vsel_min;
+	unsigned int vsel_step;
+	unsigned int n_voltages;
+	/* Voltage slew rate limiting */
+	unsigned int slew_rate;
+	/* Sleep voltage cache */
+	unsigned int sleep_vol_cache;
+	struct gpio_desc *vsel_gpio;
+	unsigned int sleep_vsel_id;
+};
+
+static unsigned int fan53200_map_mode(unsigned int mode)
+{
+	return mode == REGULATOR_MODE_FAST ?
+		REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
+}
+
+static int fan53200_set_suspend_voltage(struct regulator_dev *rdev, int uV)
+{
+	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
+	int ret;
+
+	if (di->sleep_vol_cache == uV)
+		return 0;
+	ret = regulator_map_voltage_linear(rdev, uV, uV);
+	if (ret < 0)
+		return ret;
+	ret = regmap_update_bits(di->regmap, di->sleep_reg,
+				 di->vol_mask, ret);
+	if (ret < 0)
+		return ret;
+	/* Cache the sleep voltage setting.
+	 * Might not be the real voltage which is rounded */
+	di->sleep_vol_cache = uV;
+
+	return 0;
+}
+
+static int fan53200_set_suspend_enable(struct regulator_dev *rdev)
+{
+	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
+
+	return regmap_update_bits(di->regmap, di->sleep_reg,
+				  VSEL_BUCK_EN, VSEL_BUCK_EN);
+}
+
+static int fan53200_set_suspend_disable(struct regulator_dev *rdev)
+{
+	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
+
+	return regmap_update_bits(di->regmap, di->sleep_reg,
+				  VSEL_BUCK_EN, 0);
+}
+
+static int fan53200_set_enable(struct regulator_dev *rdev)
+{
+	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
+
+	if (di->vsel_gpio) {
+		gpiod_set_raw_value(di->vsel_gpio, !di->sleep_vsel_id);
+		return 0;
+	}
+
+	return regmap_update_bits(di->regmap, di->vol_reg,
+				  VSEL_BUCK_EN, VSEL_BUCK_EN);
+}
+
+static int fan53200_set_disable(struct regulator_dev *rdev)
+{
+	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
+
+	if (di->vsel_gpio) {
+		gpiod_set_raw_value(di->vsel_gpio, di->sleep_vsel_id);
+		return 0;
+	}
+
+	return regmap_update_bits(di->regmap, di->vol_reg,
+				  VSEL_BUCK_EN, 0);
+}
+
+static int fan53200_is_enabled(struct regulator_dev *rdev)
+{
+	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
+	unsigned int val;
+	int ret = 0;
+
+	if (di->vsel_gpio) {
+		if (di->sleep_vsel_id)
+			return !gpiod_get_raw_value(di->vsel_gpio);
+		else
+			return gpiod_get_raw_value(di->vsel_gpio);
+	}
+
+	ret = regmap_read(di->regmap, di->vol_reg, &val);
+	if (ret < 0)
+		return ret;
+	if (val & VSEL_BUCK_EN)
+		return 1;
+	else
+		return 0;
+}
+
+static int fan53200_set_mode(struct regulator_dev *rdev, unsigned int mode)
+{
+	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
+
+	switch (mode) {
+	case REGULATOR_MODE_FAST:
+		regmap_update_bits(di->regmap, di->mode_reg,
+				   di->mode_mask, di->mode_mask);
+		break;
+	case REGULATOR_MODE_NORMAL:
+		regmap_update_bits(di->regmap, di->mode_reg, di->mode_mask, 0);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static unsigned int fan53200_get_mode(struct regulator_dev *rdev)
+{
+	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
+	unsigned int val;
+	int ret = 0;
+
+	ret = regmap_read(di->regmap, di->mode_reg, &val);
+	if (ret < 0)
+		return ret;
+	if (val & di->mode_mask)
+		return REGULATOR_MODE_FAST;
+	else
+		return REGULATOR_MODE_NORMAL;
+}
+
+static const int slew_rates[] = {
+	80000,
+	40000,
+	20000,
+	10000,
+	5000,
+	2500,
+	1250,
+	625,
+};
+
+static int fan53200_set_ramp(struct regulator_dev *rdev, int ramp)
+{
+	struct fan53200_device_info *di = rdev_get_drvdata(rdev);
+	int regval = -1, i;
+
+	for (i = 0; i < ARRAY_SIZE(slew_rates); i++) {
+		if (ramp <= slew_rates[i])
+			regval = i;
+		else
+			break;
+	}
+
+	if (regval < 0) {
+		dev_err(di->dev, "unsupported ramp value %d\n", ramp);
+		return -EINVAL;
+	}
+
+	return regmap_update_bits(di->regmap, di->slew_reg,
+				  di->slew_mask, regval << di->slew_shift);
+}
+
+static struct regulator_ops fan53200_regulator_ops = {
+	.set_voltage_sel = regulator_set_voltage_sel_regmap,
+	.get_voltage_sel = regulator_get_voltage_sel_regmap,
+	.set_voltage_time_sel = regulator_set_voltage_time_sel,
+	.map_voltage = regulator_map_voltage_linear,
+	.list_voltage = regulator_list_voltage_linear,
+	.set_suspend_voltage = fan53200_set_suspend_voltage,
+	.enable = fan53200_set_enable,
+	.disable = fan53200_set_disable,
+	.is_enabled = fan53200_is_enabled,
+	.set_mode = fan53200_set_mode,
+	.get_mode = fan53200_get_mode,
+	.set_ramp_delay = fan53200_set_ramp,
+	.set_suspend_enable = fan53200_set_suspend_enable,
+	.set_suspend_disable = fan53200_set_suspend_disable,
+};
+
+static int fan53200_voltages_setup_fairchild(struct fan53200_device_info *di)
+{
+
+	if (di->sleep_vsel_id) {
+		di->sleep_reg = FAN53200_VSEL0;
+		di->vol_reg = FAN53200_VSEL1;
+	} else {
+		di->sleep_reg = FAN53200_VSEL1;
+		di->vol_reg = FAN53200_VSEL0;
+	}
+
+	/* Init voltage range and step */
+	di->vsel_min = 600000;
+	di->vsel_step = 12500;
+	di->vol_mask = VSEL_NSEL_MASK;
+	di->mode_reg = di->vol_reg;
+	di->mode_mask = VSEL_MODE;
+	di->slew_reg = FAN53200_CONTROL;
+	di->slew_mask = CTL_SLEW_MASK;
+	di->slew_shift = CTL_SLEW_SHIFT;
+	di->n_voltages = FAN53200_NVOLTAGES;
+
+	return 0;
+}
+
+/* For 00,01,03,05 options:
+ * VOUT = 0.60V + NSELx * 10mV, from 0.60 to 1.23V.
+ * For 04 option:
+ * VOUT = 0.603V + NSELx * 12.826mV, from 0.603 to 1.411V.
+ * */
+static int fan53200_device_setup(struct fan53200_device_info *di,
+				struct fan53200_platform_data *pdata)
+{
+	int ret = 0;
+
+	ret = fan53200_voltages_setup_fairchild(di);
+
+	return ret;
+}
+
+static int fan53200_regulator_register(struct fan53200_device_info *di,
+			struct regulator_config *config)
+{
+	struct regulator_desc *rdesc = &di->desc;
+
+	rdesc->name = "fan53200-reg";
+	rdesc->supply_name = "vin";
+	rdesc->ops = &fan53200_regulator_ops;
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->n_voltages = di->n_voltages;
+	rdesc->enable_reg = di->vol_reg;
+	rdesc->enable_mask = VSEL_BUCK_EN;
+	rdesc->min_uV = di->vsel_min;
+	rdesc->uV_step = di->vsel_step;
+	rdesc->vsel_reg = di->vol_reg;
+	rdesc->vsel_mask = di->vol_mask;
+	rdesc->owner = THIS_MODULE;
+	rdesc->enable_time = 400;
+
+	di->rdev = devm_regulator_register(di->dev, &di->desc, config);
+	return PTR_ERR_OR_ZERO(di->rdev);
+}
+
+static const struct regmap_config fan53200_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+};
+
+static struct fan53200_platform_data *fan53200_parse_dt(struct device *dev,
+					      struct device_node *np,
+					      const struct regulator_desc *desc)
+{
+	struct fan53200_platform_data *pdata;
+	int ret, flag;
+	u32 tmp;
+
+	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return NULL;
+
+	pdata->regulator = of_get_regulator_init_data(dev, np, desc);
+	pdata->regulator->constraints.initial_state = PM_SUSPEND_MEM;
+
+	ret = of_property_read_u32(np, "fcs,suspend-voltage-selector",
+				   &tmp);
+	if (!ret)
+		pdata->sleep_vsel_id = tmp;
+
+	if (pdata->sleep_vsel_id)
+		flag = GPIOD_OUT_LOW;
+	else
+		flag = GPIOD_OUT_HIGH;
+
+	pdata->vsel_gpio =
+		devm_gpiod_get_index_optional(dev, "vsel", 0,
+					      flag);
+	if (IS_ERR(pdata->vsel_gpio)) {
+		ret = PTR_ERR(pdata->vsel_gpio);
+		dev_err(dev, "failed to get vesl gpio (%d)\n", ret);
+	}
+
+	return pdata;
+}
+
+static const struct of_device_id fan53200_dt_ids[] = {
+	{
+		.compatible = "fcs,fan53200",
+		.data = (void *)FAN53200_VENDOR_FAIRCHILD,
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, fan53200_dt_ids);
+
+static int fan53200_regulator_probe(struct i2c_client *client)
+{
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
+	struct device_node *np = client->dev.of_node;
+	struct fan53200_device_info *di;
+	struct fan53200_platform_data *pdata;
+	struct regulator_config config = { };
+	unsigned int val;
+	int ret;
+
+	di = devm_kzalloc(&client->dev, sizeof(struct fan53200_device_info),
+					GFP_KERNEL);
+	if (!di)
+		return -ENOMEM;
+
+	di->desc.of_map_mode = fan53200_map_mode;
+
+	pdata = dev_get_platdata(&client->dev);
+	if (!pdata)
+		pdata = fan53200_parse_dt(&client->dev, np, &di->desc);
+
+	if (!pdata || !pdata->regulator) {
+		dev_err(&client->dev, "Platform data not found!\n");
+		return -ENODEV;
+	}
+
+	di->vsel_gpio = pdata->vsel_gpio;
+	di->sleep_vsel_id = pdata->sleep_vsel_id;
+
+	di->regulator = pdata->regulator;
+	if (client->dev.of_node) {
+		const struct of_device_id *match;
+
+		match = of_match_device(of_match_ptr(fan53200_dt_ids),
+					&client->dev);
+		if (!match)
+			return -ENODEV;
+
+		di->vendor = (unsigned long) match->data;
+	} else {
+		/* if no ramp constraint set, get the pdata ramp_delay */
+		if (!di->regulator->constraints.ramp_delay) {
+			int slew_idx = (pdata->slew_rate & 0x7)
+						? pdata->slew_rate : 0;
+
+			di->regulator->constraints.ramp_delay
+						= slew_rates[slew_idx];
+		}
+
+		di->vendor = id->driver_data;
+	}
+
+	di->regmap = devm_regmap_init_i2c(client, &fan53200_regmap_config);
+	if (IS_ERR(di->regmap)) {
+		dev_err(&client->dev, "Failed to allocate regmap!\n");
+		return PTR_ERR(di->regmap);
+	}
+	di->dev = &client->dev;
+	i2c_set_clientdata(client, di);
+	/* Get chip ID */
+	ret = regmap_read(di->regmap, FAN53200_ID1, &val);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed to get chip ID!\n");
+		return ret;
+	}
+	di->chip_id = val & DIE_ID;
+	/* Get chip revision */
+	ret = regmap_read(di->regmap, FAN53200_ID2, &val);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed to get chip Rev!\n");
+		return ret;
+	}
+	di->chip_rev = val & DIE_REV;
+	dev_info(&client->dev, "FAN53200 Option[%d] Rev[%d] Detected!\n",
+				di->chip_id, di->chip_rev);
+	/* Device init */
+	ret = fan53200_device_setup(di, pdata);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed to setup device!\n");
+		return ret;
+	}
+	/* Register regulator */
+	config.dev = di->dev;
+	config.init_data = di->regulator;
+	config.regmap = di->regmap;
+	config.driver_data = di;
+	config.of_node = np;
+
+	ret = fan53200_regulator_register(di, &config);
+	if (ret < 0)
+		dev_err(&client->dev, "Failed to register regulator!\n");
+	return ret;
+
+}
+
+static const struct i2c_device_id fan53200_id[] = {
+	{
+		.name = "fan53200",
+		.driver_data = FAN53200_VENDOR_FAIRCHILD
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, fan53200_id);
+
+static struct i2c_driver fan53200_regulator_driver = {
+	.driver = {
+		.name = "fan53200-regulator",
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+		.of_match_table = of_match_ptr(fan53200_dt_ids),
+	},
+	.probe = fan53200_regulator_probe,
+	.id_table = fan53200_id,
+};
+
+module_i2c_driver(fan53200_regulator_driver);
+
+MODULE_AUTHOR("Rock Shen <rock_shen@asus.com>");
+MODULE_DESCRIPTION("FAN53200 regulator driver");
+MODULE_LICENSE("GPL v2");
+-- 
+Armbian
+
--- a/_build/patch/rk3588-0010-fix-clk-divisions.patch
+++ b/_build/patch/rk3588-0010-fix-clk-divisions.patch
@@ -15,7 +15,7 @@ diff --git a/include/linux/math.h b/include/linux/math.h
 index 111111111111..222222222222 100644
 --- a/include/linux/math.h
 +++ b/include/linux/math.h
-@@ -36,6 +36,17 @@
+@@ -48,6 +48,17 @@
 
 #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
 
@@ -70,7 +70,7 @@ diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
 index 111111111111..222222222222 100644
 --- a/drivers/clk/clk-divider.c
 +++ b/drivers/clk/clk-divider.c
-@@ -220,7 +220,7 @@ static int _div_round_up(const struct clk_div_table *table,
+@@ -226,7 +226,7 @@ static int _div_round_up(const struct clk_div_table *table,
 			 unsigned long parent_rate, unsigned long rate,
 			 unsigned long flags)
 {
@@ -79,7 +79,7 @@ index 111111111111..222222222222 100644
 
 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
 		div = __roundup_pow_of_two(div);
-@@ -237,7 +237,7 @@ static int _div_round_closest(const struct clk_div_table *table,
+@@ -243,7 +243,7 @@ static int _div_round_closest(const struct clk_div_table *table,
 	int up, down;
 	unsigned long up_rate, down_rate;
 
@@ -88,7 +88,7 @@ index 111111111111..222222222222 100644
 	down = parent_rate / rate;
 
 	if (flags & CLK_DIVIDER_POWER_OF_TWO) {
-@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
+@@ -458,7 +458,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
 {
 	unsigned int div, value;
 
--- a/_build/patch/rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch
+++ b/_build/patch/rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch
@@ -0,0 +1,62 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Joshua Riek <jjriek@verizon.net>
+Date: Thu, 22 Aug 2024 22:32:47 -0400
+Subject: arm64: dts: rockchip: Enable automatic fan control on the Turing RK1
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 32 +++++++++-
+ 1 file changed, 31 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
+@@ -23,7 +23,7 @@ aliases {
+ 
+ 	fan: pwm-fan {
+ 		compatible = "pwm-fan";
+-		cooling-levels = <0 25 95 145 195 255>;
+		cooling-levels = <0 120 150 180 210 240 255>;
+ 		fan-supply = <&vcc5v0_sys>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwm0m2_pins &fan_int>;
+@@ -268,6 +268,36 @@ map5 {
+ 	};
+ };
+ 
+&package_thermal {
+	polling-delay = <1000>;
+
+	trips {
+		package_fan0: package-fan0 {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		package_fan1: package-fan1 {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map1 {
+			trip = <&package_fan0>;
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+		};
+
+		map2 {
+			trip = <&package_fan1>;
+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+ &pcie2x1l1 {
+ 	linux,pci-domain = <1>;
+ 	pinctrl-names = "default";
+-- 
+Armbian
+
--- a/_build/patch/rk3588-1201-arm64-dts-rockchip-Enable-the-NPU-on-CM3588.patch
+++ b/_build/patch/rk3588-1201-arm64-dts-rockchip-Enable-the-NPU-on-CM3588.patch
@@ -0,0 +1,68 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ricardo Pardini <ricardo@pardini.net>
+Date: Mon, 20 Oct 2025 21:29:13 +0200
+Subject: arm64: dts: rockchip: Enable the NPU on CM3588
+
+Enable the NPU on FriendlyElec CM3588;
+vdd_npu_s0 was already in place.
+
+Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi | 34 ++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi
+@@ -264,6 +264,10 @@ &pd_gpu {
+ 	domain-supply = <&vdd_gpu_s0>;
+ };
+ 
+&pd_npu {
+	domain-supply = <&vdd_npu_s0>;
+};
+
+ &pinctrl {
+ 	gpio-leds {
+ 		led_sys_pin: led-sys-pin {
+@@ -294,6 +298,36 @@ sd_s0_pwr: sd-s0-pwr {
+ 	};
+ };
+ 
+&rknn_core_0 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_s0>;
+	status = "okay";
+};
+
+&rknn_core_1 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_s0>;
+	status = "okay";
+};
+
+&rknn_core_2 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_s0>;
+	status = "okay";
+};
+
+&rknn_mmu_0 {
+	status = "okay";
+};
+
+&rknn_mmu_1 {
+	status = "okay";
+};
+
+&rknn_mmu_2 {
+	status = "okay";
+};
+
+ &saradc {
+ 	vref-supply = <&avcc_1v8_s0>;
+ 	status = "okay";
+-- 
+Armbian
+
--- a/_build/patch/rk35xx-montjoie-crypto-v2-rk35xx.patch
+++ b/_build/patch/rk35xx-montjoie-crypto-v2-rk35xx.patch
@@ -95,15 +95,15 @@ node for it.

 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
 ---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 12 ++++++++++
 1 file changed, 12 insertions(+)

-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
 index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1923,6 +1923,18 @@ sdhci: mmc@fe2e0000 {
- 		status = "disabled";
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -2256,6 +2256,18 @@ rng@fe378000 {
+ 		resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>;
 	};
 
 +	crypto: crypto@fe370000 {
@@ -135,14 +135,14 @@ node for it.
 Tested-by: Ricardo Pardini <ricardo@pardini.net>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
 ---
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++
+ arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++
 1 file changed, 12 insertions(+)

-diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
 index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1112,6 +1112,18 @@ sdhci: mmc@fe310000 {
+--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+@@ -1090,6 +1090,18 @@ rng: rng@fe388000 {
 		status = "disabled";
 	};
 
@@ -345,9 +345,9 @@ diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
 index 111111111111..222222222222 100644
 --- a/drivers/crypto/Kconfig
 +++ b/drivers/crypto/Kconfig
-@@ -653,6 +653,35 @@ config CRYPTO_DEV_TEGRA
- 	  Select this to enable Tegra Security Engine which accelerates various
- 	  AES encryption/decryption and HASH algorithms.
+@@ -745,6 +745,35 @@ config CRYPTO_DEV_XILINX_TRNG
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called xilinx-trng.
 
 +config CRYPTO_DEV_ROCKCHIP2
 +	tristate "Rockchip's cryptographic offloader V2"
@@ -385,10 +385,10 @@ diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile
 index 111111111111..222222222222 100644
 --- a/drivers/crypto/rockchip/Makefile
 +++ b/drivers/crypto/rockchip/Makefile
-@@ -3,3 +3,8 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o
- rk_crypto-objs := rk3288_crypto.o \
+@@ -4,3 +4,8 @@ rk_crypto-objs := rk3288_crypto.o \
 		  rk3288_crypto_skcipher.o \
 		  rk3288_crypto_ahash.o
+ rk_crypto-$(CONFIG_CRYPTO_DEV_ROCKCHIP_TRNG) += rk3288_crypto_trng.o
 +
 +obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP2) += rk_crypto2.o
 +rk_crypto2-objs := rk2_crypto.o \
@@ -1102,7 +1102,7 @@ index 000000000000..111111111111
 +	return err;
 +}
 +
-+static int rk2_crypto_remove(struct platform_device *pdev)
+static void rk2_crypto_remove(struct platform_device *pdev)
 +{
 +	struct rk2_crypto_dev *rkc = platform_get_drvdata(pdev);
 +	struct rk2_crypto_dev *first;
@@ -1121,7 +1121,7 @@ index 000000000000..111111111111
 +	}
 +	rk2_crypto_pm_exit(rkc);
 +	crypto_engine_exit(rkc->engine);
-+	return 0;
+	return;
 +}
 +
 +static struct platform_driver crypto_driver = {
@@ -1403,7 +1403,7 @@ index 000000000000..111111111111
 + *
 + * Copyright (c) 2022-2023 Corentin Labbe <clabbe@baylibre.com>
 + */
-+#include <asm/unaligned.h>
+#include <linux/unaligned.h>
 +#include <linux/iopoll.h>
 +#include "rk2_crypto.h"
 +
--- a/_build/series
+++ b/_build/series
@@ -0,0 +1,30 @@
+0001-gokrazy-logo.patch
+drv-spi-spidev-remove-warnings.patch
+general-add-hdmi-mks-ips50-resolutions.patch
+general-add-pll-hdmi-timings.patch
+general-cryptov1-trng.patch
+general-disable-mtu-validation.patch
+general-drm-rockchip-Set-dma-mask-to-64-bit.patch
+general-fix-es8316-kernel-panic.patch
+general-fix-mmc-signal-voltage-before-reboot.patch
+general-hdmi-clock-fixes.patch
+general-increase-spdif-dma-burst.patch
+general-increasing_DMA_block_memory_allocation_to_2048.patch
+general-pl330-01-fix-periodic-transfers.patch
+general-pl330-02-add-support-for-interleaved-transfers.patch
+general-pl330-04-bigger-mcode-buffer.patch
+general-pl330-05-fix-unbalanced-power-down.patch
+general-pl330-06-fix-buffer-underruns.patch
+general-possibility-of-disabling-rk808-rtc.patch
+general-rk808-configurable-switch-voltage-steps.patch
+general-v4l2-iep-driver.patch
+media-0001-Add-rkvdec-Support-v5.patch
+media-0002-media-rkvdec-remove-vb2_is_busy-check-in-rkvdec_s_ct.patch
+media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch
+media-0003-rk3568-disable-hantro-h264.patch
+net-ethernet-realtek-add-r8169-LED-configuration-from-OF.patch
+regulator-add-fan53200-driver.patch
+rk3588-0010-fix-clk-divisions.patch
+rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch
+rk3588-1201-arm64-dts-rockchip-Enable-the-NPU-on-CM3588.patch
+rk35xx-montjoie-crypto-v2-rk35xx.patch
--- a/_build/uboot.patches/boot.cmd
+++ b/_build/uboot.patches/boot.cmd
--- a/_build/uboot.patches/rk3588_bl31_v1.46.elf
+++ b/_build/uboot.patches/rk3588_bl31_v1.46.elf
--- a/_build/uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin
+++ b/_build/uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin
--- a/_build/uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin
+++ b/_build/uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin
--- a/_build/upstream-url.txt
+++ b/_build/upstream-url.txt
@@ -0,0 +1 @@
+https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-6.18.6.tar.xz
--- a/atf.patches/feat-rk3588-support-rk3588.patch
+++ b/atf.patches/feat-rk3588-support-rk3588.patch
--- a/atf.patches/feat-rockchip-support-SCMI-for-clock-reset-domain.patch
+++ b/atf.patches/feat-rockchip-support-SCMI-for-clock-reset-domain.patch
@@ -1,465 +0,0 @@
-From 3bd5d90889173031e1a4177835225e3f9ffd6e49 Mon Sep 17 00:00:00 2001
-From: XiaoDong Huang <derrick.huang@rock-chips.com>
-Date: Sun, 25 Jun 2023 17:38:13 +0800
-Subject: [PATCH] feat(rockchip): support SCMI for clock/reset domain
-
-Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
-Change-Id: I5b983877a5b4e8acababbf7e0a3e2725e6479e08
---
-
-diff --git a/plat/rockchip/common/include/rockchip_sip_svc.h b/plat/rockchip/common/include/rockchip_sip_svc.h
-index 340d653..8836f9b 100644
--- a/plat/rockchip/common/include/rockchip_sip_svc.h
-+++ b/plat/rockchip/common/include/rockchip_sip_svc.h
-@@ -11,6 +11,7 @@
- #define SIP_SVC_CALL_COUNT		0x8200ff00
- #define SIP_SVC_UID			0x8200ff01
- #define SIP_SVC_VERSION			0x8200ff03
-+#define RK_SIP_SCMI_AGENT0		0x82000010
- 
- /* rockchip SiP Service Calls version numbers */
- #define RK_SIP_SVC_VERSION_MAJOR	0x0
-diff --git a/plat/rockchip/common/scmi/scmi.c b/plat/rockchip/common/scmi/scmi.c
-new file mode 100644
-index 0000000..23ea991
--- /dev/null
-+++ b/plat/rockchip/common/scmi/scmi.c
-@@ -0,0 +1,88 @@
-+/*
-+ * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ */
-+
-+#include <assert.h>
-+#include <string.h>
-+
-+#include <plat_scmi_def.h>
-+
-+#include <drivers/scmi-msg.h>
-+#include <drivers/scmi.h>
-+#include <lib/utils.h>
-+#include <lib/utils_def.h>
-+
-+#define MAX_PROTOCOL_IN_LIST		8U
-+
-+static const char vendor[] = "rockchip";
-+static const char sub_vendor[] = "";
-+
-+#pragma weak rockchip_scmi_protocol_table
-+
-+const uint8_t rockchip_scmi_protocol_table[1][MAX_PROTOCOL_IN_LIST] = {
-+	{ SCMI_PROTOCOL_ID_CLOCK,
-+	  SCMI_PROTOCOL_ID_RESET_DOMAIN,
-+	  0
-+	}
-+};
-+
-+const char *plat_scmi_vendor_name(void)
-+{
-+	return vendor;
-+}
-+
-+const char *plat_scmi_sub_vendor_name(void)
-+{
-+	return sub_vendor;
-+}
-+
-+size_t plat_scmi_protocol_count(void)
-+{
-+	unsigned int count = 0U;
-+	const uint8_t *protocol_list = rockchip_scmi_protocol_table[0];
-+
-+	while (protocol_list[count])
-+		count++;
-+
-+	return count;
-+}
-+
-+const uint8_t *plat_scmi_protocol_list(unsigned int agent_id)
-+{
-+	assert(agent_id < ARRAY_SIZE(rockchip_scmi_protocol_table));
-+
-+	return rockchip_scmi_protocol_table[agent_id];
-+}
-+
-+static struct scmi_msg_channel scmi_channel[] = {
-+	[0] = {
-+		.shm_addr = SMT_BUFFER0_BASE,
-+		.shm_size = SMT_BUF_SLOT_SIZE,
-+	},
-+
-+#ifdef SMT_BUFFER1_BASE
-+	[1] = {
-+		.shm_addr = SMT_BUFFER1_BASE,
-+		.shm_size = SMT_BUF_SLOT_SIZE,
-+	},
-+#endif
-+};
-+
-+struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id)
-+{
-+	assert(agent_id < ARRAY_SIZE(scmi_channel));
-+
-+	return &scmi_channel[agent_id];
-+}
-+
-+#pragma weak rockchip_init_scmi_server
-+
-+void rockchip_init_scmi_server(void)
-+{
-+	size_t i;
-+
-+	for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++)
-+		scmi_smt_init_agent_channel(&scmi_channel[i]);
-+}
-diff --git a/plat/rockchip/common/scmi/scmi_clock.c b/plat/rockchip/common/scmi/scmi_clock.c
-new file mode 100644
-index 0000000..4921d49
--- /dev/null
-+++ b/plat/rockchip/common/scmi/scmi_clock.c
-@@ -0,0 +1,157 @@
-+/*
-+ * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ */
-+
-+#include <drivers/scmi-msg.h>
-+#include <drivers/scmi.h>
-+
-+#include "scmi_clock.h"
-+
-+#pragma weak rockchip_scmi_clock_count
-+#pragma weak rockchip_scmi_get_clock
-+
-+size_t rockchip_scmi_clock_count(unsigned int agent_id __unused)
-+{
-+	return 0;
-+}
-+
-+rk_scmi_clock_t *rockchip_scmi_get_clock(uint32_t agent_id __unused,
-+					 uint32_t scmi_id __unused)
-+{
-+	return NULL;
-+}
-+
-+size_t plat_scmi_clock_count(unsigned int agent_id)
-+{
-+	return rockchip_scmi_clock_count(agent_id);
-+}
-+
-+const char *plat_scmi_clock_get_name(unsigned int agent_id,
-+				     unsigned int scmi_id)
-+{
-+	rk_scmi_clock_t *clock;
-+
-+	clock = rockchip_scmi_get_clock(agent_id, scmi_id);
-+	if (clock == 0)
-+		return NULL;
-+
-+	return clock->name;
-+}
-+
-+int32_t plat_scmi_clock_rates_array(unsigned int agent_id,
-+				    unsigned int scmi_id,
-+				    unsigned long *rates,
-+				    size_t *nb_elts,
-+				    uint32_t start_idx)
-+{
-+	uint32_t i;
-+	unsigned long *rate_table;
-+	rk_scmi_clock_t *clock;
-+
-+	clock = rockchip_scmi_get_clock(agent_id, scmi_id);
-+	if (clock == 0)
-+		return SCMI_NOT_FOUND;
-+
-+	rate_table = clock->rate_table;
-+	if (rate_table == 0)
-+		return SCMI_NOT_SUPPORTED;
-+
-+	if (rates == 0) {
-+		*nb_elts = clock->rate_cnt;
-+		goto out;
-+	}
-+
-+	if (start_idx + *nb_elts > clock->rate_cnt)
-+		return SCMI_OUT_OF_RANGE;
-+
-+	for (i = 0; i < *nb_elts; i++)
-+		rates[i] = rate_table[start_idx + i];
-+
-+out:
-+	return SCMI_SUCCESS;
-+}
-+
-+int32_t plat_scmi_clock_rates_by_step(unsigned int agent_id __unused,
-+				      unsigned int scmi_id __unused,
-+				      unsigned long *steps __unused)
-+{
-+	return SCMI_NOT_SUPPORTED;
-+}
-+
-+unsigned long plat_scmi_clock_get_rate(unsigned int agent_id,
-+				       unsigned int scmi_id)
-+{
-+	rk_scmi_clock_t *clock;
-+	unsigned long rate = 0;
-+
-+	clock = rockchip_scmi_get_clock(agent_id, scmi_id);
-+	if (clock == 0)
-+		return 0;
-+
-+	if (clock->clk_ops && clock->clk_ops->get_rate)
-+		rate = clock->clk_ops->get_rate(clock);
-+
-+	/* return cur_rate if no get_rate ops or get_rate return 0 */
-+	if (rate == 0)
-+		rate = clock->cur_rate;
-+
-+	return rate;
-+}
-+
-+int32_t plat_scmi_clock_set_rate(unsigned int agent_id,
-+				 unsigned int scmi_id,
-+				 unsigned long rate)
-+{
-+	rk_scmi_clock_t *clock;
-+	int32_t status = 0;
-+
-+	clock = rockchip_scmi_get_clock(agent_id, scmi_id);
-+	if (clock == 0)
-+		return SCMI_NOT_FOUND;
-+
-+	if (clock->clk_ops && clock->clk_ops->set_rate) {
-+		status = clock->clk_ops->set_rate(clock, rate);
-+		if (status == SCMI_SUCCESS)
-+			clock->cur_rate = rate;
-+	} else {
-+		status = SCMI_NOT_SUPPORTED;
-+	}
-+
-+	return status;
-+}
-+
-+int32_t plat_scmi_clock_get_state(unsigned int agent_id,
-+				  unsigned int scmi_id)
-+{
-+	rk_scmi_clock_t *clock;
-+
-+	clock = rockchip_scmi_get_clock(agent_id, scmi_id);
-+	if (clock == 0)
-+		return 0;
-+
-+	return clock->enable;
-+}
-+
-+int32_t plat_scmi_clock_set_state(unsigned int agent_id,
-+				  unsigned int scmi_id,
-+				  bool enable_not_disable)
-+{
-+	rk_scmi_clock_t *clock;
-+	int32_t status = 0;
-+
-+	clock = rockchip_scmi_get_clock(agent_id, scmi_id);
-+	if (clock == 0)
-+		return SCMI_NOT_FOUND;
-+
-+	if (clock->clk_ops && clock->clk_ops->set_status) {
-+		status = clock->clk_ops->set_status(clock, enable_not_disable);
-+		if (status == SCMI_SUCCESS)
-+			clock->enable = enable_not_disable;
-+	} else {
-+		status = SCMI_NOT_SUPPORTED;
-+	}
-+
-+	return status;
-+}
-diff --git a/plat/rockchip/common/scmi/scmi_clock.h b/plat/rockchip/common/scmi/scmi_clock.h
-new file mode 100644
-index 0000000..e640fe1
--- /dev/null
-+++ b/plat/rockchip/common/scmi/scmi_clock.h
-@@ -0,0 +1,50 @@
-+/*
-+ * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ */
-+
-+#ifndef RK_SCMI_CLOCK_H
-+#define RK_SCMI_CLOCK_H
-+
-+#include <stdint.h>
-+
-+#include <common.h>
-+
-+struct rk_scmi_clock;
-+
-+struct rk_clk_ops {
-+	unsigned long (*get_rate)(struct rk_scmi_clock *clock);
-+	int (*set_rate)(struct rk_scmi_clock *clock, unsigned long rate);
-+	int (*set_status)(struct rk_scmi_clock *clock, bool status);
-+};
-+
-+typedef struct rk_scmi_clock {
-+	char name[SCMI_CLOCK_NAME_LENGTH_MAX];
-+	uint8_t enable;
-+	int8_t is_security;
-+	uint32_t id;
-+	uint32_t rate_cnt;
-+	uint64_t cur_rate;
-+	uint32_t enable_count;
-+	const struct rk_clk_ops *clk_ops;
-+	unsigned long *rate_table;
-+} rk_scmi_clock_t;
-+
-+/*
-+ * Return number of clock controllers for an agent
-+ * @agent_id: SCMI agent ID
-+ * Return number of clock controllers
-+ */
-+size_t rockchip_scmi_clock_count(unsigned int agent_id);
-+
-+/*
-+ * Get rk_scmi_clock_t point
-+ * @agent_id: SCMI agent ID
-+ * @scmi_id: SCMI clock ID
-+ * Return a rk_scmi_clock_t point
-+ */
-+rk_scmi_clock_t *rockchip_scmi_get_clock(uint32_t agent_id,
-+					 uint32_t scmi_id);
-+
-+#endif /* RK_SCMI_CLOCK_H */
-diff --git a/plat/rockchip/common/scmi/scmi_rstd.c b/plat/rockchip/common/scmi/scmi_rstd.c
-new file mode 100644
-index 0000000..404d85e
--- /dev/null
-+++ b/plat/rockchip/common/scmi/scmi_rstd.c
-@@ -0,0 +1,74 @@
-+/*
-+ * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ */
-+
-+#include <drivers/scmi-msg.h>
-+#include <drivers/scmi.h>
-+
-+#include "scmi_rstd.h"
-+
-+#pragma weak rockchip_scmi_rstd_count
-+#pragma weak rockchip_scmi_get_rstd
-+
-+size_t rockchip_scmi_rstd_count(unsigned int agent_id __unused)
-+{
-+	return 0U;
-+}
-+
-+rk_scmi_rstd_t *rockchip_scmi_get_rstd(unsigned int agent_id __unused,
-+				       unsigned int scmi_id __unused)
-+{
-+	return NULL;
-+}
-+
-+size_t plat_scmi_rstd_count(unsigned int agent_id)
-+{
-+	return rockchip_scmi_rstd_count(agent_id);
-+}
-+
-+const char *plat_scmi_rstd_get_name(unsigned int agent_id,
-+				    unsigned int scmi_id)
-+{
-+	rk_scmi_rstd_t *rstd;
-+
-+	rstd = rockchip_scmi_get_rstd(agent_id, scmi_id);
-+	if (rstd == 0)
-+		return NULL;
-+
-+	return rstd->name;
-+}
-+
-+int32_t plat_scmi_rstd_autonomous(unsigned int agent_id,
-+				  unsigned int scmi_id,
-+				  unsigned int state)
-+{
-+	rk_scmi_rstd_t *rstd;
-+
-+	rstd = rockchip_scmi_get_rstd(agent_id, scmi_id);
-+	if (rstd == 0)
-+		return SCMI_NOT_FOUND;
-+
-+	if ((rstd->rstd_ops && rstd->rstd_ops->reset_auto) != 0)
-+		return rstd->rstd_ops->reset_auto(rstd, state);
-+	else
-+		return SCMI_NOT_SUPPORTED;
-+}
-+
-+int32_t plat_scmi_rstd_set_state(unsigned int agent_id,
-+				 unsigned int scmi_id,
-+				 bool assert_not_deassert)
-+{
-+	rk_scmi_rstd_t *rstd;
-+
-+	rstd = rockchip_scmi_get_rstd(agent_id, scmi_id);
-+	if (rstd == 0)
-+		return SCMI_NOT_FOUND;
-+
-+	if ((rstd->rstd_ops && rstd->rstd_ops->reset_explicit) != 0)
-+		return rstd->rstd_ops->reset_explicit(rstd,
-+						      assert_not_deassert);
-+	else
-+		return SCMI_NOT_SUPPORTED;
-+}
-diff --git a/plat/rockchip/common/scmi/scmi_rstd.h b/plat/rockchip/common/scmi/scmi_rstd.h
-new file mode 100644
-index 0000000..1af5881
--- /dev/null
-+++ b/plat/rockchip/common/scmi/scmi_rstd.h
-@@ -0,0 +1,45 @@
-+/*
-+ * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ */
-+
-+#ifndef RK_SCMI_RESET_DOMAIN_H
-+#define RK_SCMI_RESET_DOMAIN_H
-+
-+#include <stdint.h>
-+
-+#include <common.h>
-+
-+struct rk_scmi_rstd;
-+
-+struct rk_scmi_rstd_ops {
-+	int (*reset_auto)(struct rk_scmi_rstd *rstd, uint32_t state);
-+	int (*reset_explicit)(struct rk_scmi_rstd *rstd, bool assert_not_deassert);
-+};
-+
-+typedef struct rk_scmi_rstd {
-+	char name[SCMI_RESET_DOMAIN_ATTR_NAME_SZ];
-+	uint32_t id;
-+	uint32_t attribute;
-+	uint32_t latency;
-+	struct rk_scmi_rstd_ops *rstd_ops;
-+} rk_scmi_rstd_t;
-+
-+/*
-+ * Return number of reset domain for an agent
-+ * @agent_id: SCMI agent ID
-+ * Return number of reset domain
-+ */
-+size_t rockchip_scmi_rstd_count(unsigned int agent_id);
-+
-+/*
-+ * Get rk_scmi_rstd_t point
-+ * @agent_id: SCMI agent ID
-+ * @scmi_id: SCMI rstd ID
-+ * Return a rk_scmi_rstd_t point
-+ */
-+rk_scmi_rstd_t *rockchip_scmi_get_rstd(unsigned int agent_id,
-+				       unsigned int scmi_id);
-+
-+#endif /* RK_SCMI_RESET_DOMAIN_H */
--- a/atf.patches/rk3588-enable-crypto-function.patch
+++ b/atf.patches/rk3588-enable-crypto-function.patch
@@ -1,142 +0,0 @@
-From 3e45797b2790492e2863441e24246536a33f1efd Mon Sep 17 00:00:00 2001
-From: XiaoDong Huang <derrick.huang@rock-chips.com>
-Date: Mon, 17 Jun 2024 10:55:27 +0800
-Subject: [PATCH] feat(rk3588): enable crypto function
-
-The CPU crypto is not default on when power up, need to enable it by
-software.
-
-Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
-Change-Id: Ifee2eab55d9c13cef5f15926fb80016845e2a66d
---
-
-diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
-index dfb14e9..6d1e11e 100644
--- a/bl31/aarch64/bl31_entrypoint.S
-+++ b/bl31/aarch64/bl31_entrypoint.S
-@@ -16,6 +16,11 @@
- 	.globl	bl31_entrypoint
- 	.globl	bl31_warm_entrypoint
- 
-+#ifdef PLAT_RK_BL31_ENTRYPOINT
-+	.globl	plat_rockchip_bl31_entrypoint
-+	.globl	plat_rockchip_bl31_entrypoint_set_sp
-+#endif
-+
- 	/* -----------------------------------------------------
- 	 * bl31_entrypoint() is the cold boot entrypoint,
- 	 * executed only by the primary cpu.
-@@ -23,6 +28,10 @@
- 	 */
- 
- func bl31_entrypoint
-+#ifdef PLAT_RK_BL31_ENTRYPOINT
-+	bl	plat_rockchip_bl31_entrypoint_set_sp
-+	bl	plat_rockchip_bl31_entrypoint
-+#endif
- 	/* ---------------------------------------------------------------
- 	 * Stash the previous bootloader arguments x0 - x3 for later use.
- 	 * ---------------------------------------------------------------
-diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c
-index 83d6cad..a7c1c47 100644
--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c
-+++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c
-@@ -136,6 +136,22 @@
- 
- static __pmusramfunc void ddr_resume(void)
- {
-+	/* check the crypto function had been enabled or not */
-+	if (mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) {
-+		/* enable the crypto function */
-+		mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
-+		dsb();
-+		isb();
-+
-+		__asm__ volatile ("mov	x0, #3\n"
-+				  "dsb	sy\n"
-+				  "msr	rmr_el3, x0\n"
-+				  "1:\n"
-+				  "isb\n"
-+				  "wfi\n"
-+				  "b 1b\n");
-+	}
-+
- 	dsu_restore_early();
- }
- 
-@@ -1437,3 +1453,66 @@
- 
- 	pm_reg_rgns_init();
- }
-+
-+void bl31_entrypoint(void);
-+
-+static uint64_t boot_cpu_save[4];
-+
-+void plat_rockchip_bl31_entrypoint_set_sp(uint64_t reg0, uint64_t reg1,
-+					  uint64_t reg2, uint64_t reg3)
-+{
-+	__asm__ volatile("mov x10, %0\n" : : "r" (reg0) : );
-+
-+	reg0 = PSRAM_SP_TOP;
-+	__asm__ volatile("mov sp, %0\n" : : "r" (reg0) : );
-+
-+	__asm__ volatile("mov %0, x10\n" : "=r" (reg0) : :);
-+}
-+
-+void plat_rockchip_bl31_entrypoint(uint64_t reg0, uint64_t reg1,
-+				   uint64_t reg2, uint64_t reg3)
-+{
-+	uint32_t tmp = mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4));
-+
-+	/* check the crypto function had been enabled or not */
-+	if (tmp & BIT(4)) {
-+		/* save x0~x3 */
-+		boot_cpu_save[0] = reg0;
-+		boot_cpu_save[1] = reg1;
-+		boot_cpu_save[2] = reg2;
-+		boot_cpu_save[3] = reg3;
-+
-+		/* enable the crypto function */
-+		mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
-+
-+		/* remap pmusram to 0xffff0000 */
-+		mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001);
-+		dsb();
-+		psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT;
-+		cpuson_flags[0] = PMU_CPU_HOTPLUG;
-+		cpuson_entry_point[0] = (uintptr_t)bl31_entrypoint;
-+		dsb();
-+
-+		/* to enable the crypto function, must reset the core0 */
-+		__asm__ volatile ("mov	x0, #3\n"
-+				  "dsb	sy\n"
-+				  "msr	rmr_el3, x0\n"
-+				  "1:\n"
-+				  "isb\n"
-+				  "wfi\n"
-+				  "b 1b\n");
-+	} else {
-+		/* remap bootrom to 0xffff0000 */
-+		mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000);
-+
-+		/*
-+		 * the crypto function has been enabled,
-+		 * restore the x0~x3.
-+		 */
-+		__asm__ volatile ("ldr	x0, [%0]\n"
-+				  "ldr	x1, [%0 , 0x8]\n"
-+				  "ldr	x2, [%0 , 0x10]\n"
-+				  "ldr	x3, [%0 , 0x18]\n"
-+				  : : "r" (&boot_cpu_save[0]));
-+	}
-+}
-diff --git a/plat/rockchip/rk3588/platform.mk b/plat/rockchip/rk3588/platform.mk
-index 07eda40..3d9dc59 100644
--- a/plat/rockchip/rk3588/platform.mk
-+++ b/plat/rockchip/rk3588/platform.mk
-@@ -96,3 +96,4 @@
- 
- $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
- $(eval $(call add_define,PLAT_SKIP_DFS_TLB_DCACHE_MAINTENANCE))
-+$(eval $(call add_define,PLAT_RK_BL31_ENTRYPOINT))
--- a/atf.patches/rockchip-add-some-pm-helpers-functions.patch
+++ b/atf.patches/rockchip-add-some-pm-helpers-functions.patch
@@ -1,293 +0,0 @@
-From eb5dfe2a76180d85f33fa2e7ed5131852a003dac Mon Sep 17 00:00:00 2001
-From: XiaoDong Huang <derrick.huang@rock-chips.com>
-Date: Sun, 25 Jun 2023 19:23:07 +0800
-Subject: [PATCH] feat(rockchip): add some pm helpers functions
-
-Some power domains will be powered off when the system suspends,
-so registers in the power domain need to be save/restore.
-Now we add some functions to save/restore registers easily:
-use rockchip_alloc_region_mem to allocate memory to save/restore registers in regions;
-use rockchip_reg_rgn_save to save registers regions in regions;
-use rockchip_reg_rgn_restore to restore registers in regions;
-use rockchip_dump_reg_rgns to dump registers in regions;
-
-Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
-Change-Id: I34f909a103fbe2d51456e1d92df0be570e35e2a1
---
-
-diff --git a/plat/rockchip/common/include/plat_pm_helpers.h b/plat/rockchip/common/include/plat_pm_helpers.h
-new file mode 100644
-index 0000000..2204a65
--- /dev/null
-+++ b/plat/rockchip/common/include/plat_pm_helpers.h
-@@ -0,0 +1,51 @@
-+/*
-+ * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ */
-+
-+#ifndef PLAT_PM_HELPERS_H
-+#define PLAT_PM_HELPERS_H
-+
-+#include <stdint.h>
-+
-+/**
-+ * Use this macro to define a register region.
-+ * start: start offset from the base address.
-+ * end: end offset from the base address.
-+ * stride: stride of registers in region.
-+ * base: base address of registers in region.
-+ * wmsk: write mask of registers in region.
-+ */
-+#define REG_REGION(_start, _end, _stride, _base, _wmsk)	\
-+{							\
-+	.start = (_base) + (_start),			\
-+	.end   = (_base) + (_end),			\
-+	.stride   = _stride,				\
-+	.wmsk  = _wmsk					\
-+}
-+
-+struct reg_region {
-+	/* Start address of region */
-+	uint32_t start;
-+	/* End address of region */
-+	uint32_t end;
-+	/* Stride of registers in region */
-+	uint32_t stride;
-+	/* Write mask of registers in region */
-+	uint32_t wmsk;
-+	/* Buffer to save/restore registers in region */
-+	uint32_t *buf;
-+};
-+
-+void rockchip_alloc_region_mem(struct reg_region *rgns, uint32_t rgn_num);
-+void rockchip_reg_rgn_save(struct reg_region *rgns, uint32_t rgn_num);
-+void rockchip_reg_rgn_restore(struct reg_region *rgns, uint32_t rgn_num);
-+void rockchip_reg_rgn_restore_reverse(struct reg_region *rgns, uint32_t rgn_num);
-+void rockchip_regs_dump(uint32_t base,
-+			uint32_t start_offset,
-+			uint32_t end_offset,
-+			uint32_t stride);
-+void rockchip_dump_reg_rgns(struct reg_region *rgns, uint32_t rgn_num);
-+
-+#endif /* PLAT_PM_HELPERS_H */
-diff --git a/plat/rockchip/common/plat_pm_helpers.c b/plat/rockchip/common/plat_pm_helpers.c
-new file mode 100644
-index 0000000..191b0ca
--- /dev/null
-+++ b/plat/rockchip/common/plat_pm_helpers.c
-@@ -0,0 +1,213 @@
-+/*
-+ * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ */
-+
-+#include <assert.h>
-+#include <errno.h>
-+
-+#include <arch_helpers.h>
-+#include <bl31/bl31.h>
-+#include <common/debug.h>
-+#include <drivers/console.h>
-+#include <drivers/delay_timer.h>
-+#include <lib/mmio.h>
-+#include <plat/common/platform.h>
-+#include <platform_def.h>
-+
-+#include <plat_pm_helpers.h>
-+
-+#define ROCKCHIP_PM_REG_REGION_MEM_LEN	(ROCKCHIP_PM_REG_REGION_MEM_SIZE / sizeof(uint32_t))
-+
-+/* REG region */
-+#define RGN_LEN(_rgn)		(((_rgn)->end - (_rgn)->start) / (_rgn)->stride + 1)
-+
-+#ifndef ROCKCHIP_PM_REG_REGION_MEM_SIZE
-+#define ROCKCHIP_PM_REG_REGION_MEM_SIZE		0
-+#endif
-+
-+#ifdef ROCKCHIP_REG_RGN_MEM_BASE
-+static uint32_t *region_mem = (uint32_t *)ROCKCHIP_REG_RGN_MEM_BASE;
-+#else
-+static uint32_t region_mem[ROCKCHIP_PM_REG_REGION_MEM_LEN];
-+#endif
-+
-+static int region_mem_idx;
-+
-+static int alloc_region_mem(uint32_t *buf, int max_len,
-+			    struct reg_region *rgns, uint32_t rgn_num)
-+{
-+	int i;
-+	int total_len = 0, len = 0;
-+	struct reg_region *r = rgns;
-+
-+	assert(buf && rgns && rgn_num);
-+
-+	for (i = 0; i < rgn_num; i++, r++) {
-+		if (total_len < max_len)
-+			r->buf = &buf[total_len];
-+
-+		len = RGN_LEN(r);
-+		total_len += len;
-+	}
-+
-+	if (total_len > max_len) {
-+		ERROR("%s The buffer remain length:%d is too small for region:0x%x, at least %d\n",
-+		      __func__, max_len, rgns[0].start, total_len);
-+		panic();
-+	}
-+
-+	return total_len;
-+}
-+
-+/**
-+ * Alloc memory to reg_region->buf from region_mem.
-+ * @rgns - struct reg_region array.
-+ * @rgn_num - struct reg_region array length.
-+ */
-+void rockchip_alloc_region_mem(struct reg_region *rgns, uint32_t rgn_num)
-+{
-+	int max_len = 0, len;
-+
-+	assert(rgns && rgn_num);
-+
-+	max_len = ROCKCHIP_PM_REG_REGION_MEM_LEN - region_mem_idx;
-+
-+	len = alloc_region_mem(region_mem + region_mem_idx, max_len,
-+			       rgns, rgn_num);
-+
-+	region_mem_idx += len;
-+}
-+
-+/**
-+ * Save (reg_region->start ~ reg_region->end) to reg_region->buf.
-+ * @rgns - struct reg_region array.
-+ * @rgn_num - struct reg_region array length.
-+ */
-+void rockchip_reg_rgn_save(struct reg_region *rgns, uint32_t rgn_num)
-+{
-+	struct reg_region *r;
-+	uint32_t addr;
-+	int i, j;
-+
-+	assert(rgns && rgn_num);
-+
-+	for (i = 0; i < rgn_num; i++) {
-+		r = &rgns[i];
-+		for (j = 0, addr = r->start; addr <= r->end; addr += r->stride, j++)
-+			r->buf[j] = mmio_read_32(addr);
-+	}
-+}
-+
-+/**
-+ * Restore reg_region->buf to (reg_region->start ~ reg_region->end).
-+ * @rgns - struct reg_region array.
-+ * @rgn_num - struct reg_region array length.
-+ */
-+void rockchip_reg_rgn_restore(struct reg_region *rgns, uint32_t rgn_num)
-+{
-+	struct reg_region *r;
-+	uint32_t addr;
-+	int i, j;
-+
-+	assert(rgns && rgn_num);
-+
-+	for (i = 0; i < rgn_num; i++) {
-+		r = &rgns[i];
-+		for (j = 0, addr = r->start; addr <= r->end; addr += r->stride, j++)
-+			mmio_write_32(addr, r->buf[j] | r->wmsk);
-+
-+		dsb();
-+	}
-+}
-+
-+/**
-+ * Restore reg_region->buf to (reg_region->start ~ reg_region->end) reversely.
-+ * @rgns - struct reg_region array.
-+ * @rgn_num - struct reg_region array length.
-+ */
-+void rockchip_reg_rgn_restore_reverse(struct reg_region *rgns, uint32_t rgn_num)
-+{
-+	struct reg_region *r;
-+	uint32_t addr;
-+	int i, j;
-+
-+	assert(rgns && rgn_num);
-+
-+	for (i = rgn_num - 1; i >= 0; i--) {
-+		r = &rgns[i];
-+		j = RGN_LEN(r) - 1;
-+		for (addr = r->end; addr >= r->start; addr -= r->stride, j--)
-+			mmio_write_32(addr, r->buf[j] | r->wmsk);
-+
-+		dsb();
-+	}
-+}
-+
-+static void rockchip_print_hex(uint32_t val)
-+{
-+	int i;
-+	unsigned char tmp;
-+
-+	putchar('0');
-+	putchar('x');
-+	for (i = 0; i < 8; val <<= 4, ++i) {
-+		tmp = (val & 0xf0000000) >> 28;
-+		if (tmp < 10)
-+			putchar('0' + tmp);
-+		else
-+			putchar('a' + tmp - 10);
-+	}
-+}
-+
-+/**
-+ * Dump registers (base + start_offset ~ base + end_offset)
-+ * @base - the base addr of the register.
-+ * @start_offset - the start offset to dump.
-+ * @end_offset - the end offset to dump.
-+ * @stride - the stride of the registers.
-+ */
-+void rockchip_regs_dump(uint32_t base,
-+			uint32_t start_offset,
-+			uint32_t end_offset,
-+			uint32_t stride)
-+{
-+	uint32_t i;
-+
-+	for (i = start_offset; i <= end_offset; i += stride) {
-+		if ((i - start_offset) % 16 == 0) {
-+			putchar('\n');
-+			rockchip_print_hex(base + i);
-+			putchar(':');
-+			putchar(' ');
-+			putchar(' ');
-+			putchar(' ');
-+			putchar(' ');
-+		}
-+		rockchip_print_hex(mmio_read_32(base + i));
-+		putchar(' ');
-+		putchar(' ');
-+		putchar(' ');
-+		putchar(' ');
-+	}
-+	putchar('\n');
-+}
-+
-+/**
-+ * Dump reg regions
-+ * @rgns - struct reg_region array.
-+ * @rgn_num - struct reg_region array length.
-+ */
-+void rockchip_dump_reg_rgns(struct reg_region *rgns, uint32_t rgn_num)
-+{
-+	struct reg_region *r;
-+	int i;
-+
-+	assert(rgns && rgn_num);
-+
-+	for (i = 0; i < rgn_num; i++) {
-+		r = &rgns[i];
-+		rockchip_regs_dump(0x0, r->start, r->end, r->stride);
-+	}
-+}
--- a/cmd/gokr-build-kernel/build.go
+++ b/cmd/gokr-build-kernel/build.go
@@ -1,178 +0,0 @@
-package main
-
-import (
-	"fmt"
-	"io"
-	"log"
-	"net/http"
-	"os"
-	"os/exec"
-	"path/filepath"
-	"runtime"
-	"strconv"
-	"strings"
-
-	_ "embed"
-)
-
-//go:embed config.txt
-var configContents []byte
-
-// see https://www.kernel.org/releases.json
-var latest = "https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-6.10.5.tar.xz"
-
-func downloadKernel() error {
-	out, err := os.Create(filepath.Base(latest))
-	if err != nil {
-		return err
-	}
-	defer out.Close()
-	resp, err := http.Get(latest)
-	if err != nil {
-		return err
-	}
-	defer resp.Body.Close()
-	if got, want := resp.StatusCode, http.StatusOK; got != want {
-		return fmt.Errorf("unexpected HTTP status code for %s: got %d, want %d", latest, got, want)
-	}
-	if _, err := io.Copy(out, resp.Body); err != nil {
-		return err
-	}
-	return out.Close()
-}
-
-func applyPatches(srcdir string) error {
-	patches, err := filepath.Glob("kernel.patches/*.patch")
-	if err != nil {
-		return err
-	}
-	for _, patch := range patches {
-		log.Printf("applying patch %q", patch)
-		f, err := os.Open(patch)
-		if err != nil {
-			return err
-		}
-		defer f.Close()
-		cmd := exec.Command("patch", "-p1")
-		cmd.Dir = srcdir
-		cmd.Stdin = f
-		cmd.Stdout = os.Stdout
-		cmd.Stderr = os.Stderr
-		if err := cmd.Run(); err != nil {
-			return err
-		}
-		f.Close()
-	}
-
-	return nil
-}
-
-func compile() error {
-	defconfig := exec.Command("make", "ARCH=arm64", "defconfig")
-	defconfig.Stdout = os.Stdout
-	defconfig.Stderr = os.Stderr
-	if err := defconfig.Run(); err != nil {
-		return fmt.Errorf("make defconfig: %v", err)
-	}
-
-	f, err := os.OpenFile(".config", os.O_CREATE|os.O_APPEND|os.O_WRONLY, 0644)
-	if err != nil {
-		return err
-	}
-	defer f.Close()
-	if _, err := f.Write(configContents); err != nil {
-		return err
-	}
-	if err := f.Close(); err != nil {
-		return err
-	}
-
-	olddefconfig := exec.Command("make", "ARCH=arm64", "olddefconfig")
-	olddefconfig.Stdout = os.Stdout
-	olddefconfig.Stderr = os.Stderr
-	if err := olddefconfig.Run(); err != nil {
-		return fmt.Errorf("make olddefconfig: %v", err)
-	}
-
-	make := exec.Command("make", "Image", "dtbs", "-j"+strconv.Itoa(runtime.NumCPU()))
-	make.Env = append(os.Environ(),
-		"ARCH=arm64",
-		"CROSS_COMPILE=aarch64-linux-gnu-",
-		"KBUILD_BUILD_USER=gokrazy",
-		"KBUILD_BUILD_HOST=docker",
-		"KBUILD_BUILD_TIMESTAMP=Wed Mar  1 20:57:29 UTC 2017",
-	)
-	make.Stdout = os.Stdout
-	make.Stderr = os.Stderr
-	if err := make.Run(); err != nil {
-		return fmt.Errorf("make: %v", err)
-	}
-
-	return nil
-}
-
-func copyFile(dest, src string) error {
-	out, err := os.Create(dest)
-	if err != nil {
-		return err
-	}
-	defer out.Close()
-
-	in, err := os.Open(src)
-	if err != nil {
-		return err
-	}
-	defer in.Close()
-
-	if _, err := io.Copy(out, in); err != nil {
-		return err
-	}
-
-	st, err := in.Stat()
-	if err != nil {
-		return err
-	}
-	if err := out.Chmod(st.Mode()); err != nil {
-		return err
-	}
-	return out.Close()
-}
-
-func main() {
-	log.Printf("downloading kernel source: %s", latest)
-	if err := downloadKernel(); err != nil {
-		log.Fatal(err)
-	}
-
-	log.Printf("unpacking kernel source")
-	untar := exec.Command("tar", "xf", filepath.Base(latest))
-	untar.Stdout = os.Stdout
-	untar.Stderr = os.Stderr
-	if err := untar.Run(); err != nil {
-		log.Fatalf("untar: %v", err)
-	}
-
-	srcdir := strings.TrimSuffix(filepath.Base(latest), ".tar.xz")
-
-	log.Printf("applying patches")
-	if err := applyPatches(srcdir); err != nil {
-		log.Fatal(err)
-	}
-
-	if err := os.Chdir(srcdir); err != nil {
-		log.Fatal(err)
-	}
-
-	log.Printf("compiling kernel")
-	if err := compile(); err != nil {
-		log.Fatal(err)
-	}
-
-	if err := copyFile("/tmp/buildresult/vmlinuz", "arch/arm64/boot/Image"); err != nil {
-		log.Fatal(err)
-	}
-
-	if err := copyFile("/tmp/buildresult/rk3588-friendlyelec-cm3588-nas.dtb", "arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dtb"); err != nil {
-		log.Fatal(err)
-	}
-}
--- a/cmd/gokr-rebuild-kernel/indocker.go
+++ b/cmd/gokr-rebuild-kernel/indocker.go
@@ -0,0 +1,374 @@
+package main
+
+import (
+	"flag"
+	"fmt"
+	"io"
+	"log"
+	"net/http"
+	"net/url"
+	"os"
+	"os/exec"
+	"path/filepath"
+	"runtime"
+	"strconv"
+	"strings"
+)
+
+var (
+	firmware       = []string{"arm/mali/arch10.8/mali_csffw.bin", "rtl_nic/rtl8125b-2.fw"}
+	firmwareDir, _ = filepath.Abs("firmware")
+)
+
+func downloadKernel(latest string) error {
+	if _, err := os.Stat(filepath.Base(latest)); err == nil {
+		return nil
+	}
+	out, err := os.Create(filepath.Base(latest))
+	if err != nil {
+		return err
+	}
+	defer out.Close()
+	if kernel, err := os.Open("/tmp/buildresult/" + filepath.Base(latest)); err == nil {
+		defer kernel.Close()
+		if _, err := io.Copy(out, kernel); err != nil {
+			return err
+		}
+		return out.Close()
+	}
+	resp, err := http.Get(latest)
+	if err != nil {
+		return err
+	}
+	defer resp.Body.Close()
+	if got, want := resp.StatusCode, http.StatusOK; got != want {
+		return fmt.Errorf("unexpected HTTP status code for %s: got %d, want %d", latest, got, want)
+	}
+	if _, err := io.Copy(out, resp.Body); err != nil {
+		return err
+	}
+	return out.Close()
+}
+
+func downloadWhence() (map[string]string, error) {
+	whenceMap := make(map[string]string)
+	uri := "https://gitlab.com/api/v4/projects/48890189/repository/files/WHENCE/raw?ref=main"
+	resp, err := http.Get(uri)
+	if err != nil {
+		return whenceMap, err
+	}
+	defer resp.Body.Close()
+	whenceBytes, err := io.ReadAll(resp.Body)
+	if err != nil {
+		return whenceMap, err
+	}
+	whence := strings.Split(string(whenceBytes), "\n")
+	for _, line := range whence {
+		if file, ok := strings.CutPrefix(line, "File: "); ok {
+			whenceMap[file] = file
+		}
+		if file, ok := strings.CutPrefix(line, "RawFile: "); ok {
+			whenceMap[file] = file
+		}
+		if l, ok := strings.CutPrefix(line, "Link: "); ok {
+			if link, file, ok := strings.Cut(l, " -> "); ok {
+				dest := filepath.Join(filepath.Dir(link), file)
+				whenceMap[link] = dest
+			}
+		}
+	}
+	return whenceMap, nil
+}
+
+func downloadFirmware() ([]string, error) {
+	firmwarePaths := make([]string, 0, len(firmware))
+	whence, err := downloadWhence()
+	if err != nil {
+		return firmwarePaths, err
+	}
+	for _, f := range firmware {
+		folder := filepath.Dir(f)
+		path, ok := whence[f]
+		if !ok {
+			return firmwarePaths, fmt.Errorf("firmware %q not found", f)
+		}
+
+		firmwarePaths = append(firmwarePaths, f)
+
+		log.Printf("downloading firmware: %q to %q", path, f)
+
+		os.MkdirAll(filepath.Join("firmware", folder), 0o777)
+		out, err := os.Create(filepath.Join("firmware", f))
+		if err != nil {
+			return firmwarePaths, err
+		}
+		defer out.Close()
+		uri := "https://gitlab.com/api/v4/projects/48890189/repository/files/" + url.PathEscape(path) + "/raw?ref=main"
+		resp, err := http.Get(uri)
+		if err != nil {
+			return firmwarePaths, err
+		}
+		defer resp.Body.Close()
+		if got, want := resp.StatusCode, http.StatusOK; got != want {
+			return firmwarePaths, fmt.Errorf("unexpected HTTP status code for %s: got %d, want %d", uri, got, want)
+		}
+		if _, err := io.Copy(out, resp.Body); err != nil {
+			return firmwarePaths, err
+		}
+		if err := out.Close(); err != nil {
+			return firmwarePaths, err
+		}
+		resp.Body.Close()
+	}
+	return firmwarePaths, nil
+}
+
+func applyPatches(srcdir string) error {
+	patches, err := filepath.Glob("*.patch")
+	if err != nil {
+		return err
+	}
+
+	for _, patch := range patches {
+		log.Printf("applying patch %q", patch)
+		f, err := os.Open(patch)
+		if err != nil {
+			return err
+		}
+		defer f.Close()
+		cmd := exec.Command("patch", "-p1")
+		cmd.Dir = srcdir
+		cmd.Stdin = f
+		cmd.Stdout = os.Stdout
+		cmd.Stderr = os.Stderr
+		if err := cmd.Run(); err != nil {
+			return err
+		}
+		f.Close()
+	}
+
+	return nil
+}
+
+func compile(cross, flavor string, firmwarePaths []string) error {
+	defconfig := exec.Command("make", "ARCH="+os.Getenv("ARCH"), "defconfig")
+	if flavor == "defconfig" {
+		defconfig = exec.Command("make", "ARCH="+os.Getenv("ARCH"), "olddefconfig")
+		cpConfig := exec.Command("cp", "/usr/_src/defconfig", ".config")
+		cpConfig.Stdout = os.Stdout
+		cpConfig.Stderr = os.Stderr
+		if err := cpConfig.Run(); err != nil {
+			return fmt.Errorf("make cpConfig: %v", err)
+		}
+	} else if flavor == "raspberrypi" {
+		// TODO(https://github.com/gokrazy/gokrazy/issues/223): is it
+		// necessary/desirable to switch to bcm2712_defconfig?
+		defconfig = exec.Command("make", "ARCH=arm64", "bcm2711_defconfig")
+	} else if strings.HasSuffix(flavor, "_defconfig") {
+		defconfig = exec.Command("make", "ARCH="+os.Getenv("ARCH"), flavor)
+	}
+
+	defconfig.Stdout = os.Stdout
+	defconfig.Stderr = os.Stderr
+	if err := defconfig.Run(); err != nil {
+		return fmt.Errorf("make defconfig: %v", err)
+	}
+
+	// Change answers from mod to no if possible, i.e. disable all modules so
+	// that we end up with a minimal set of modules (from the config addendum).
+	mod2noconfig := exec.Command("make", "mod2noconfig")
+	mod2noconfig.Stdout = os.Stdout
+	mod2noconfig.Stderr = os.Stderr
+	if err := mod2noconfig.Run(); err != nil {
+		return fmt.Errorf("make mod2noconfig: %v", err)
+	}
+
+	f, err := os.OpenFile(".config", os.O_APPEND|os.O_WRONLY, 0o644)
+	if err != nil {
+		return err
+	}
+	defer f.Close()
+	addendum, err := os.ReadFile("/usr/src/config.addendum.txt")
+	if err != nil {
+		return err
+	}
+	if _, err := f.Write(addendum); err != nil {
+		return err
+	}
+	if len(firmwarePaths) > 0 {
+		fmt.Fprintf(f, "CONFIG_EXTRA_FIRMWARE=%q\n", strings.Join(firmwarePaths, " "))
+		fmt.Fprintf(f, "CONFIG_EXTRA_FIRMWARE_DIR=%q\n", firmwareDir)
+	}
+
+	if err := f.Close(); err != nil {
+		return err
+	}
+
+	olddefconfig := exec.Command("make", "olddefconfig")
+	olddefconfig.Stdout = os.Stdout
+	olddefconfig.Stderr = os.Stderr
+	if err := olddefconfig.Run(); err != nil {
+		return fmt.Errorf("make olddefconfig: %v", err)
+	}
+
+	env := append(os.Environ(),
+		"KBUILD_BUILD_USER=gokrazy",
+		"KBUILD_BUILD_HOST=docker",
+		"KBUILD_BUILD_TIMESTAMP=Wed Mar  1 20:57:29 UTC 2017",
+	)
+	make := exec.Command("make", "bzImage", "modules", "-j"+strconv.Itoa(runtime.NumCPU()))
+	if cross == "arm64" {
+		make = exec.Command("make", "Image.gz", "dtbs", "modules", "-j"+strconv.Itoa(runtime.NumCPU()))
+	}
+	make.Env = env
+	make.Stdout = os.Stdout
+	make.Stderr = os.Stderr
+	if err := make.Run(); err != nil {
+		return fmt.Errorf("make: %v", err)
+	}
+
+	make = exec.Command("make", "INSTALL_MOD_PATH=/tmp/buildresult", "modules_install", "-j"+strconv.Itoa(runtime.NumCPU()))
+	make.Env = env
+	make.Stdout = os.Stdout
+	make.Stderr = os.Stderr
+	if err := make.Run(); err != nil {
+		return fmt.Errorf("make: %v", err)
+	}
+
+	make = exec.Command("make", "INSTALL_DTBS_PATH=/tmp/buildresult/dtbs", "dtbs_install", "-j"+strconv.Itoa(runtime.NumCPU()))
+	make.Env = env
+	make.Stdout = os.Stdout
+	make.Stderr = os.Stderr
+	if err := make.Run(); err != nil {
+		return fmt.Errorf("make: %v", err)
+	}
+
+	return nil
+}
+
+func indockerMain() {
+	cross := flag.String("cross",
+		"",
+		"if non-empty, cross-compile for the specified arch (one of 'arm64')")
+
+	flavor := flag.String("flavor",
+		"vanilla",
+		"which kernel flavor to build. one of vanilla (kernel.org) or raspberrypi (https://github.com/raspberrypi/linux/tags)")
+	persistent := flag.Bool("persistent", false, "Mounts a folder into the docker container to persist kernel source for debugging")
+
+	flag.Parse()
+	latest := flag.Arg(0)
+	if latest == "" {
+		log.Fatalf("syntax: %s <upstream-URL>", os.Args[0])
+	}
+	log.Printf("downloading kernel source: %s", latest)
+	err := downloadKernel(latest)
+	if err != nil {
+		log.Fatal(err)
+	}
+
+	srcdir := strings.TrimSuffix(filepath.Base(latest), ".tar.gz")
+	srcdir = strings.TrimSuffix(srcdir, ".tar.xz")
+	if *flavor != "vanilla" && strings.HasPrefix(latest, "https://github.com/") {
+		s := strings.SplitN(latest, "/", 6)
+		if len(s) < 6 {
+			srcdir = "linux-" + srcdir
+		} else {
+			srcdir = s[4] + "-" + srcdir
+		}
+	}
+
+	if *persistent {
+		if _, err = os.Stat(srcdir); err == nil {
+			err = os.ErrExist
+		} else {
+			err = nil
+		}
+	}
+	unpacked := false
+	if err == nil {
+		log.Printf("unpacking kernel source")
+		untar := exec.Command("tar", "xf", filepath.Base(latest))
+		untar.Stdout = os.Stdout
+		untar.Stderr = os.Stderr
+		if err := untar.Run(); err != nil {
+			log.Fatalf("untar: %v", err)
+		}
+		unpacked = true
+	}
+	srcFiles, err := filepath.Glob("/usr/_src/*")
+	if err != nil {
+		log.Fatalf("failed to find source files: %v", err)
+	}
+	for _, fileName := range srcFiles {
+		file, err := os.OpenFile(fileName, os.O_CREATE|os.O_RDWR, 0o644)
+		if err != nil {
+			log.Fatalf("Unable to open source file for writing: %s", filepath.Base(fileName))
+		}
+		newFile, err := os.OpenFile(filepath.Base(fileName), os.O_CREATE|os.O_RDWR, 0o644)
+		if err != nil {
+			log.Fatalf("Unable to open source file for writing: %s", filepath.Base(fileName))
+		}
+		_, err = io.Copy(newFile, file)
+		if err != nil {
+			log.Fatalf("Error when copying file %v: %v", fileName, err)
+		}
+		file.Close()
+		newFile.Close()
+	}
+
+	log.Printf("applying patches")
+	if unpacked {
+		if err := applyPatches(srcdir); err != nil {
+			log.Fatal(err)
+		}
+	}
+	firmwarePaths, err := downloadFirmware()
+	if err != nil {
+		log.Fatal(err)
+	}
+
+	if err := os.Chdir(srcdir); err != nil {
+		log.Fatal(err)
+	}
+
+	if *cross == "arm64" {
+		log.Printf("exporting ARCH=arm64, CROSS_COMPILE=aarch64-linux-gnu-")
+		os.Setenv("ARCH", "arm64")
+		os.Setenv("CROSS_COMPILE", "aarch64-linux-gnu-")
+	}
+
+	log.Printf("compiling kernel")
+	if err := compile(*cross, *flavor, firmwarePaths); err != nil {
+		log.Fatal(err)
+	}
+
+	if *cross == "arm64" {
+		if err := copyFile("/tmp/buildresult/vmlinuz", "arch/arm64/boot/Image"); err != nil {
+			log.Fatal(err)
+		}
+		if err := copyFile("/tmp/buildresult/vmlinuz.config", ".config"); err != nil {
+			log.Fatal(err)
+		}
+
+		dtbos, err := filepath.Glob("arch/arm64/boot/dts/overlays/*.dtbo")
+		if err != nil {
+			log.Fatal(err)
+		}
+		if _, err = os.Stat("arch/arm64/boot/dts/overlays/overlay_map.dtb"); err == nil {
+			dtbos = append(dtbos, "arch/arm64/boot/dts/overlays/overlay_map.dtb")
+		}
+		if err := os.MkdirAll("/tmp/buildresult/overlays", 0o755); err != nil {
+			log.Fatal(err)
+		}
+		for _, fn := range dtbos {
+			if err := copyFile(filepath.Join("/tmp/buildresult/overlays/", filepath.Base(fn)), fn); err != nil {
+				log.Fatal(err)
+			}
+		}
+	} else {
+		if err := copyFile("/tmp/buildresult/vmlinuz", "arch/x86/boot/bzImage"); err != nil {
+			log.Fatal(err)
+		}
+	}
+}
--- a/cmd/gokr-rebuild-kernel/kernel.go
+++ b/cmd/gokr-rebuild-kernel/kernel.go
@@ -1,282 +0,0 @@
-package main
-
-import (
-	"flag"
-	"fmt"
-	"io"
-	"io/ioutil"
-	"log"
-	"os"
-	"os/exec"
-	"os/user"
-	"path/filepath"
-	"strings"
-	"text/template"
-)
-
-const dockerFileContents = `
-FROM debian:bullseye
-
-RUN apt-get update && apt-get install -y crossbuild-essential-arm64 bc libssl-dev bison flex
-RUN mkdir -p /usr/src/kernel.patches
-
-COPY gokr-build-kernel /usr/bin/gokr-build-kernel
-{{- range $idx, $path := .Patches }}
-COPY {{ $path }} /usr/src/{{ $path }}
-{{- end }}
-
-RUN echo 'builduser:x:{{ .Uid }}:{{ .Gid }}:nobody:/:/bin/sh' >> /etc/passwd && \
-    chown -R {{ .Uid }}:{{ .Gid }} /usr/src
-
-USER builduser
-WORKDIR /usr/src
-ENTRYPOINT /usr/bin/gokr-build-kernel
-`
-
-var dockerFileTmpl = template.Must(template.New("dockerfile").
-	Funcs(map[string]interface{}{
-		"basename": func(path string) string {
-			return filepath.Base(path)
-		},
-	}).
-	Parse(dockerFileContents))
-
-var patchFiles = []string{
-	"kernel.patches/0001-dt-bindings-arm-rockchip-Add-FriendlyElec-CM3588-NAS.patch",
-	"kernel.patches/0002-arm64-dts-rockchip-Add-FriendlyElec-CM3588-NAS-board.patch",
-	"kernel.patches/0010-fix-clk-divisions.patch",
-	"kernel.patches/0011-irqchip-fix-its-timeout-issue.patch",
-	"kernel.patches/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch",
-	"kernel.patches/0024-RK3588-Add-Crypto-Support.patch",
-	"kernel.patches/0025-RK3588-Add-HW-RNG-Support.patch",
-	"kernel.patches/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch",
-	"kernel.patches/0027-RK3588-Add-rkvdec2-Support-v3.patch",
-	"kernel.patches/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch",
-	"kernel.patches/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch",
-	"kernel.patches/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch",
-	"kernel.patches/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch",
-	"kernel.patches/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch",
-	"kernel.patches/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch",
-	"kernel.patches/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch",
-	"kernel.patches/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch",
-	"kernel.patches/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch",
-	"kernel.patches/0170-drm-rockchip-vop2-add-clocks-reset-support.patch",
-	"kernel.patches/0801-wireless-add-bcm43752.patch",
-	"kernel.patches/0802-wireless-add-clk-property.patch",
-	"kernel.patches/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch",
-	"kernel.patches/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch",
-	"kernel.patches/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch",
-	"kernel.patches/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch",
-	"kernel.patches/1015-board-rock5b-automatic-fan-control.patch",
-	"kernel.patches/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch",
-	"kernel.patches/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch",
-	"kernel.patches/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch",
-	"kernel.patches/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch",
-	"kernel.patches/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch",
-	"kernel.patches/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch",
-	"kernel.patches/1040-board-khadas-edge2-add-nodes.patch",
-	"kernel.patches/1041-board-khadas-edge2-mcu.patch",
-	"kernel.patches/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch",
-}
-
-func copyFile(dest, src string) error {
-	out, err := os.Create(dest)
-	if err != nil {
-		return err
-	}
-	defer out.Close()
-
-	in, err := os.Open(src)
-	if err != nil {
-		return err
-	}
-	defer in.Close()
-
-	if _, err := io.Copy(out, in); err != nil {
-		return err
-	}
-
-	st, err := in.Stat()
-	if err != nil {
-		return err
-	}
-	if err := out.Chmod(st.Mode()); err != nil {
-		return err
-	}
-	return out.Close()
-}
-
-var gopath = mustGetGopath()
-
-func mustGetGopath() string {
-	gopathb, err := exec.Command("go", "env", "GOPATH").Output()
-	if err != nil {
-		log.Panic(err)
-	}
-	return strings.TrimSpace(string(gopathb))
-}
-
-func find(filename string) (string, error) {
-	if _, err := os.Stat(filename); err == nil {
-		return filename, nil
-	}
-
-	path := filepath.Join(gopath, "src", "github.com", "lordwelch", "gokrazy-cm3588-kernel", filename)
-	if _, err := os.Stat(path); err == nil {
-		return path, nil
-	}
-
-	return "", fmt.Errorf("could not find file %q (looked in . and %s)", filename, path)
-}
-
-func getContainerExecutable() (string, error) {
-	// Probe podman first, because the docker binary might actually
-	// be a thin podman wrapper with podman behavior.
-	choices := []string{"podman", "docker"}
-	for _, exe := range choices {
-		p, err := exec.LookPath(exe)
-		if err != nil {
-			continue
-		}
-		resolved, err := filepath.EvalSymlinks(p)
-		if err != nil {
-			return "", err
-		}
-		return resolved, nil
-	}
-	return "", fmt.Errorf("none of %v found in $PATH", choices)
-}
-
-func main() {
-	var overwriteContainerExecutable = flag.String("overwrite_container_executable",
-		"",
-		"E.g. docker or podman to overwrite the automatically detected container executable")
-	flag.Parse()
-	executable, err := getContainerExecutable()
-	if err != nil {
-		log.Fatal(err)
-	}
-	if *overwriteContainerExecutable != "" {
-		executable = *overwriteContainerExecutable
-	}
-	execName := filepath.Base(executable)
-	// We explicitly use /tmp, because Docker only allows volume mounts under
-	// certain paths on certain platforms, see
-	// e.g. https://docs.docker.com/docker-for-mac/osxfs/#namespaces for macOS.
-	tmp, err := ioutil.TempDir("/tmp", "gokr-rebuild-kernel")
-	if err != nil {
-		log.Fatal(err)
-	}
-	defer os.RemoveAll(tmp)
-
-	cmd := exec.Command("go", "build", "-o", tmp, "github.com/lordwelch/gokrazy-cm3588-kernel/cmd/gokr-build-kernel")
-	cmd.Env = append(os.Environ(), "GOOS=linux", "CGO_ENABLED=0")
-	cmd.Stderr = os.Stderr
-	if err := cmd.Run(); err != nil {
-		log.Fatalf("%v: %v", cmd.Args, err)
-	}
-
-	buildPath := filepath.Join(tmp, "gokr-build-kernel")
-
-	var patchPaths []string
-	for _, filename := range patchFiles {
-		path, err := find(filename)
-		if err != nil {
-			log.Fatal(err)
-		}
-		patchPaths = append(patchPaths, path)
-	}
-
-	kernelPath, err := find("vmlinuz")
-	if err != nil {
-		log.Fatal(err)
-	}
-	dtbPath, err := find("rk3588-friendlyelec-cm3588-nas.dtb")
-	if err != nil {
-		log.Fatal(err)
-	}
-	err = os.MkdirAll(filepath.Join(tmp, "kernel.patches"), 0750)
-	if err != nil {
-		log.Fatal(err)
-	}
-	// Copy all files into the temporary directory so that docker
-	// includes them in the build context.
-	for _, path := range patchPaths {
-		if err := copyFile(filepath.Join(tmp, path), path); err != nil {
-			log.Fatal(err)
-		}
-	}
-
-	u, err := user.Current()
-	if err != nil {
-		log.Fatal(err)
-	}
-	dockerFile, err := os.Create(filepath.Join(tmp, "Dockerfile"))
-	if err != nil {
-		log.Fatal(err)
-	}
-
-	if err := dockerFileTmpl.Execute(dockerFile, struct {
-		Uid       string
-		Gid       string
-		BuildPath string
-		Patches   []string
-	}{
-		Uid:       u.Uid,
-		Gid:       u.Gid,
-		BuildPath: buildPath,
-		Patches:   patchFiles,
-	}); err != nil {
-		log.Fatal(err)
-	}
-
-	if err := dockerFile.Close(); err != nil {
-		log.Fatal(err)
-	}
-
-	log.Printf("building %s container for kernel compilation", execName)
-
-	dockerBuild := exec.Command(execName,
-		"build",
-		"--rm=true",
-		"--tag=gokr-rebuild-kernel",
-		".")
-	dockerBuild.Dir = tmp
-	dockerBuild.Stdout = os.Stdout
-	dockerBuild.Stderr = os.Stderr
-	if err := dockerBuild.Run(); err != nil {
-		log.Fatalf("%s build: %v (cmd: %v)", execName, err, dockerBuild.Args)
-	}
-
-	log.Printf("compiling kernel")
-
-	var dockerRun *exec.Cmd
-	if execName == "podman" {
-		dockerRun = exec.Command(executable,
-			"run",
-			"--userns=keep-id",
-			"--rm",
-			"--volume", tmp+":/tmp/buildresult:Z",
-			"gokr-rebuild-kernel")
-	} else {
-		dockerRun = exec.Command(executable,
-			"run",
-			"--rm",
-			"--volume", tmp+":/tmp/buildresult:Z",
-			"gokr-rebuild-kernel")
-	}
-	dockerRun.Dir = tmp
-	dockerRun.Stdout = os.Stdout
-	dockerRun.Stderr = os.Stderr
-	if err := dockerRun.Run(); err != nil {
-		log.Fatalf("%s run: %v (cmd: %v)", execName, err, dockerRun.Args)
-	}
-
-	if err := copyFile(kernelPath, filepath.Join(tmp, "vmlinuz")); err != nil {
-		log.Fatal(err)
-	}
-
-	if err := copyFile(dtbPath, filepath.Join(tmp, "rk3588-friendlyelec-cm3588-nas.dtb")); err != nil {
-		log.Fatal(err)
-	}
-}
--- a/cmd/gokr-rebuild-kernel/rebuildkernel.go
+++ b/cmd/gokr-rebuild-kernel/rebuildkernel.go
@@ -0,0 +1,353 @@
+package main
+
+import (
+	"bytes"
+	"flag"
+	"fmt"
+	"io"
+	"log"
+	"os"
+	"os/exec"
+	"os/user"
+	"path"
+	"path/filepath"
+	"strings"
+	"text/template"
+)
+
+const dockerFileContents = `
+FROM docker.io/library/debian:trixie
+
+RUN apt-get update && apt-get install -y \
+{{ if (eq .Cross "arm64") -}}
+  crossbuild-essential-arm64 \
+{{ end -}}
+  build-essential bc libssl-dev bison flex libelf-dev ncurses-dev ca-certificates zstd kmod python3 git
+
+COPY gokr-rebuild-kernel /usr/bin/gokr-rebuild-kernel
+COPY config.addendum.txt /usr/_src/config.addendum.txt
+COPY defconfig /usr/_src/defconfig
+COPY config.addendum.txt /usr/_src/.config
+COPY config.addendum.txt /usr/src/.config
+{{- range $idx, $path := .Patches }}
+COPY patch/{{ $path }} /usr/_src/{{ $path }}
+{{- end }}
+
+RUN echo 'builduser:x:{{ .Uid }}:{{ .Gid }}:nobody:/:/bin/sh' >> /etc/passwd && \
+    chown -R {{ .Uid }}:{{ .Gid }} /usr/src /usr/_src
+
+USER builduser
+WORKDIR /usr/src
+ENV GOKRAZY_IN_DOCKER=1
+ENTRYPOINT ["/usr/bin/gokr-rebuild-kernel"]
+`
+
+var dockerFileTmpl = template.Must(template.New("dockerfile").
+	Funcs(map[string]interface{}{
+		"basename": func(path string) string {
+			return filepath.Base(path)
+		},
+	}).
+	Parse(dockerFileContents))
+
+func copyFile(dest, src string) error {
+	log.Printf("copyFile(dest=%s, src=%s)", dest, src)
+	out, err := os.Create(dest)
+	if err != nil {
+		return err
+	}
+	defer out.Close()
+
+	in, err := os.Open(src)
+	if err != nil {
+		return err
+	}
+	defer in.Close()
+
+	n, err := io.Copy(out, in)
+	if err != nil {
+		return err
+	}
+	log.Printf("  -> %d bytes copied", n)
+
+	st, err := in.Stat()
+	if err != nil {
+		return err
+	}
+	if err := out.Chmod(st.Mode()); err != nil {
+		return err
+	}
+	return out.Close()
+}
+
+func find(filename string) (string, error) {
+	if _, err := os.Stat(filename); err == nil {
+		return filename, nil
+	}
+
+	return "", fmt.Errorf("could not find file %q", filename)
+}
+
+func getContainerExecutable() (string, error) {
+	// Probe podman first, because the docker binary might actually
+	// be a thin podman wrapper with podman behavior.
+	choices := []string{"podman", "docker"}
+	for _, exe := range choices {
+		p, err := exec.LookPath(exe)
+		if err != nil {
+			continue
+		}
+		resolved, err := filepath.EvalSymlinks(p)
+		if err != nil {
+			return "", err
+		}
+		return resolved, nil
+	}
+	return "", fmt.Errorf("none of %v found in $PATH", choices)
+}
+
+func rebuildKernel() error {
+	overwriteContainerExecutable := flag.String("overwrite_container_executable",
+		"",
+		"E.g. docker or podman to overwrite the automatically detected container executable")
+
+	keepBuildContainer := flag.Bool("keep_build_container",
+		false,
+		"do not delete build container after building the kernel")
+
+	cross := flag.String("cross",
+		"arm64",
+		"if non-empty, cross-compile for the specified arch (one of 'arm64')")
+	persistent := flag.Bool("persistent", false, "Mounts a folder into the docker container to persist kernel source for debugging")
+
+	flavor := flag.String("flavor",
+		"vanilla",
+		"which kernel flavor to build. one of vanilla (kernel.org) or raspberrypi (https://github.com/raspberrypi/linux/tags)")
+
+	dtbs := flag.String("dtbs",
+		"raspberrypi",
+		"which device tree files (.dtb files) to copy. 'raspberrypi' or empty")
+	_ = dtbs
+	flag.Parse()
+
+	if *cross != "" && *cross != "arm64" {
+		return fmt.Errorf("invalid -cross value %q: expected one of 'arm64'")
+	}
+
+	abs, err := os.Getwd()
+	if err != nil {
+		return err
+	}
+	if !strings.HasSuffix(strings.TrimSuffix(abs, "/"), "/_build") {
+		return fmt.Errorf("gokr-rebuild-kernel is not run from a _build directory")
+	}
+
+	series, err := os.ReadFile("series")
+	if err != nil {
+		return err
+	}
+	patches := strings.Split(strings.TrimSpace(string(series)), "\n")
+
+	executable, err := getContainerExecutable()
+	if err != nil {
+		return err
+	}
+	if *overwriteContainerExecutable != "" {
+		executable = *overwriteContainerExecutable
+	}
+
+	execName := filepath.Base(executable)
+
+	for _, filename := range patches {
+		_, err := find("patch/" + filename)
+		if err != nil {
+			return err
+		}
+	}
+
+	kernelPath, err := filepath.Abs("../vmlinuz")
+	if err != nil {
+		return err
+	}
+
+	libPath, err := filepath.Abs("../lib")
+	if err != nil {
+		return err
+	}
+
+	if _, err := find("config.addendum.txt"); err != nil {
+		return err
+	}
+
+	u, err := user.Current()
+	if err != nil {
+		return err
+	}
+
+	upstreamURL, err := os.ReadFile("upstream-url.txt")
+	if err != nil {
+		return err
+	}
+	upstreamURL = bytes.TrimSpace(upstreamURL)
+
+	dockerFile, err := os.Create("Dockerfile")
+	if err != nil {
+		return err
+	}
+
+	if err := dockerFileTmpl.Execute(dockerFile, struct {
+		Uid     string
+		Gid     string
+		Patches []string
+		Cross   string
+	}{
+		Uid:     u.Uid,
+		Gid:     u.Gid,
+		Patches: patches,
+		Cross:   *cross,
+	}); err != nil {
+		return err
+	}
+
+	if err := dockerFile.Close(); err != nil {
+		return err
+	}
+
+	log.Printf("building %s container for kernel compilation", execName)
+
+	dockerBuild := exec.Command(execName,
+		"build",
+		// "--platform=linux/amd64",
+		"--rm=true",
+		"--tag=gokr-rebuild-kernel",
+		".")
+	dockerBuild.Stdout = os.Stdout
+	dockerBuild.Stderr = os.Stderr
+	log.Printf("%v", dockerBuild.Args)
+	if err := dockerBuild.Run(); err != nil {
+		return fmt.Errorf("%s build: %v (cmd: %v)", execName, err, dockerBuild.Args)
+	}
+
+	log.Printf("compiling kernel")
+
+	var dockerRun *exec.Cmd
+
+	dockerArgs := []string{
+		"run",
+		// "--platform=linux/amd64",
+		"--volume", abs + ":/tmp/buildresult:Z",
+	}
+	kernelName := path.Base(string(upstreamURL))
+	_, err = os.Stat(kernelName)
+	log.Printf("Check for downloaded kernel %s: %v", kernelName, err)
+	if err == nil {
+		absKernelName, _ := filepath.Abs(kernelName)
+		dockerArgs = append(dockerArgs, "--volume", absKernelName+":/usr/src/"+kernelName)
+	}
+	if *persistent {
+		err = os.MkdirAll("./src_build", 0o777)
+		srcBuild, _ := filepath.Abs("./src_build")
+		if err != nil {
+			log.Fatal("Failed to create ./src_build", err)
+		}
+		dockerArgs = append(dockerArgs, "-v", srcBuild+":/usr/src")
+	} else {
+		dockerArgs = append(dockerArgs, fmt.Sprintf("--mount=type=tmpfs,tmpfs-size=%d%s,destination=%s,U", 5, "G", "/usr/src")) // Ramfs for faster build.... maybe
+	}
+
+	if !*keepBuildContainer {
+		dockerArgs = append(dockerArgs, "--rm")
+	}
+	if execName == "podman" {
+		dockerArgs = append(dockerArgs, "--userns=keep-id")
+	}
+	dockerArgs = append(dockerArgs,
+		"gokr-rebuild-kernel",
+		"-cross="+*cross,
+		"-flavor="+*flavor,
+		fmt.Sprintf("-persistent=%v", *persistent),
+		strings.TrimSpace(string(upstreamURL)))
+
+	dockerRun = exec.Command(executable, dockerArgs...)
+
+	dockerRun.Stdout = os.Stdout
+	dockerRun.Stderr = os.Stderr
+	log.Printf("%v", dockerRun.Args)
+	if err := dockerRun.Run(); err != nil {
+		return fmt.Errorf("%s run: %v (cmd: %v)", execName, err, dockerRun.Args)
+	}
+
+	if err := copyFile(kernelPath, "vmlinuz"); err != nil {
+		return err
+	}
+
+	if err := copyFile(kernelPath+".config", "vmlinuz.config"); err != nil {
+		return err
+	}
+
+	// remove symlinks that only work when source/build directory are present
+	for _, subdir := range []string{"build", "source"} {
+		matches, err := filepath.Glob(filepath.Join("lib/modules", "*", subdir))
+		if err != nil {
+			return err
+		}
+		for _, match := range matches {
+			log.Printf("removing build/source symlink %s", match)
+			if err := os.Remove(match); err != nil {
+				return err
+			}
+		}
+	}
+
+	// replace kernel modules directory
+	rm := exec.Command("rm", "-rf", filepath.Join(libPath, "modules"))
+	rm.Stdout = os.Stdout
+	rm.Stderr = os.Stderr
+	log.Printf("%v", rm.Args)
+	if err := rm.Run(); err != nil {
+		return fmt.Errorf("%v: %v", rm.Args, err)
+	}
+	cp := exec.Command("cp", "-r", filepath.Join("lib/modules"), libPath)
+	cp.Stdout = os.Stdout
+	cp.Stderr = os.Stderr
+	log.Printf("%v", cp.Args)
+	if err := cp.Run(); err != nil {
+		return fmt.Errorf("%v: %v", cp.Args, err)
+	}
+
+	if *cross == "arm64" {
+		if *flavor == "raspberrypi" {
+			// replace overlays directory
+			overlaysPath, err := find("../overlays")
+			if err != nil {
+				return err
+			}
+			rm = exec.Command("rm", "-rf", overlaysPath)
+			rm.Stdout = os.Stdout
+			rm.Stderr = os.Stderr
+			log.Printf("%v", rm.Args)
+			if err := rm.Run(); err != nil {
+				log.Printf("%v: %v", rm.Args, err)
+			}
+			cp = exec.Command("cp", "-r", "overlays", overlaysPath)
+			cp.Stdout = os.Stdout
+			cp.Stderr = os.Stderr
+			log.Printf("%v", cp.Args)
+			if err := cp.Run(); err != nil {
+				return fmt.Errorf("%v: %v", cp.Args, err)
+			}
+		}
+	}
+
+	return nil
+}
+
+func main() {
+	if os.Getenv("GOKRAZY_IN_DOCKER") == "1" {
+		indockerMain()
+	} else {
+		if err := rebuildKernel(); err != nil {
+			log.Fatal(err)
+		}
+	}
+}
--- a/cmd/gokr-rebuild-uboot/indocker.go
+++ b/cmd/gokr-rebuild-uboot/indocker.go
@@ -1,6 +1,7 @@
 package main

 import (
+	"errors"
 	"fmt"
 	"io"
 	"log"
@@ -9,15 +10,16 @@ import (
 	"path/filepath"
 	"runtime"
 	"strconv"
+	"strings"
 )

-const ubootRev = "a3cd0b4c632fff0f39013efebd419356eb6b4064"
-const ubootTS = 1723759665
-const trustedRepoRev = "a4e2a9f16d5c4620cd824294ef91a198fd276c80"
-
 const (
 	uBootRepo           = "https://github.com/u-boot/u-boot"
+	ubootRev            = "ff498a3c5efb424accc1d825cc45cede2540ca13"
 	trustedFirmwareRepo = "https://github.com/ARM-software/arm-trusted-firmware"
+	trustedRepoRev      = "6251d6ed1ffa7080edc55fa75f525e19ecf5edbd"
+	rkbinRepo           = "https://github.com/friendlyarm/rkbin"
+	rkbinRev            = "nanopi6"
 )

 func applyPatches(srcdir, t string) error {
@@ -46,30 +48,43 @@ func applyPatches(srcdir, t string) error {
 	return nil
 }

-func compile(trustedFirmwareDir string) error {
+func compile(ubootDir, trustedFirmwareDir string) error {
 	defconfig := exec.Command("make", "ARCH=arm64", "cm3588-nas-rk3588_defconfig")
 	defconfig.Stdout = os.Stdout
 	defconfig.Stderr = os.Stderr
+	defconfig.Dir = ubootDir
 	if err := defconfig.Run(); err != nil {
 		return fmt.Errorf("make defconfig: %v", err)
 	}

-	f, err := os.OpenFile(".config", os.O_RDWR|os.O_APPEND, 0755)
+	f, err := os.OpenFile(filepath.Join(ubootDir, ".config"), os.O_RDWR|os.O_APPEND, 0o755)
 	if err != nil {
 		return err
 	}
-	if _, err := f.Write([]byte("CONFIG_CMD_SETEXPR=y\nCONFIG_CMD_SETEXPR_FMT=y\n")); err != nil {
+	if _, err := f.Write([]byte(`
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_SETEXPR_FMT=y
+CONFIG_BOOTCOMMAND="setenv bootmeths script; bootflow scan -lb"
+`)); err != nil {
 		return err
 	}
 	if err := f.Close(); err != nil {
 		return err
 	}

+	cmd := exec.Command("git", "show", "-s", "--date=unix", "--pretty=format:%ad", "HEAD")
+	cmd.Dir = ubootDir
+	output, err := cmd.Output()
+	if err != nil {
+		return fmt.Errorf("unable to get date of git repo: %w", err)
+	}
+
 	make := exec.Command("make", "-j"+strconv.Itoa(runtime.NumCPU()))
+	make.Dir = ubootDir
 	make.Env = append(os.Environ(),
 		"ARCH=arm64",
 		"CROSS_COMPILE=aarch64-linux-gnu-",
-		"SOURCE_DATE_EPOCH="+strconv.Itoa(ubootTS),
+		"SOURCE_DATE_EPOCH="+strings.TrimSpace(string(output)),
 		fmt.Sprintf("BL31=%s/build/rk3588/release/bl31/bl31.elf", trustedFirmwareDir),
 		fmt.Sprintf("ROCKCHIP_TPL=%s", "/usr/src/uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin"),
 	)
@@ -82,13 +97,14 @@ func compile(trustedFirmwareDir string) error {
 	return nil
 }

-func generateBootScr(bootCmdPath string) error {
-	mkimage := exec.Command("./tools/mkimage", "-A", "arm", "-T", "script", "-C", "none", "-d", bootCmdPath, "boot.scr")
+func generateBootScr(ubootDir, bootCmdPath string) error {
+	mkimage := exec.Command(filepath.Join(ubootDir, "./tools/mkimage"), "-A", "arm", "-T", "script", "-C", "none", "-d", bootCmdPath, "boot.scr")
 	mkimage.Env = append(os.Environ(),
 		"ARCH=arm64",
 		"CROSS_COMPILE=aarch64-linux-gnu-",
 		"SOURCE_DATE_EPOCH=1600000000",
 	)
+	mkimage.Dir = ubootDir
 	mkimage.Stdout = os.Stdout
 	mkimage.Stderr = os.Stderr
 	if err := mkimage.Run(); err != nil {
@@ -125,32 +141,38 @@ func copyFile(dest, src string) error {
 	return out.Close()
 }

-func main() {
-	ubootDir, err := os.MkdirTemp("", "u-boot")
-	if err != nil {
+func clone(dir string, repo string, rev string) error {
+	err := os.Mkdir(dir, 0o777)
+	if err != nil && !errors.Is(err, os.ErrExist) {
 		log.Fatal(err)
 	}
-
-	trustedFirmwareDir, err := os.MkdirTemp("", "arm-trusted-firmware")
-	if err != nil {
-		log.Fatal(err)
-	}
-
-	for _, cmd := range [][]string{
+	var commands = [][]string{
 		{"git", "init"},
-		{"git", "remote", "add", "origin", trustedFirmwareRepo},
-		{"git", "fetch", "--depth=1", "origin", trustedRepoRev},
+		{"git", "remote", "add", "origin", repo},
+		{"git", "fetch", "--depth=1", "origin", rev},
 		{"git", "checkout", "FETCH_HEAD"},
-	} {
+	}
+	if _, err = os.Stat(filepath.Join(dir, ".git")); err == nil {
+		commands = commands[2:]
+	}
+	for _, cmd := range commands {
 		log.Printf("Running %s", cmd)
 		cmdObj := exec.Command(cmd[0], cmd[1:]...)
 		cmdObj.Stdout = os.Stdout
 		cmdObj.Stderr = os.Stderr
-		cmdObj.Dir = trustedFirmwareDir
+		cmdObj.Dir = dir
 		if err := cmdObj.Run(); err != nil {
-			log.Fatal(err)
+			return err
 		}
 	}
+	return nil
+}
+
+func compileATF() string {
+	trustedFirmwareDir, _ := filepath.Abs("arm-trusted-firmware")
+	if err := clone(trustedFirmwareDir, trustedFirmwareRepo, trustedRepoRev); err != nil {
+		log.Fatal("Failed to clone Trusted Firmware:", err)
+	}

 	log.Printf("applying patches")
 	if err := applyPatches(trustedFirmwareDir, "atf"); err != nil {
@@ -168,33 +190,45 @@ func main() {
 			log.Fatal(err)
 		}
 	}
-
-	var bootCmdPath string
-	if p, err := filepath.Abs("uboot.patches/boot.cmd"); err != nil {
-		log.Fatal(err)
-	} else {
-		bootCmdPath = p
+	return trustedFirmwareDir
 }

-	if err := os.Chdir(ubootDir); err != nil {
-		log.Fatal(err)
+func downloadRKbin() string {
+	var err error = nil
+	rkbinDir, _ := filepath.Abs("rkbin")
+
+	if err = clone(rkbinDir, rkbinRepo, rkbinRev); err != nil {
+		log.Fatal("Failed to clone rkbin Firmware:", err)
 	}

-	for _, cmd := range [][]string{
-		{"git", "init"},
-		{"git", "remote", "add", "origin", uBootRepo},
-		{"git", "fetch", "--depth=1", "origin", ubootRev},
-		{"git", "checkout", "FETCH_HEAD"},
-	} {
-		log.Printf("Running %s", cmd)
-		cmdObj := exec.Command(cmd[0], cmd[1:]...)
+	log.Printf("applying patches")
+	if err := applyPatches(rkbinDir, "rkbin"); err != nil {
+		log.Fatal(err)
+	}
+	return rkbinDir
+}
+
+func indockerMain() {
+
+	srcFiles, err := filepath.Glob("/usr/_src/*")
+	if err != nil {
+		log.Fatalf("failed to find source files: %v", err)
+	}
+	for _, fileName := range srcFiles {
+		cmdObj := exec.Command("cp", "-r", "-t", "/usr/src", fileName)
 		cmdObj.Stdout = os.Stdout
 		cmdObj.Stderr = os.Stderr
-		cmdObj.Dir = ubootDir
 		if err := cmdObj.Run(); err != nil {
 			log.Fatal(err)
 		}
 	}
+	rkbinDir := compileATF()
+	bootCmdPath, _ := filepath.Abs("uboot.patches/boot.cmd")
+
+	ubootDir, _ := filepath.Abs("u-boot")
+	if err := clone(ubootDir, uBootRepo, ubootRev); err != nil {
+		log.Fatal("Failed to clone uboot repo:", err)
+	}

 	log.Printf("applying patches")
 	if err := applyPatches(ubootDir, "uboot"); err != nil {
@@ -202,23 +236,23 @@ func main() {
 	}

 	log.Printf("compiling uboot")
-	if err := compile(trustedFirmwareDir); err != nil {
+	if err := compile(ubootDir, rkbinDir); err != nil {
 		log.Fatal(err)
 	}

 	log.Printf("generating boot.scr")
-	if err := generateBootScr(bootCmdPath); err != nil {
+	if err := generateBootScr(ubootDir, bootCmdPath); err != nil {
 		log.Fatal(err)
 	}

 	for _, copyCfg := range []struct {
 		dest, src string
 	}{
-		{"boot.scr", "boot.scr"},
-		{"u-boot-rockchip.bin", "u-boot-rockchip.bin"},
+		{"boot.scr", "u-boot/boot.scr"},
+		{"u-boot-rockchip.bin", "u-boot/u-boot-rockchip.bin"},
 	} {
 		if err := copyFile(filepath.Join("/tmp/buildresult", copyCfg.dest), copyCfg.src); err != nil {
-			log.Fatal(err)
+			log.Fatal("indocker ", err)
 		}
 	}
 }
--- a/cmd/gokr-rebuild-uboot/uboot.go
+++ b/cmd/gokr-rebuild-uboot/uboot.go
@@ -3,7 +3,6 @@ package main
 import (
 	"flag"
 	"fmt"
-	"io"
 	"log"
 	"os"
 	"os/exec"
@@ -14,22 +13,24 @@ import (
 )

 const dockerFileContents = `
-FROM debian:bookworm
+FROM docker.io/library/debian:trixie

-RUN apt-get update && apt-get install -y crossbuild-essential-arm64 bc libssl-dev bison flex git python3 python3-setuptools swig python3-dev python3-pyelftools uuid-dev libgnutls28-dev
+RUN apt-get update && apt-get install -y build-essential crossbuild-essential-arm64 bc libssl-dev bison flex git python3 python3-setuptools swig python3-dev python3-pyelftools uuid-dev libgnutls28-dev
+RUN apt-get install -y device-tree-compiler

 COPY gokr-build-uboot /usr/bin/gokr-build-uboot
-RUN mkdir -p /usr/src/atf.patches
-RUN mkdir -p /usr/src/uboot.patches
+RUN mkdir -p /usr/_src/atf.patches
+RUN mkdir -p /usr/_src/uboot.patches
 {{- range $idx, $path := .Patches }}
-COPY {{ $path }} /usr/src/{{ $path }}
+COPY {{ $path }} /usr/_src/{{ $path }}
 {{- end }}

 RUN echo 'builduser:x:{{ .Uid }}:{{ .Gid }}:nobody:/:/bin/sh' >> /etc/passwd && \
-    chown -R {{ .Uid }}:{{ .Gid }} /usr/src
+    chown -R {{ .Uid }}:{{ .Gid }} /usr/src /usr/_src

 USER builduser
 WORKDIR /usr/src
+ENV GOKRAZY_IN_DOCKER=1
 ENTRYPOINT /usr/bin/gokr-build-uboot
 `

@@ -43,50 +44,15 @@ var dockerFileTmpl = template.Must(template.New("dockerfile").

 var ubootPatchFiles = []string{
 	"uboot.patches/boot.cmd",
+	"uboot.patches/rk3588_bl31_v1.46.elf",
 	"uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin",
+	"uboot.patches/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin",
 }
+
 var atfPatchFiles = []string{
-	"atf.patches/feat-rk3588-support-rk3588.patch",
-	"atf.patches/rk3588-enable-crypto-function.patch",
-	"atf.patches/feat-rockchip-support-SCMI-for-clock-reset-domain.patch",
-	"atf.patches/rockchip-add-some-pm-helpers-functions.patch",
-}
-
-func copyFile(dest, src string) error {
-	out, err := os.Create(dest)
-	if err != nil {
-		return err
-	}
-	defer out.Close()
-
-	in, err := os.Open(src)
-	if err != nil {
-		return err
-	}
-	defer in.Close()
-
-	if _, err := io.Copy(out, in); err != nil {
-		return err
-	}
-
-	st, err := in.Stat()
-	if err != nil {
-		return err
-	}
-	if err := out.Chmod(st.Mode()); err != nil {
-		return err
-	}
-	return out.Close()
-}
-
-var gopath = mustGetGopath()
-
-func mustGetGopath() string {
-	gopathb, err := exec.Command("go", "env", "GOPATH").Output()
-	if err != nil {
-		log.Panic(err)
-	}
-	return strings.TrimSpace(string(gopathb))
+	// "atf.patches/feat-rk3588-support-rk3588.patch",
+	// "atf.patches/rk3588-enable-crypto-function.patch",
+	// "atf.patches/feat-rockchip-support-SCMI-for-clock-reset-domain.patch",
 }

 func find(filename string) (string, error) {
@@ -94,12 +60,7 @@ func find(filename string) (string, error) {
 		return filename, nil
 	}

-	path := filepath.Join(gopath, "src", "github", "lordwelch", "gokrazy-cm3588-kernel", filename)
-	if _, err := os.Stat(path); err == nil {
-		return path, nil
-	}
-
-	return "", fmt.Errorf("could not find file %q (looked in . and %s)", filename, path)
+	return "", fmt.Errorf("could not find file %q", filename)
 }

 func getContainerExecutable() (string, error) {
@@ -120,15 +81,24 @@ func getContainerExecutable() (string, error) {
 	return "", fmt.Errorf("none of %v found in $PATH", choices)
 }

-func main() {
-	var overwriteContainerExecutable = flag.String("overwrite_container_executable",
+func rebuildUboot() {
+	overwriteContainerExecutable := flag.String("overwrite_container_executable",
 		"",
 		"E.g. docker or podman to overwrite the automatically detected container executable")
+	persistent := flag.Bool("persistent", false, "Mounts a folder into the docker container to persist u-boot source for debugging")
 	flag.Parse()
 	executable, err := getContainerExecutable()
 	if err != nil {
 		log.Fatal(err)
 	}
+
+	abs, err := os.Getwd()
+	if err != nil {
+		log.Fatal(err)
+	}
+	if !strings.HasSuffix(strings.TrimSuffix(abs, "/"), "/_build") {
+		log.Fatalf("gokr-rebuild-uboot is not run from a _build directory")
+	}
 	if *overwriteContainerExecutable != "" {
 		executable = *overwriteContainerExecutable
 	}
@@ -141,15 +111,15 @@ func main() {
 		log.Fatal(err)
 	}
 	defer os.RemoveAll(tmp)
-
-	cmd := exec.Command("go", "build", "-o", tmp, "github/lordwelch/gokrazy-cm3588-kernel/cmd/gokr-build-uboot")
-	cmd.Env = append(os.Environ(), "GOOS=linux", "CGO_ENABLED=0")
-	cmd.Stderr = os.Stderr
-	if err := cmd.Run(); err != nil {
-		log.Fatalf("%v: %v", cmd.Args, err)
+	exePath, err := os.Executable()
+	if err != nil {
+		log.Fatal("Unable to find current executable", err)
 	}
-
 	buildPath := filepath.Join(tmp, "gokr-build-uboot")
+	err = copyFile(buildPath, exePath)
+	if err != nil {
+		log.Fatal("Unable to copy executable for docker", err)
+	}

 	var patchPaths []string

@@ -161,7 +131,7 @@ func main() {
 		patchPaths = append(patchPaths, path)
 	}

-	err = os.MkdirAll(filepath.Join(tmp, "uboot.patches"), 0750)
+	err = os.MkdirAll(filepath.Join(tmp, "uboot.patches"), 0o750)
 	if err != nil {
 		log.Fatal(err)
 	}
@@ -173,7 +143,6 @@ func main() {
 		}
 	}

-
 	patchPaths = patchPaths[0:0]
 	for _, filename := range atfPatchFiles {
 		path, err := find(filename)
@@ -183,8 +152,7 @@ func main() {
 		patchPaths = append(patchPaths, path)
 	}

-
-	err = os.MkdirAll(filepath.Join(tmp, "atf.patches"), 0750)
+	err = os.MkdirAll(filepath.Join(tmp, "atf.patches"), 0o750)
 	if err != nil {
 		log.Fatal(err)
 	}
@@ -225,7 +193,7 @@ func main() {

 	log.Printf("building %s container for uboot compilation", execName)

-	dockerBuild := exec.Command(execName,
+	dockerBuild := exec.Command(executable,
 		"build",
 		"--rm=true",
 		"--tag=gokr-rebuild-uboot",
@@ -240,20 +208,26 @@ func main() {
 	log.Printf("compiling uboot")

 	var dockerRun *exec.Cmd
-	if execName == "podman" {
-		dockerRun = exec.Command(executable,
+	dockerArgs := []string{
 		"run",
-			"--userns=keep-id",
-			"--rm",
+		// "--platform=linux/amd64",
 		"--volume", tmp + ":/tmp/buildresult:Z",
-			"gokr-rebuild-uboot")
-	} else {
-		dockerRun = exec.Command(executable,
-			"run",
-			"--rm",
-			"--volume", tmp+":/tmp/buildresult:Z",
-			"gokr-rebuild-uboot")
 	}
+	if *persistent {
+		err = os.MkdirAll("./src_build", 0o777)
+		srcBuild, _ := filepath.Abs("./src_build")
+		if err != nil {
+			log.Fatal("Failed to create ./src_build", err)
+		}
+		dockerArgs = append(dockerArgs, "-v", srcBuild+":/usr/src")
+	} else {
+		dockerArgs = append(dockerArgs, fmt.Sprintf("--mount=type=tmpfs,tmpfs-size=%d%s,destination=%s,U", 5, "G", "/usr/src")) // Ramfs for faster build.... maybe
+	}
+	if execName == "podman" {
+		dockerArgs = append(dockerArgs, "--userns=keep-id")
+	}
+	dockerArgs = append(dockerArgs, "gokr-rebuild-uboot")
+	dockerRun = exec.Command(executable, dockerArgs...)
 	dockerRun.Dir = tmp
 	dockerRun.Stdout = os.Stdout
 	dockerRun.Stderr = os.Stderr
@@ -261,12 +235,19 @@ func main() {
 		log.Fatalf("%s run: %v (cmd: %v)", execName, err, dockerRun.Args)
 	}

-	for _, filename := range []string{
-		"boot.scr",
-		"u-boot-rockchip.bin",
-	} {
-		if err := copyFile(filename, filepath.Join(tmp, filename)); err != nil {
+	if err := copyFile("../boot.scr", "boot.scr"); err != nil {
+		log.Fatal(err)
+	}
+
+	if err := copyFile("../u-boot-rockchip.bin", "u-boot-rockchip.bin"); err != nil {
 		log.Fatal(err)
 	}
 }
+
+func main() {
+	if os.Getenv("GOKRAZY_IN_DOCKER") == "1" {
+		indockerMain()
+	} else {
+		rebuildUboot()
+	}
 }
--- a/go.mod
+++ b/go.mod
@@ -1,3 +1,3 @@
-module github.com/lordwelch/gokrazy-cm3588-kernel
+module gitea.narnian.us/lordwelch/gokrazy-cm3588-kernel

 go 1.22
--- a/kernel.patches/0001-dt-bindings-arm-rockchip-Add-FriendlyElec-CM3588-NAS.patch
+++ b/kernel.patches/0001-dt-bindings-arm-rockchip-Add-FriendlyElec-CM3588-NAS.patch
@@ -1,37 +0,0 @@
-From e6b6a82789baf275a597ef312a145c3b4a44da19 Mon Sep 17 00:00:00 2001
-From: Sebastian Kropatsch <seb-dev@mail.de>
-Date: Sun, 16 Jun 2024 23:48:29 +0200
-Subject: [PATCH 1/2] dt-bindings: arm: rockchip: Add FriendlyElec CM3588 NAS
-
-Add devicetree bindings for the FriendlyElec CM3588 NAS board.
-
-The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based on
-the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board.
-
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
---
- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
-index fcf7316ec..86379b8cc 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
-+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
-@@ -248,6 +248,13 @@ properties:
-           - const: friendlyarm,nanopc-t6
-           - const: rockchip,rk3588
- 
-+      - description: FriendlyElec CM3588-based boards
-+        items:
-+          - enum:
-+              - friendlyarm,cm3588-nas
-+          - const: friendlyarm,cm3588
-+          - const: rockchip,rk3588
-+
-       - description: GameForce Chi
-         items:
-           - const: gameforce,chi
-- 
-2.45.2
-
--- a/kernel.patches/0002-arm64-dts-rockchip-Add-FriendlyElec-CM3588-NAS-board.patch
+++ b/kernel.patches/0002-arm64-dts-rockchip-Add-FriendlyElec-CM3588-NAS-board.patch
--- a/kernel.patches/0011-irqchip-fix-its-timeout-issue.patch
+++ b/kernel.patches/0011-irqchip-fix-its-timeout-issue.patch
@@ -1,214 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Fri, 11 Aug 2023 17:56:00 +0300
-Subject: irqchip/irq-gic-v3-its: fix its timeout issue for rk35xx boards
-
---
- drivers/irqchip/irq-gic-v3-its.c | 79 +++++++++-
- 1 file changed, 72 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
-index 111111111111..222222222222 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
-+++ b/drivers/irqchip/irq-gic-v3-its.c
-@@ -163,6 +163,7 @@ struct its_device {
- 	struct its_node		*its;
- 	struct event_lpi_map	event_map;
- 	void			*itt;
-+	u32			itt_sz;
- 	u32			nr_ites;
- 	u32			device_id;
- 	bool			shared;
-@@ -2191,6 +2192,9 @@ static void gic_reset_prop_table(void *va)
- static struct page *its_allocate_prop_table(gfp_t gfp_flags)
- {
- 	struct page *prop_page;
-+
-+	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
-+		gfp_flags |= GFP_DMA32;
- 
- 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
- 	if (!prop_page)
-@@ -2315,6 +2319,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
- 	u32 alloc_pages, psz;
- 	struct page *page;
- 	void *base;
-+	gfp_t gfp_flags;
- 
- 	psz = baser->psz;
- 	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
-@@ -2326,7 +2331,11 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
- 		order = get_order(GITS_BASER_PAGES_MAX * psz);
- 	}
- 
-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
-+	gfp_flags = GFP_KERNEL | __GFP_ZERO;
-+	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
-+		gfp_flags |= GFP_DMA32;
-+
-+	page = alloc_pages_node(its->numa_node, gfp_flags, order);
- 	if (!page)
- 		return -ENOMEM;
- 
-@@ -2376,6 +2385,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
- 	its_write_baser(its, baser, val);
- 	tmp = baser->val;
- 
-+	if (of_machine_is_compatible("rockchip,rk3568") ||
-+	     of_machine_is_compatible("rockchip,rk3566") ||
-+	     of_machine_is_compatible("rockchip,rk3588")) {
-+		if (tmp & GITS_BASER_SHAREABILITY_MASK)
-+			tmp &= ~GITS_BASER_SHAREABILITY_MASK;
-+		else
-+			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
-+	}
-+
- 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
- 		/*
- 		 * Shareability didn't stick. Just use
-@@ -2965,7 +2983,9 @@ static int its_alloc_collections(struct its_node *its)
- static struct page *its_allocate_pending_table(gfp_t gfp_flags)
- {
- 	struct page *pend_page;
-
-+
-+	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
-+		gfp_flags |= GFP_DMA32;
- 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
- 				get_order(LPI_PENDBASE_SZ));
- 	if (!pend_page)
-@@ -3124,6 +3144,11 @@ static void its_cpu_init_lpis(void)
- 	if (!rdists_support_shareable())
- 		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
- 
-+	if (of_machine_is_compatible("rockchip,rk3568") ||
-+	     of_machine_is_compatible("rockchip,rk3566") ||
-+	     of_machine_is_compatible("rockchip,rk3588"))
-+		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
-+
- 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
- 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
- 			/*
-@@ -3151,6 +3176,11 @@ static void its_cpu_init_lpis(void)
- 	if (!rdists_support_shareable())
- 		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
- 
-+	if (of_machine_is_compatible("rockchip,rk3568") ||
-+	     of_machine_is_compatible("rockchip,rk3566") ||
-+	     of_machine_is_compatible("rockchip,rk3588"))
-+		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
-+
- 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
- 		/*
- 		 * The HW reports non-shareable, we must remove the
-@@ -3314,7 +3344,11 @@ static bool its_alloc_table_entry(struct its_node *its,
- 
- 	/* Allocate memory for 2nd level table */
- 	if (!table[idx]) {
-		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
-+		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
-+
-+		if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
-+			gfp_flags |= GFP_DMA32;
-+		page = alloc_pages_node(its->numa_node, gfp_flags,
- 					get_order(baser->psz));
- 		if (!page)
- 			return false;
-@@ -3403,6 +3437,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
- 	int nr_lpis;
- 	int nr_ites;
- 	int sz;
-+	gfp_t gfp_flags;
- 
- 	if (!its_alloc_device_table(its, dev_id))
- 		return NULL;
-@@ -3418,7 +3453,15 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
- 	nr_ites = max(2, nvecs);
- 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
- 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
-	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
-+	gfp_flags = GFP_KERNEL;
-+
-+	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) {
-+		gfp_flags |= GFP_DMA32;
-+		itt = (void *)__get_free_pages(gfp_flags, get_order(sz));
-+	} else {
-+		itt = kzalloc_node(sz, gfp_flags, its->numa_node);
-+	}
-+
- 	if (alloc_lpis) {
- 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
- 		if (lpi_map)
-@@ -3432,7 +3475,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
- 
- 	if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
- 		kfree(dev);
-		kfree(itt);
-+
-+		if (of_machine_is_compatible("rockchip,rk3568") ||
-+		    of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
-+			free_pages((unsigned long)itt, get_order(sz));
-+		else
-+			kfree(itt);
-+
- 		bitmap_free(lpi_map);
- 		kfree(col_map);
- 		return NULL;
-@@ -3442,6 +3491,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
- 
- 	dev->its = its;
- 	dev->itt = itt;
-+	dev->itt_sz = sz;
- 	dev->nr_ites = nr_ites;
- 	dev->event_map.lpi_map = lpi_map;
- 	dev->event_map.col_map = col_map;
-@@ -3469,7 +3519,13 @@ static void its_free_device(struct its_device *its_dev)
- 	list_del(&its_dev->entry);
- 	raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
- 	kfree(its_dev->event_map.col_map);
-	kfree(its_dev->itt);
-+
-+	if (of_machine_is_compatible("rockchip,rk3568") ||
-+	    of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
-+		free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz));
-+	else
-+		kfree(its_dev->itt);
-+
- 	kfree(its_dev);
- }
- 
-@@ -5078,6 +5134,7 @@ static int __init its_probe_one(struct its_node *its)
- 	struct page *page;
- 	u32 ctlr;
- 	int err;
-+	gfp_t gfp_flags;
- 
- 	its_enable_quirks(its);
- 
-@@ -5111,7 +5168,10 @@ static int __init its_probe_one(struct its_node *its)
- 		}
- 	}
- 
-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
-+	gfp_flags = GFP_KERNEL | __GFP_ZERO;
-+	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
-+		gfp_flags |= GFP_DMA32;
-+	page = alloc_pages_node(its->numa_node, gfp_flags,
- 				get_order(ITS_CMD_QUEUE_SZ));
- 	if (!page) {
- 		err = -ENOMEM;
-@@ -5140,6 +5200,11 @@ static int __init its_probe_one(struct its_node *its)
- 	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
- 		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
- 
-+	if (of_machine_is_compatible("rockchip,rk3568") ||
-+	     of_machine_is_compatible("rockchip,rk3566") ||
-+	     of_machine_is_compatible("rockchip,rk3588"))
-+		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
-+
- 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
- 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
- 			/*
-- 
-Armbian
-
--- a/kernel.patches/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch
+++ b/kernel.patches/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch
@@ -1,758 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 6 May 2024 13:36:32 +0400
-Subject: arm64: dts: rockchip: add thermal zones information on RK3588
-
-This includes the necessary device tree data to allow thermal
-monitoring on RK3588(s) using the on-chip TSADC device, along with
-trip points for automatic thermal management.
-
-Each of the CPU clusters (one for the little cores and two for
-the big cores) get a passive cooling trip point at 85C, which
-will trigger DVFS throttling of the respective cluster upon
-reaching a high temperature condition.
-
-All zones also have a critical trip point at 115C, which will
-trigger a reset.
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 147 ++++++++++
- 1 file changed, 147 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -10,6 +10,7 @@
- #include <dt-bindings/reset/rockchip,rk3588-cru.h>
- #include <dt-bindings/phy/phy.h>
- #include <dt-bindings/ata/ahci.h>
-+#include <dt-bindings/thermal/thermal.h>
- 
- / {
- 	compatible = "rockchip,rk3588";
-@@ -2368,6 +2369,152 @@ pwm15: pwm@febf0030 {
- 		status = "disabled";
- 	};
- 
-+	thermal_zones: thermal-zones {
-+		/* sensor near the center of the SoC */
-+		package_thermal: package-thermal {
-+			polling-delay-passive = <0>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsadc 0>;
-+
-+			trips {
-+				package_crit: package-crit {
-+					temperature = <115000>;
-+					hysteresis = <0>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		/* sensor between A76 cores 0 and 1 */
-+		bigcore0_thermal: bigcore0-thermal {
-+			polling-delay-passive = <100>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsadc 1>;
-+
-+			trips {
-+				bigcore0_alert: bigcore0-alert {
-+					temperature = <85000>;
-+					hysteresis = <2000>;
-+					type = "passive";
-+				};
-+				bigcore0_crit: bigcore0-crit {
-+					temperature = <115000>;
-+					hysteresis = <0>;
-+					type = "critical";
-+				};
-+			};
-+			cooling-maps {
-+				map0 {
-+					trip = <&bigcore0_alert>;
-+					cooling-device =
-+						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+						<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+				};
-+			};
-+		};
-+
-+		/* sensor between A76 cores 2 and 3 */
-+		bigcore2_thermal: bigcore2-thermal {
-+			polling-delay-passive = <100>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsadc 2>;
-+
-+			trips {
-+				bigcore2_alert: bigcore2-alert {
-+					temperature = <85000>;
-+					hysteresis = <2000>;
-+					type = "passive";
-+				};
-+				bigcore2_crit: bigcore2-crit {
-+					temperature = <115000>;
-+					hysteresis = <0>;
-+					type = "critical";
-+				};
-+			};
-+			cooling-maps {
-+				map0 {
-+					trip = <&bigcore2_alert>;
-+					cooling-device =
-+						<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+						<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+				};
-+			};
-+		};
-+
-+		/* sensor between the four A55 cores */
-+		little_core_thermal: littlecore-thermal {
-+			polling-delay-passive = <100>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsadc 3>;
-+
-+			trips {
-+				littlecore_alert: littlecore-alert {
-+					temperature = <85000>;
-+					hysteresis = <2000>;
-+					type = "passive";
-+				};
-+				littlecore_crit: littlecore-crit {
-+					temperature = <115000>;
-+					hysteresis = <0>;
-+					type = "critical";
-+				};
-+			};
-+			cooling-maps {
-+				map0 {
-+					trip = <&littlecore_alert>;
-+					cooling-device =
-+						<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+						<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+						<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+						<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+				};
-+			};
-+		};
-+
-+		/* sensor near the PD_CENTER power domain */
-+		center_thermal: center-thermal {
-+			polling-delay-passive = <0>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsadc 4>;
-+
-+			trips {
-+				center_crit: center-crit {
-+					temperature = <115000>;
-+					hysteresis = <0>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		gpu_thermal: gpu-thermal {
-+			polling-delay-passive = <0>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsadc 5>;
-+
-+			trips {
-+				gpu_crit: gpu-crit {
-+					temperature = <115000>;
-+					hysteresis = <0>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		npu_thermal: npu-thermal {
-+			polling-delay-passive = <0>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsadc 6>;
-+
-+			trips {
-+				npu_crit: npu-crit {
-+					temperature = <115000>;
-+					hysteresis = <0>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+	};
-+
- 	tsadc: tsadc@fec00000 {
- 		compatible = "rockchip,rk3588-tsadc";
- 		reg = <0x0 0xfec00000 0x0 0x400>;
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 6 May 2024 13:36:33 +0400
-Subject: arm64: dts: rockchip: enable thermal management on all RK3588 boards
-
-This enables the on-chip thermal monitoring sensor (TSADC) on all
-RK3588(s) boards that don't have it enabled yet. It provides temperature
-monitoring for the SoC and emergency thermal shutdowns, and is thus
-important to have in place before CPU DVFS is enabled, as high CPU
-operating performance points can overheat the chip quickly in the
-absence of thermal management.
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts          | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts              | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts              | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts               | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts           | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi           | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts              | 4 ++++
- 8 files changed, 32 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-@@ -673,6 +673,10 @@ regulator-state-mem {
- 	};
- };
- 
-+&tsadc {
-+	status = "okay";
-+};
-+
- &u2phy0 {
- 	status = "okay";
- };
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
-@@ -466,3 +466,7 @@ regulator-state-mem {
- 		};
- 	};
- };
-+
-+&tsadc {
-+	status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-@@ -1131,6 +1131,10 @@ &sata0 {
- 	status = "okay";
- };
- 
-+&tsadc {
-+	status = "okay";
-+};
-+
- &u2phy0 {
- 	status = "okay";
- };
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
-@@ -376,6 +376,10 @@ &sdmmc {
- 	status = "okay";
- };
- 
-+&tsadc {
-+	status = "okay";
-+};
-+
- &u2phy2 {
- 	status = "okay";
- };
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -743,6 +743,10 @@ regulator-state-mem {
- 	};
- };
- 
-+&tsadc {
-+	status = "okay";
-+};
-+
- &uart2 {
- 	pinctrl-0 = <&uart2m0_xfer>;
- 	status = "okay";
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts
-@@ -648,6 +648,10 @@ regulator-state-mem {
- 	};
- };
- 
-+&tsadc {
-+	status = "okay";
-+};
-+
- &u2phy2 {
- 	status = "okay";
- };
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
-@@ -601,6 +601,10 @@ regulator-state-mem {
- 	};
- };
- 
-+&tsadc {
-+	status = "okay";
-+};
-+
- &uart2 {
- 	pinctrl-0 = <&uart2m0_xfer>;
- 	status = "okay";
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -699,6 +699,10 @@ regulator-state-mem {
- 	};
- };
- 
-+&tsadc {
-+	status = "okay";
-+};
-+
- &u2phy0 {
- 	status = "okay";
- };
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 6 May 2024 13:36:34 +0400
-Subject: arm64: dts: rockchip: add passive GPU cooling on RK3588
-
-As the GPU support on RK3588 has been merged upstream, along with OPP
-values, add a corresponding cooling map for passive cooling using the GPU.
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 14 +++++++++-
- 1 file changed, 13 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -2487,17 +2487,29 @@ center_crit: center-crit {
- 		};
- 
- 		gpu_thermal: gpu-thermal {
-			polling-delay-passive = <0>;
-+			polling-delay-passive = <100>;
- 			polling-delay = <0>;
- 			thermal-sensors = <&tsadc 5>;
- 
- 			trips {
-+				gpu_alert: gpu-alert {
-+					temperature = <85000>;
-+					hysteresis = <2000>;
-+					type = "passive";
-+				};
- 				gpu_crit: gpu-crit {
- 					temperature = <115000>;
- 					hysteresis = <0>;
- 					type = "critical";
- 				};
- 			};
-+			cooling-maps {
-+				map0 {
-+					trip = <&gpu_alert>;
-+					cooling-device =
-+						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+				};
-+			};
- 		};
- 
- 		npu_thermal: npu-thermal {
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 6 May 2024 13:36:36 +0400
-Subject: arm64: dts: rockchip: Add CPU/memory regulator coupling for RK3588
-
-RK3588 chips allow for their CPU cores to be powered by a different
-supply vs. their corresponding memory interfaces, and two of the
-boards currently upstream do that (EVB1 and QuartzPro64).
-
-The voltage of the memory interface though has to match that of the
-CPU cores that use it, which downstream kernels achieve by the means
-of a custom cpufreq driver which adjusts both at the same time.
-
-It seems that regulator coupling is a more appropriate generic
-interface for it, so this patch introduces coupling to affected
-device trees to ensure that memory interface voltage is also updated
-whenever cpufreq switches between CPU OPPs.
-
-Note that other boards, such as Radxa Rock 5B, define both the CPU
-and memory interface regulators as aliases to the same DT node, so
-this doesn't apply there.
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts    | 12 ++++++++++
- arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 12 ++++++++++
- 2 files changed, 24 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-@@ -878,6 +878,8 @@ regulators {
- 			vdd_cpu_big1_s0: dcdc-reg1 {
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_big1_mem_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <550000>;
- 				regulator-max-microvolt = <1050000>;
- 				regulator-ramp-delay = <12500>;
-@@ -890,6 +892,8 @@ regulator-state-mem {
- 			vdd_cpu_big0_s0: dcdc-reg2 {
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_big0_mem_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <550000>;
- 				regulator-max-microvolt = <1050000>;
- 				regulator-ramp-delay = <12500>;
-@@ -902,6 +906,8 @@ regulator-state-mem {
- 			vdd_cpu_lit_s0: dcdc-reg3 {
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_lit_mem_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <550000>;
- 				regulator-max-microvolt = <950000>;
- 				regulator-ramp-delay = <12500>;
-@@ -926,6 +932,8 @@ regulator-state-mem {
- 			vdd_cpu_big1_mem_s0: dcdc-reg5 {
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_big1_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <675000>;
- 				regulator-max-microvolt = <1050000>;
- 				regulator-ramp-delay = <12500>;
-@@ -939,6 +947,8 @@ regulator-state-mem {
- 			vdd_cpu_big0_mem_s0: dcdc-reg6 {
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_big0_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <675000>;
- 				regulator-max-microvolt = <1050000>;
- 				regulator-ramp-delay = <12500>;
-@@ -963,6 +973,8 @@ regulator-state-mem {
- 			vdd_cpu_lit_mem_s0: dcdc-reg8 {
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_lit_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <675000>;
- 				regulator-max-microvolt = <950000>;
- 				regulator-ramp-delay = <12500>;
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
-@@ -833,6 +833,8 @@ vdd_cpu_big1_s0: dcdc-reg1 {
- 				regulator-name = "vdd_cpu_big1_s0";
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_big1_mem_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <550000>;
- 				regulator-max-microvolt = <1050000>;
- 				regulator-ramp-delay = <12500>;
-@@ -846,6 +848,8 @@ vdd_cpu_big0_s0: dcdc-reg2 {
- 				regulator-name = "vdd_cpu_big0_s0";
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_big0_mem_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <550000>;
- 				regulator-max-microvolt = <1050000>;
- 				regulator-ramp-delay = <12500>;
-@@ -859,6 +863,8 @@ vdd_cpu_lit_s0: dcdc-reg3 {
- 				regulator-name = "vdd_cpu_lit_s0";
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_lit_mem_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <550000>;
- 				regulator-max-microvolt = <950000>;
- 				regulator-ramp-delay = <12500>;
-@@ -885,6 +891,8 @@ vdd_cpu_big1_mem_s0: dcdc-reg5 {
- 				regulator-name = "vdd_cpu_big1_mem_s0";
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_big1_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <675000>;
- 				regulator-max-microvolt = <1050000>;
- 				regulator-ramp-delay = <12500>;
-@@ -899,6 +907,8 @@ vdd_cpu_big0_mem_s0: dcdc-reg6 {
- 				regulator-name = "vdd_cpu_big0_mem_s0";
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_big0_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <675000>;
- 				regulator-max-microvolt = <1050000>;
- 				regulator-ramp-delay = <12500>;
-@@ -925,6 +935,8 @@ vdd_cpu_lit_mem_s0: dcdc-reg8 {
- 				regulator-name = "vdd_cpu_lit_mem_s0";
- 				regulator-always-on;
- 				regulator-boot-on;
-+				regulator-coupled-with = <&vdd_cpu_lit_s0>;
-+				regulator-coupled-max-spread = <10000>;
- 				regulator-min-microvolt = <675000>;
- 				regulator-max-microvolt = <950000>;
- 				regulator-ramp-delay = <12500>;
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 6 May 2024 13:36:37 +0400
-Subject: arm64: dts: rockchip: Add OPP data for CPU cores on RK3588
-
-By default the CPUs on RK3588 start up in a conservative performance
-mode. Add frequency and voltage mappings to the device tree to enable
-dynamic scaling via cpufreq.
-
-OPP values are adapted from Radxa's downstream kernel for Rock 5B [1],
-stripping them down to the minimum frequency and voltage combinations
-as expected by the generic upstream cpufreq-dt driver, and also dropping
-those OPPs that don't differ in voltage but only in frequency (keeping
-the top frequency OPP in each case).
-
-Note that this patch ignores voltage scaling for the CPU memory
-interface which the downstream kernel does through a custom cpufreq
-driver, and which is why the downstream version has two sets of voltage
-values for each OPP (the second one being meant for the memory
-interface supply regulator). This is done instead via regulator
-coupling between CPU and memory interface supplies on affected boards.
-
-This has been tested on Rock 5B with u-boot 2023.11 compiled from
-Collabora's integration tree [2] with binary bl31 and appears to be
-stable both under active cooling and passive cooling (with throttling)
-
-[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 122 ++++++++++
- 1 file changed, 122 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -97,6 +97,7 @@ cpu_l0: cpu@0 {
- 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
- 			assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
- 			assigned-clock-rates = <816000000>;
-+			operating-points-v2 = <&cluster0_opp_table>;
- 			cpu-idle-states = <&CPU_SLEEP>;
- 			i-cache-size = <32768>;
- 			i-cache-line-size = <64>;
-@@ -116,6 +117,7 @@ cpu_l1: cpu@100 {
- 			enable-method = "psci";
- 			capacity-dmips-mhz = <530>;
- 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
-+			operating-points-v2 = <&cluster0_opp_table>;
- 			cpu-idle-states = <&CPU_SLEEP>;
- 			i-cache-size = <32768>;
- 			i-cache-line-size = <64>;
-@@ -135,6 +137,7 @@ cpu_l2: cpu@200 {
- 			enable-method = "psci";
- 			capacity-dmips-mhz = <530>;
- 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
-+			operating-points-v2 = <&cluster0_opp_table>;
- 			cpu-idle-states = <&CPU_SLEEP>;
- 			i-cache-size = <32768>;
- 			i-cache-line-size = <64>;
-@@ -154,6 +157,7 @@ cpu_l3: cpu@300 {
- 			enable-method = "psci";
- 			capacity-dmips-mhz = <530>;
- 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
-+			operating-points-v2 = <&cluster0_opp_table>;
- 			cpu-idle-states = <&CPU_SLEEP>;
- 			i-cache-size = <32768>;
- 			i-cache-line-size = <64>;
-@@ -175,6 +179,7 @@ cpu_b0: cpu@400 {
- 			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
- 			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
- 			assigned-clock-rates = <816000000>;
-+			operating-points-v2 = <&cluster1_opp_table>;
- 			cpu-idle-states = <&CPU_SLEEP>;
- 			i-cache-size = <65536>;
- 			i-cache-line-size = <64>;
-@@ -194,6 +199,7 @@ cpu_b1: cpu@500 {
- 			enable-method = "psci";
- 			capacity-dmips-mhz = <1024>;
- 			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
-+			operating-points-v2 = <&cluster1_opp_table>;
- 			cpu-idle-states = <&CPU_SLEEP>;
- 			i-cache-size = <65536>;
- 			i-cache-line-size = <64>;
-@@ -215,6 +221,7 @@ cpu_b2: cpu@600 {
- 			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
- 			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
- 			assigned-clock-rates = <816000000>;
-+			operating-points-v2 = <&cluster2_opp_table>;
- 			cpu-idle-states = <&CPU_SLEEP>;
- 			i-cache-size = <65536>;
- 			i-cache-line-size = <64>;
-@@ -234,6 +241,7 @@ cpu_b3: cpu@700 {
- 			enable-method = "psci";
- 			capacity-dmips-mhz = <1024>;
- 			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
-+			operating-points-v2 = <&cluster2_opp_table>;
- 			cpu-idle-states = <&CPU_SLEEP>;
- 			i-cache-size = <65536>;
- 			i-cache-line-size = <64>;
-@@ -348,6 +356,120 @@ l3_cache: l3-cache {
- 		};
- 	};
- 
-+	cluster0_opp_table: opp-table-cluster0 {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp-1008000000 {
-+			opp-hz = /bits/ 64 <1008000000>;
-+			opp-microvolt = <675000 675000 950000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt = <712500 712500 950000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-1416000000 {
-+			opp-hz = /bits/ 64 <1416000000>;
-+			opp-microvolt = <762500 762500 950000>;
-+			clock-latency-ns = <40000>;
-+			opp-suspend;
-+		};
-+		opp-1608000000 {
-+			opp-hz = /bits/ 64 <1608000000>;
-+			opp-microvolt = <850000 850000 950000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-1800000000 {
-+			opp-hz = /bits/ 64 <1800000000>;
-+			opp-microvolt = <950000 950000 950000>;
-+			clock-latency-ns = <40000>;
-+		};
-+	};
-+
-+	cluster1_opp_table: opp-table-cluster1 {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp-1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt = <675000 675000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-1416000000 {
-+			opp-hz = /bits/ 64 <1416000000>;
-+			opp-microvolt = <725000 725000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-1608000000 {
-+			opp-hz = /bits/ 64 <1608000000>;
-+			opp-microvolt = <762500 762500 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-1800000000 {
-+			opp-hz = /bits/ 64 <1800000000>;
-+			opp-microvolt = <850000 850000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-2016000000 {
-+			opp-hz = /bits/ 64 <2016000000>;
-+			opp-microvolt = <925000 925000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-2208000000 {
-+			opp-hz = /bits/ 64 <2208000000>;
-+			opp-microvolt = <987500 987500 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-2400000000 {
-+			opp-hz = /bits/ 64 <2400000000>;
-+			opp-microvolt = <1000000 1000000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+	};
-+
-+	cluster2_opp_table: opp-table-cluster2 {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp-1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt = <675000 675000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-1416000000 {
-+			opp-hz = /bits/ 64 <1416000000>;
-+			opp-microvolt = <725000 725000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-1608000000 {
-+			opp-hz = /bits/ 64 <1608000000>;
-+			opp-microvolt = <762500 762500 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-1800000000 {
-+			opp-hz = /bits/ 64 <1800000000>;
-+			opp-microvolt = <850000 850000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-2016000000 {
-+			opp-hz = /bits/ 64 <2016000000>;
-+			opp-microvolt = <925000 925000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-2208000000 {
-+			opp-hz = /bits/ 64 <2208000000>;
-+			opp-microvolt = <987500 987500 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+		opp-2400000000 {
-+			opp-hz = /bits/ 64 <2400000000>;
-+			opp-microvolt = <1000000 1000000 1000000>;
-+			clock-latency-ns = <40000>;
-+		};
-+	};
-+
- 	display_subsystem: display-subsystem {
- 		compatible = "rockchip,display-subsystem";
- 		ports = <&vop_out>;
-- 
-Armbian
-
--- a/kernel.patches/0025-RK3588-Add-HW-RNG-Support.patch
+++ b/kernel.patches/0025-RK3588-Add-HW-RNG-Support.patch
@@ -1,663 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Thu, 16 Nov 2023 17:49:42 +0300
-Subject: hwrng: rockchip: Add support for Rockchip HW RNG
-
---
- drivers/char/hw_random/Kconfig        |  13 +
- drivers/char/hw_random/Makefile       |   1 +
- drivers/char/hw_random/rockchip-rng.c | 574 ++++++++++
- 3 files changed, 588 insertions(+)
-
-diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
-index 111111111111..222222222222 100644
--- a/drivers/char/hw_random/Kconfig
-+++ b/drivers/char/hw_random/Kconfig
-@@ -538,6 +538,19 @@ config HW_RANDOM_XIPHERA
- 	  To compile this driver as a module, choose M here: the
- 	  module will be called xiphera-trng.
- 
-+config HW_RANDOM_ROCKCHIP
-+	tristate "Rockchip Random Number Generator support"
-+	depends on ARCH_ROCKCHIP
-+	default HW_RANDOM
-+	help
-+	  This driver provides kernel-side support for the Random Number
-+	  Generator hardware found on Rockchip cpus.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called rockchip-rng.
-+
-+	  If unsure, say Y.
-+
- config HW_RANDOM_ARM_SMCCC_TRNG
- 	tristate "Arm SMCCC TRNG firmware interface support"
- 	depends on HAVE_ARM_SMCCC_DISCOVERY
-diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
-index 111111111111..222222222222 100644
--- a/drivers/char/hw_random/Makefile
-+++ b/drivers/char/hw_random/Makefile
-@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
- obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
- obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
- obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
-+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
- obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
- obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
- obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
-diff --git a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c
-new file mode 100644
-index 000000000000..111111111111
--- /dev/null
-+++ b/drivers/char/hw_random/rockchip-rng.c
-@@ -0,0 +1,574 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * rockchip-rng.c Random Number Generator driver for the Rockchip
-+ *
-+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
-+ * Author: Lin Jinhan <troy.lin@rock-chips.com>
-+ *
-+ */
-+#include <linux/clk.h>
-+#include <linux/hw_random.h>
-+#include <linux/iopoll.h>
-+#include <linux/module.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+
-+#define _SBF(s, v)	((v) << (s))
-+#define HIWORD_UPDATE(val, mask, shift) \
-+			((val) << (shift) | (mask) << ((shift) + 16))
-+
-+#define ROCKCHIP_AUTOSUSPEND_DELAY		100
-+#define ROCKCHIP_POLL_PERIOD_US			100
-+#define ROCKCHIP_POLL_TIMEOUT_US		50000
-+#define RK_MAX_RNG_BYTE				(32)
-+
-+/* start of CRYPTO V1 register define */
-+#define CRYPTO_V1_CTRL				0x0008
-+#define CRYPTO_V1_RNG_START			BIT(8)
-+#define CRYPTO_V1_RNG_FLUSH			BIT(9)
-+
-+#define CRYPTO_V1_TRNG_CTRL			0x0200
-+#define CRYPTO_V1_OSC_ENABLE			BIT(16)
-+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)		(x)
-+
-+#define CRYPTO_V1_TRNG_DOUT_0			0x0204
-+/* end of CRYPTO V1 register define */
-+
-+/* start of CRYPTO V2 register define */
-+#define CRYPTO_V2_RNG_DEFAULT_OFFSET		0x0400
-+#define CRYPTO_V2_RNG_CTL			0x0
-+#define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
-+#define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
-+#define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
-+#define CRYPTO_V2_RNG_256_BIT_LEN		_SBF(4, 0x03)
-+#define CRYPTO_V2_RNG_FATESY_SOC_RING		_SBF(2, 0x00)
-+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0		_SBF(2, 0x01)
-+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1		_SBF(2, 0x02)
-+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
-+#define CRYPTO_V2_RNG_ENABLE			BIT(1)
-+#define CRYPTO_V2_RNG_START			BIT(0)
-+#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0004
-+#define CRYPTO_V2_RNG_DOUT_0			0x0010
-+/* end of CRYPTO V2 register define */
-+
-+/* start of TRNG_V1 register define */
-+/* TRNG is no longer subordinate to the Crypto module */
-+#define TRNG_V1_CTRL				0x0000
-+#define TRNG_V1_CTRL_NOP			_SBF(0, 0x00)
-+#define TRNG_V1_CTRL_RAND			_SBF(0, 0x01)
-+#define TRNG_V1_CTRL_SEED			_SBF(0, 0x02)
-+
-+#define TRNG_V1_STAT				0x0004
-+#define TRNG_V1_STAT_SEEDED			BIT(9)
-+#define TRNG_V1_STAT_GENERATING			BIT(30)
-+#define TRNG_V1_STAT_RESEEDING			BIT(31)
-+
-+#define TRNG_V1_MODE				0x0008
-+#define TRNG_V1_MODE_128_BIT			_SBF(3, 0x00)
-+#define TRNG_V1_MODE_256_BIT			_SBF(3, 0x01)
-+
-+#define TRNG_V1_IE				0x0010
-+#define TRNG_V1_IE_GLBL_EN			BIT(31)
-+#define TRNG_V1_IE_SEED_DONE_EN			BIT(1)
-+#define TRNG_V1_IE_RAND_RDY_EN			BIT(0)
-+
-+#define TRNG_V1_ISTAT				0x0014
-+#define TRNG_V1_ISTAT_RAND_RDY			BIT(0)
-+
-+/* RAND0 ~ RAND7 */
-+#define TRNG_V1_RAND0				0x0020
-+#define TRNG_V1_RAND7				0x003C
-+
-+#define TRNG_V1_AUTO_RQSTS			0x0060
-+
-+#define TRNG_V1_VERSION				0x00F0
-+#define TRNG_v1_VERSION_CODE			0x46bc
-+/* end of TRNG_V1 register define */
-+
-+/* start of RKRNG register define */
-+#define RKRNG_CTRL				0x0010
-+#define RKRNG_CTRL_INST_REQ			BIT(0)
-+#define RKRNG_CTRL_RESEED_REQ			BIT(1)
-+#define RKRNG_CTRL_TEST_REQ			BIT(2)
-+#define RKRNG_CTRL_SW_DRNG_REQ			BIT(3)
-+#define RKRNG_CTRL_SW_TRNG_REQ			BIT(4)
-+
-+#define RKRNG_STATE				0x0014
-+#define RKRNG_STATE_INST_ACK			BIT(0)
-+#define RKRNG_STATE_RESEED_ACK			BIT(1)
-+#define RKRNG_STATE_TEST_ACK			BIT(2)
-+#define RKRNG_STATE_SW_DRNG_ACK			BIT(3)
-+#define RKRNG_STATE_SW_TRNG_ACK			BIT(4)
-+
-+/* DRNG_DATA_0 ~ DNG_DATA_7 */
-+#define RKRNG_DRNG_DATA_0			0x0070
-+#define RKRNG_DRNG_DATA_7			0x008C
-+
-+/* end of RKRNG register define */
-+
-+struct rk_rng_soc_data {
-+	u32 default_offset;
-+
-+	int (*rk_rng_init)(struct hwrng *rng);
-+	int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
-+};
-+
-+struct rk_rng {
-+	struct device		*dev;
-+	struct hwrng		rng;
-+	void __iomem		*mem;
-+	struct rk_rng_soc_data	*soc_data;
-+	int			clk_num;
-+	struct clk_bulk_data	*clk_bulks;
-+};
-+
-+static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
-+{
-+	__raw_writel(val, rng->mem + offset);
-+}
-+
-+static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
-+{
-+	return __raw_readl(rng->mem + offset);
-+}
-+
-+static int rk_rng_init(struct hwrng *rng)
-+{
-+	int ret;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
-+
-+	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
-+	if (ret < 0) {
-+		dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static void rk_rng_cleanup(struct hwrng *rng)
-+{
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
-+	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
-+}
-+
-+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	int ret;
-+	int read_len = 0;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	if (!rk_rng->soc_data->rk_rng_read)
-+		return -EFAULT;
-+
-+	ret = pm_runtime_get_sync(rk_rng->dev);
-+	if (ret < 0) {
-+		pm_runtime_put_noidle(rk_rng->dev);
-+		return ret;
-+	}
-+
-+	ret = 0;
-+	while (max > ret) {
-+		read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
-+							 max - ret, wait);
-+		if (read_len < 0) {
-+			ret = read_len;
-+			break;
-+		}
-+		ret += read_len;
-+	}
-+
-+	pm_runtime_mark_last_busy(rk_rng->dev);
-+	pm_runtime_put_sync_autosuspend(rk_rng->dev);
-+
-+	return ret;
-+}
-+
-+static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
-+			     size_t size)
-+{
-+	u32 i;
-+
-+	for (i = 0; i < size; i += 4)
-+		*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
-+}
-+
-+static int crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	int ret = 0;
-+	u32 reg_ctrl = 0;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	/* enable osc_ring to get entropy, sample period is set as 100 */
-+	reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
-+	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
-+
-+	reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
-+
-+	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
-+
-+	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
-+				!(reg_ctrl & CRYPTO_V1_RNG_START),
-+				ROCKCHIP_POLL_PERIOD_US,
-+				ROCKCHIP_POLL_TIMEOUT_US, false,
-+				rk_rng, CRYPTO_V1_CTRL);
-+
-+	if (ret < 0)
-+		goto out;
-+
-+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
-+
-+	rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
-+
-+out:
-+	/* close TRNG */
-+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
-+		      CRYPTO_V1_CTRL);
-+
-+	return ret;
-+}
-+
-+static int crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	int ret = 0;
-+	u32 reg_ctrl = 0;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	/* enable osc_ring to get entropy, sample period is set as 100 */
-+	rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
-+
-+	reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
-+	reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
-+	reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
-+	reg_ctrl |= CRYPTO_V2_RNG_START;
-+
-+	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
-+		      CRYPTO_V2_RNG_CTL);
-+
-+	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
-+				!(reg_ctrl & CRYPTO_V2_RNG_START),
-+				ROCKCHIP_POLL_PERIOD_US,
-+				ROCKCHIP_POLL_TIMEOUT_US, false,
-+				rk_rng, CRYPTO_V2_RNG_CTL);
-+	if (ret < 0)
-+		goto out;
-+
-+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
-+
-+	rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
-+
-+out:
-+	/* close TRNG */
-+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
-+
-+	return ret;
-+}
-+
-+static int trng_v1_init(struct hwrng *rng)
-+{
-+	int ret;
-+	uint32_t auto_reseed_cnt = 1000;
-+	uint32_t reg_ctrl, status, version;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
-+	if (version != TRNG_v1_VERSION_CODE) {
-+		dev_err(rk_rng->dev,
-+			"wrong trng version, expected = %08x, actual = %08x\n",
-+			TRNG_V1_VERSION, version);
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+
-+	status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
-+
-+	/* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
-+	if (!(status & TRNG_V1_STAT_SEEDED) ||
-+	    (status & TRNG_V1_STAT_GENERATING) ||
-+	    (status & TRNG_V1_STAT_RESEEDING)) {
-+		uint32_t mask = TRNG_V1_STAT_SEEDED |
-+				TRNG_V1_STAT_GENERATING |
-+				TRNG_V1_STAT_RESEEDING;
-+
-+		udelay(10);
-+
-+		/* wait for GENERATING and RESEEDING flag to clear */
-+		read_poll_timeout(rk_rng_readl, reg_ctrl,
-+				  (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
-+				  ROCKCHIP_POLL_PERIOD_US,
-+				  ROCKCHIP_POLL_TIMEOUT_US, false,
-+				  rk_rng, TRNG_V1_STAT);
-+	}
-+
-+	/* clear ISTAT flag because trng may auto reseeding when power on */
-+	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
-+	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
-+
-+	/* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
-+	rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
-+
-+	ret = 0;
-+exit:
-+
-+	return ret;
-+}
-+
-+static int trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	int ret = 0;
-+	u32 reg_ctrl = 0;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	/* clear ISTAT anyway */
-+	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
-+	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
-+
-+	/* generate 256bit random */
-+	rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
-+	rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
-+
-+	/*
-+	 * Generate2 56 bit random data will cost 1024 clock cycles.
-+	 * Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
-+	 */
-+	udelay(10);
-+	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
-+	if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
-+		/* wait RAND_RDY triggered */
-+		ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
-+					(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
-+					ROCKCHIP_POLL_PERIOD_US,
-+					ROCKCHIP_POLL_TIMEOUT_US, false,
-+					rk_rng, TRNG_V1_ISTAT);
-+		if (ret < 0)
-+			goto out;
-+	}
-+
-+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
-+
-+	rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
-+
-+	/* clear all status flag */
-+	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
-+out:
-+	/* close TRNG */
-+	rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
-+
-+	return ret;
-+}
-+
-+static int rkrng_init(struct hwrng *rng)
-+{
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+	u32 reg = 0;
-+
-+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
-+
-+	reg = rk_rng_readl(rk_rng, RKRNG_STATE);
-+	rk_rng_writel(rk_rng, reg, RKRNG_STATE);
-+
-+	return 0;
-+}
-+
-+static int rkrng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+	u32 reg_ctrl = 0;
-+	int ret;
-+
-+	reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ;
-+
-+	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL);
-+
-+	ret = readl_poll_timeout(rk_rng->mem + RKRNG_STATE, reg_ctrl,
-+				 (reg_ctrl & RKRNG_STATE_SW_DRNG_ACK),
-+				 ROCKCHIP_POLL_PERIOD_US,
-+				 ROCKCHIP_POLL_TIMEOUT_US);
-+
-+	if (ret)
-+		goto exit;
-+
-+	rk_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE);
-+
-+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
-+
-+	rk_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, ret);
-+
-+exit:
-+	/* close TRNG */
-+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
-+
-+	return ret;
-+}
-+
-+static const struct rk_rng_soc_data crypto_v1_soc_data = {
-+	.default_offset = 0,
-+
-+	.rk_rng_read = crypto_v1_read,
-+};
-+
-+static const struct rk_rng_soc_data crypto_v2_soc_data = {
-+	.default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
-+
-+	.rk_rng_read = crypto_v2_read,
-+};
-+
-+static const struct rk_rng_soc_data trng_v1_soc_data = {
-+	.default_offset = 0,
-+
-+	.rk_rng_init = trng_v1_init,
-+	.rk_rng_read = trng_v1_read,
-+};
-+
-+static const struct rk_rng_soc_data rkrng_soc_data = {
-+	.default_offset = 0,
-+
-+	.rk_rng_init = rkrng_init,
-+	.rk_rng_read = rkrng_read,
-+};
-+
-+static const struct of_device_id rk_rng_dt_match[] = {
-+	{
-+		.compatible = "rockchip,cryptov1-rng",
-+		.data = (void *)&crypto_v1_soc_data,
-+	},
-+	{
-+		.compatible = "rockchip,cryptov2-rng",
-+		.data = (void *)&crypto_v2_soc_data,
-+	},
-+	{
-+		.compatible = "rockchip,trngv1",
-+		.data = (void *)&trng_v1_soc_data,
-+	},
-+		{
-+		.compatible = "rockchip,rkrng",
-+		.data = (void *)&rkrng_soc_data,
-+	},
-+	{ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
-+
-+static int rk_rng_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+	struct rk_rng *rk_rng;
-+	struct device_node *np = pdev->dev.of_node;
-+	const struct of_device_id *match;
-+	resource_size_t map_size;
-+
-+	dev_dbg(&pdev->dev, "probing...\n");
-+	rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
-+	if (!rk_rng)
-+		return -ENOMEM;
-+
-+	match = of_match_node(rk_rng_dt_match, np);
-+	rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
-+
-+	rk_rng->dev = &pdev->dev;
-+	rk_rng->rng.name    = "rockchip";
-+#ifndef CONFIG_PM
-+	rk_rng->rng.init    = rk_rng_init;
-+	rk_rng->rng.cleanup = rk_rng_cleanup,
-+#endif
-+	rk_rng->rng.read    = rk_rng_read;
-+	rk_rng->rng.quality = 999;
-+
-+	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
-+	if (IS_ERR(rk_rng->mem))
-+		return PTR_ERR(rk_rng->mem);
-+
-+	/* compatible with crypto v2 module */
-+	/*
-+	 * With old dtsi configurations, the RNG base was equal to the crypto
-+	 * base, so both drivers could not be enabled at the same time.
-+	 * RNG base = CRYPTO base + RNG offset
-+	 * (Since RK356X, RNG module is no longer belongs to CRYPTO module)
-+	 *
-+	 * With new dtsi configurations, CRYPTO regs is divided into two parts
-+	 * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
-+	 * RNG driver and CRYPTO driver could be enabled at the same time.
-+	 */
-+	if (map_size > rk_rng->soc_data->default_offset)
-+		rk_rng->mem += rk_rng->soc_data->default_offset;
-+
-+	rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
-+	if (rk_rng->clk_num < 0) {
-+		dev_err(&pdev->dev, "failed to get clks property\n");
-+		return -ENODEV;
-+	}
-+
-+	platform_set_drvdata(pdev, rk_rng);
-+
-+	pm_runtime_set_autosuspend_delay(&pdev->dev,
-+					 ROCKCHIP_AUTOSUSPEND_DELAY);
-+	pm_runtime_use_autosuspend(&pdev->dev);
-+	pm_runtime_enable(&pdev->dev);
-+
-+	ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
-+	if (ret) {
-+		pm_runtime_dont_use_autosuspend(&pdev->dev);
-+		pm_runtime_disable(&pdev->dev);
-+	}
-+
-+	/* for some platform need hardware operation when probe */
-+	if (rk_rng->soc_data->rk_rng_init) {
-+		pm_runtime_get_sync(rk_rng->dev);
-+
-+		ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
-+
-+		pm_runtime_mark_last_busy(rk_rng->dev);
-+		pm_runtime_put_sync_autosuspend(rk_rng->dev);
-+	}
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_PM
-+static int rk_rng_runtime_suspend(struct device *dev)
-+{
-+	struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+	rk_rng_cleanup(&rk_rng->rng);
-+
-+	return 0;
-+}
-+
-+static int rk_rng_runtime_resume(struct device *dev)
-+{
-+	struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+	return rk_rng_init(&rk_rng->rng);
-+}
-+
-+static const struct dev_pm_ops rk_rng_pm_ops = {
-+	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
-+			   rk_rng_runtime_resume, NULL)
-+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
-+				pm_runtime_force_resume)
-+};
-+
-+#endif
-+
-+static struct platform_driver rk_rng_driver = {
-+	.driver	= {
-+		.name	= "rockchip-rng",
-+#ifdef CONFIG_PM
-+		.pm	= &rk_rng_pm_ops,
-+#endif
-+		.of_match_table = rk_rng_dt_match,
-+	},
-+	.probe	= rk_rng_probe,
-+};
-+
-+module_platform_driver(rk_rng_driver);
-+
-+MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
-+MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
-+MODULE_LICENSE("GPL v2");
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Thu, 16 Nov 2023 17:52:35 +0300
-Subject: arm64: dts: Add HW RNG support to RK3588S
-
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1935,6 +1935,16 @@ crypto: crypto@fe370000 {
- 		status = "okay";
- 	};
- 
-+	rng: rng@fe378000 {
-+		compatible = "rockchip,trngv1";
-+		reg = <0x0 0xfe378000 0x0 0x200>;
-+		interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
-+		clock-names = "hclk_trng";
-+		resets = <&scmi_reset SRST_H_TRNG_NS>;
-+		reset-names = "reset";
-+	};
-+
- 	i2s0_8ch: i2s@fe470000 {
- 		compatible = "rockchip,rk3588-i2s-tdm";
- 		reg = <0x0 0xfe470000 0x0 0x1000>;
-- 
-Armbian
-
--- a/kernel.patches/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch
+++ b/kernel.patches/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch
@@ -1,311 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Thu, 13 Jun 2024 15:48:42 +0200
-Subject: media: dt-bindings: rk3568-vepu: Add RK3588 VEPU121
-
-From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
-
-This encoder-only device is present four times on this SoC, and should
-support everything the rk3568 vepu supports (so JPEG, H.264 and VP8
-encoding). No fallback compatible has been added, since the operating
-systems might already support RK3568 VEPU and want to avoid registering
-four of them separately considering they can be used as a cluster.
-
-Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
- Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
-index 111111111111..222222222222 100644
--- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
-+++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
-@@ -17,6 +17,7 @@ properties:
-   compatible:
-     enum:
-       - rockchip,rk3568-vepu
-+      - rockchip,rk3588-vepu121
- 
-   reg:
-     maxItems: 1
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Thu, 13 Jun 2024 15:48:44 +0200
-Subject: media: hantro: Disable multicore support
-
-Avoid exposing equal Hantro video codecs to userspace. Equal video
-codecs allow scheduling work between the cores. For that kernel support
-is required, which does not yet exist. Until that is implemented avoid
-exposing each core separately to userspace so that multicore can be
-added in the future without breaking userspace ABI.
-
-This was written with Rockchip RK3588 in mind (which has 4 Hantro H1
-cores), but applies to all SoCs.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
- drivers/media/platform/verisilicon/hantro_drv.c | 37 ++++++++++
- 1 file changed, 37 insertions(+)
-
-diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
-index 111111111111..222222222222 100644
--- a/drivers/media/platform/verisilicon/hantro_drv.c
-+++ b/drivers/media/platform/verisilicon/hantro_drv.c
-@@ -992,6 +992,39 @@ static const struct media_device_ops hantro_m2m_media_ops = {
- 	.req_queue = v4l2_m2m_request_queue,
- };
- 
-+/*
-+ * Some SoCs, like RK3588 have multiple identical Hantro cores, but the
-+ * kernel is currently missing support for multi-core handling. Exposing
-+ * separate devices for each core to userspace is bad, since that does
-+ * not allow scheduling tasks properly (and creates ABI). With this workaround
-+ * the driver will only probe for the first core and early exit for the other
-+ * cores. Once the driver gains multi-core support, the same technique
-+ * for detecting the main core can be used to cluster all cores together.
-+ */
-+static int hantro_disable_multicore(struct hantro_dev *vpu)
-+{
-+	const char *compatible;
-+	struct device_node *node;
-+	int ret;
-+
-+	/* Intentionally ignores the fallback strings */
-+	ret = of_property_read_string(vpu->dev->of_node, "compatible", &compatible);
-+	if (ret)
-+		return ret;
-+
-+	/* first compatible node found from the root node is considered the main core */
-+	node = of_find_compatible_node(NULL, NULL, compatible);
-+	if (!node)
-+		return -EINVAL; /* broken DT? */
-+
-+	if (vpu->dev->of_node != node) {
-+		dev_info(vpu->dev, "missing multi-core support, ignoring this instance\n");
-+		return -ENODEV;
-+	}
-+
-+	return 0;
-+}
-+
- static int hantro_probe(struct platform_device *pdev)
- {
- 	const struct of_device_id *match;
-@@ -1011,6 +1044,10 @@ static int hantro_probe(struct platform_device *pdev)
- 	match = of_match_node(of_hantro_match, pdev->dev.of_node);
- 	vpu->variant = match->data;
- 
-+	ret = hantro_disable_multicore(vpu);
-+	if (ret)
-+		return ret;
-+
- 	/*
- 	 * Support for nxp,imx8mq-vpu is kept for backwards compatibility
- 	 * but it's deprecated. Please update your DTS file to use
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Thu, 13 Jun 2024 15:48:45 +0200
-Subject: media: hantro: Add RK3588 VEPU121
-
-RK3588 handling is exactly the same as RK3568. This is not
-handled using fallback compatibles to avoid exposing multiple
-video devices on kernels not having the multicore disable
-patch.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
- drivers/media/platform/verisilicon/hantro_drv.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
-index 111111111111..222222222222 100644
--- a/drivers/media/platform/verisilicon/hantro_drv.c
-+++ b/drivers/media/platform/verisilicon/hantro_drv.c
-@@ -722,6 +722,7 @@ static const struct of_device_id of_hantro_match[] = {
- 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
- 	{ .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
- 	{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
-+	{ .compatible = "rockchip,rk3588-vepu121", .data = &rk3568_vepu_variant, },
- 	{ .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, },
- #endif
- #ifdef CONFIG_VIDEO_HANTRO_IMX8M
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Thu, 13 Jun 2024 15:48:46 +0200
-Subject: arm64: dts: rockchip: Add VEPU121 to RK3588
-
-From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
-
-RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
-but can be used as a cluster (i.e. sharing work between the cores).
-These cores are called VEPU121 in the TRM. The TRM describes one more
-VEPU121, but that is combined with a Hantro H1. That one will be handled
-using the VPU binding instead.
-
-Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 ++++++++++
- 1 file changed, 80 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1282,6 +1282,86 @@ power-domain@RK3588_PD_SDMMC {
- 		};
- 	};
- 
-+	vepu121_0: video-codec@fdba0000 {
-+		compatible = "rockchip,rk3588-vepu121";
-+		reg = <0x0 0xfdba0000 0x0 0x800>;
-+		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
-+		clock-names = "aclk", "hclk";
-+		iommus = <&vepu121_0_mmu>;
-+		power-domains = <&power RK3588_PD_VDPU>;
-+	};
-+
-+	vepu121_0_mmu: iommu@fdba0800 {
-+		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-+		reg = <0x0 0xfdba0800 0x0 0x40>;
-+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
-+		clock-names = "aclk", "iface";
-+		power-domains = <&power RK3588_PD_VDPU>;
-+		#iommu-cells = <0>;
-+	};
-+
-+	vepu121_1: video-codec@fdba4000 {
-+		compatible = "rockchip,rk3588-vepu121";
-+		reg = <0x0 0xfdba4000 0x0 0x800>;
-+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
-+		clock-names = "aclk", "hclk";
-+		iommus = <&vepu121_1_mmu>;
-+		power-domains = <&power RK3588_PD_VDPU>;
-+	};
-+
-+	vepu121_1_mmu: iommu@fdba4800 {
-+		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-+		reg = <0x0 0xfdba4800 0x0 0x40>;
-+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
-+		clock-names = "aclk", "iface";
-+		power-domains = <&power RK3588_PD_VDPU>;
-+		#iommu-cells = <0>;
-+	};
-+
-+	vepu121_2: video-codec@fdba8000 {
-+		compatible = "rockchip,rk3588-vepu121";
-+		reg = <0x0 0xfdba8000 0x0 0x800>;
-+		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
-+		clock-names = "aclk", "hclk";
-+		iommus = <&vepu121_2_mmu>;
-+		power-domains = <&power RK3588_PD_VDPU>;
-+	};
-+
-+	vepu121_2_mmu: iommu@fdba8800 {
-+		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-+		reg = <0x0 0xfdba8800 0x0 0x40>;
-+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
-+		clock-names = "aclk", "iface";
-+		power-domains = <&power RK3588_PD_VDPU>;
-+		#iommu-cells = <0>;
-+	};
-+
-+	vepu121_3: video-codec@fdbac000 {
-+		compatible = "rockchip,rk3588-vepu121";
-+		reg = <0x0 0xfdbac000 0x0 0x800>;
-+		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
-+		clock-names = "aclk", "hclk";
-+		iommus = <&vepu121_3_mmu>;
-+		power-domains = <&power RK3588_PD_VDPU>;
-+	};
-+
-+	vepu121_3_mmu: iommu@fdbac800 {
-+		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-+		reg = <0x0 0xfdbac800 0x0 0x40>;
-+		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
-+		clock-names = "aclk", "iface";
-+		power-domains = <&power RK3588_PD_VDPU>;
-+		#iommu-cells = <0>;
-+	};
-+
- 	av1d: video-codec@fdc70000 {
- 		compatible = "rockchip,rk3588-av1-vpu";
- 		reg = <0x0 0xfdc70000 0x0 0x800>;
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Thu, 13 Jun 2024 15:48:47 +0200
-Subject: arm64: dts: rockchip: Add VPU121 support for RK3588
-
-From: Jianfeng Liu <liujianfeng1994@gmail.com>
-
-Enable Hantro G1 video decoder in RK3588's devicetree.
-
-Tested with FFmpeg v4l2_request code taken from [1]
-with MPEG2, H.264 and VP8 samples.
-
-[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
-
-Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
-Tested-by: Hugh Cole-Baker <sigmaris@gmail.com>
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++
- 1 file changed, 22 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1282,6 +1282,28 @@ power-domain@RK3588_PD_SDMMC {
- 		};
- 	};
- 
-+	vpu121: video-codec@fdb50000 {
-+		compatible = "rockchip,rk3588-vpu121", "rockchip,rk3399-vpu";
-+		reg = <0x0 0xfdb50000 0x0 0x800>;
-+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>,
-+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
-+		interrupt-names = "vepu", "vdpu";
-+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
-+		clock-names = "aclk", "hclk";
-+		iommus = <&vpu121_mmu>;
-+		power-domains = <&power RK3588_PD_VDPU>;
-+	};
-+
-+	vpu121_mmu: iommu@fdb50800 {
-+		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-+		reg = <0x0 0xfdb50800 0x0 0x40>;
-+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clock-names = "aclk", "iface";
-+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
-+		power-domains = <&power RK3588_PD_VDPU>;
-+		#iommu-cells = <0>;
-+	};
-+
- 	vepu121_0: video-codec@fdba0000 {
- 		compatible = "rockchip,rk3588-vepu121";
- 		reg = <0x0 0xfdba0000 0x0 0x800>;
-- 
-Armbian
-
--- a/kernel.patches/0027-RK3588-Add-rkvdec2-Support-v3.patch
+++ b/kernel.patches/0027-RK3588-Add-rkvdec2-Support-v3.patch
--- a/kernel.patches/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch
+++ b/kernel.patches/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch
@@ -1,81 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
-Date: Mon, 15 Jan 2024 22:47:41 +0200
-Subject: arm64: dts: rockchip: Add HDMI0 bridge to rk3588
-
-Add DT node for the HDMI0 bridge found on RK3588 SoC.
-
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 55 ++++++++++
- 1 file changed, 55 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1516,6 +1516,61 @@ i2s9_8ch: i2s@fddfc000 {
- 		status = "disabled";
- 	};
- 
-+	hdmi0: hdmi@fde80000 {
-+		compatible = "rockchip,rk3588-dw-hdmi";
-+		reg = <0x0 0xfde80000 0x0 0x20000>;
-+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
-+			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
-+			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
-+			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
-+			     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru PCLK_HDMITX0>,
-+			 <&cru CLK_HDMIHDP0>,
-+			 <&cru CLK_HDMITX0_EARC>,
-+			 <&cru CLK_HDMITX0_REF>,
-+			 <&cru MCLK_I2S5_8CH_TX>,
-+			 <&cru DCLK_VOP0>,
-+			 <&cru DCLK_VOP1>,
-+			 <&cru DCLK_VOP2>,
-+			 <&cru DCLK_VOP3>,
-+			 <&cru HCLK_VO1>;
-+		clock-names = "pclk",
-+			      "hpd",
-+			      "earc",
-+			      "hdmitx_ref",
-+			      "aud",
-+			      "dclk_vp0",
-+			      "dclk_vp1",
-+			      "dclk_vp2",
-+			      "dclk_vp3",
-+			      "hclk_vo1";
-+		resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
-+		reset-names = "ref", "hdp";
-+		power-domains = <&power RK3588_PD_VO1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
-+			     &hdmim0_tx0_scl &hdmim0_tx0_sda>;
-+		reg-io-width = <4>;
-+		rockchip,grf = <&sys_grf>;
-+		rockchip,vo1_grf = <&vo1_grf>;
-+		phys = <&hdptxphy_hdmi0>;
-+		phy-names = "hdmi";
-+		status = "disabled";
-+
-+		ports {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			hdmi0_in: port@0 {
-+				reg = <0>;
-+			};
-+
-+			hdmi0_out: port@1 {
-+				reg = <1>;
-+			};
-+		};
-+	};
-+
- 	qos_gpu_m0: qos@fdf35000 {
- 		compatible = "rockchip,rk3588-qos", "syscon";
- 		reg = <0x0 0xfdf35000 0x0 0x20>;
-- 
-Armbian
-
--- a/kernel.patches/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch
+++ b/kernel.patches/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch
@@ -1,26 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
-Date: Tue, 16 Jan 2024 03:13:38 +0200
-Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on rk3588
-
-The HDMI0 PHY can be used as a clock provider on RK3588, hence add the
-missing #clock-cells property.
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -2985,6 +2985,7 @@ hdptxphy_hdmi0: phy@fed60000 {
- 		reg = <0x0 0xfed60000 0x0 0x2000>;
- 		clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
- 		clock-names = "ref", "apb";
-+		#clock-cells = <0>;
- 		#phy-cells = <0>;
- 		resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
- 			 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
-- 
-Armbian
-
--- a/kernel.patches/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch
+++ b/kernel.patches/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch
@@ -1,549 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
-Date: Mon, 5 Feb 2024 01:38:48 +0200
-Subject: phy: phy-rockchip-samsung-hdptx: Add FRL & EARC support
-
-For upstreaming, this requires extending the standard PHY API to support
-HDMI configuration options [1].
-
-Currently, the bus_width PHY attribute is used to pass clock rate and
-flags for 10-bit color depth, FRL and EARC. This is done by the HDMI
-bridge driver via phy_set_bus_width().
-
-[1]: https://lore.kernel.org/all/59d5595a24bbcca897e814440179fa2caf3dff38.1707040881.git.Sandor.yu@nxp.com/
-
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 434 +++++++++-
- 1 file changed, 431 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
-index 111111111111..222222222222 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
-+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
-@@ -190,6 +190,12 @@
- #define LN3_TX_SER_RATE_SEL_HBR2	BIT(3)
- #define LN3_TX_SER_RATE_SEL_HBR3	BIT(2)
- 
-+#define HDMI20_MAX_RATE			600000000
-+#define DATA_RATE_MASK			0xFFFFFFF
-+#define COLOR_DEPTH_MASK		BIT(31)
-+#define HDMI_MODE_MASK			BIT(30)
-+#define HDMI_EARC_MASK			BIT(29)
-+
- struct lcpll_config {
- 	u32 bit_rate;
- 	u8 lcvco_mode_en;
-@@ -272,6 +278,25 @@ struct rk_hdptx_phy {
- 	struct clk_bulk_data *clks;
- 	int nr_clks;
- 	struct reset_control_bulk_data rsts[RST_MAX];
-+	bool earc_en;
-+};
-+
-+static const struct lcpll_config lcpll_cfg[] = {
-+	{ 48000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2,
-+	  0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, },
-+	{ 40000000, 1, 1, 0, 0x68, 0x68, 1, 1, 0, 0, 0, 1, 1, 1, 1, 9, 0, 1, 1,
-+	  0, 2, 3, 1, 0, 0x20, 0x0c, 1, 0, },
-+	{ 32000000, 1, 1, 1, 0x6b, 0x6b, 1, 1, 0, 1, 2, 1, 1, 1, 1, 9, 1, 2, 1,
-+	  0, 0x0d, 0x18, 1, 0, 0x20, 0x0c, 1, 1, },
-+};
-+
-+static const struct ropll_config ropll_frl_cfg[] = {
-+	{ 24000000, 0x19, 0x19, 1, 1, 0, 1, 2, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1,
-+	  0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
-+	{ 18000000, 0x7d, 0x7d, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1,
-+	  0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
-+	{ 9000000, 0x7d, 0x7d, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1,
-+	  0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
- };
- 
- static const struct ropll_config ropll_tmds_cfg[] = {
-@@ -449,6 +474,73 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
- 	REG_SEQ0(CMN_REG(009b), 0x00),
- };
- 
-+static const struct reg_sequence rk_hdtpx_frl_cmn_init_seq[] = {
-+	REG_SEQ0(CMN_REG(0011), 0x00),
-+	REG_SEQ0(CMN_REG(0017), 0x00),
-+	REG_SEQ0(CMN_REG(0026), 0x53),
-+	REG_SEQ0(CMN_REG(0030), 0x00),
-+	REG_SEQ0(CMN_REG(0031), 0x20),
-+	REG_SEQ0(CMN_REG(0032), 0x30),
-+	REG_SEQ0(CMN_REG(0033), 0x0b),
-+	REG_SEQ0(CMN_REG(0034), 0x23),
-+	REG_SEQ0(CMN_REG(0042), 0xb8),
-+	REG_SEQ0(CMN_REG(004e), 0x14),
-+	REG_SEQ0(CMN_REG(0074), 0x00),
-+	REG_SEQ0(CMN_REG(0081), 0x09),
-+	REG_SEQ0(CMN_REG(0086), 0x01),
-+	REG_SEQ0(CMN_REG(0087), 0x0c),
-+	REG_SEQ0(CMN_REG(009b), 0x10),
-+};
-+
-+static const struct reg_sequence rk_hdtpx_frl_ropll_cmn_init_seq[] = {
-+	REG_SEQ0(CMN_REG(0008), 0x00),
-+	REG_SEQ0(CMN_REG(001e), 0x14),
-+	REG_SEQ0(CMN_REG(0020), 0x00),
-+	REG_SEQ0(CMN_REG(0021), 0x00),
-+	REG_SEQ0(CMN_REG(0022), 0x11),
-+	REG_SEQ0(CMN_REG(0023), 0x00),
-+	REG_SEQ0(CMN_REG(0025), 0x00),
-+	REG_SEQ0(CMN_REG(0027), 0x00),
-+	REG_SEQ0(CMN_REG(0028), 0x00),
-+	REG_SEQ0(CMN_REG(002a), 0x01),
-+	REG_SEQ0(CMN_REG(002b), 0x00),
-+	REG_SEQ0(CMN_REG(002c), 0x00),
-+	REG_SEQ0(CMN_REG(002d), 0x00),
-+	REG_SEQ0(CMN_REG(002e), 0x00),
-+	REG_SEQ0(CMN_REG(002f), 0x04),
-+	REG_SEQ0(CMN_REG(003d), 0x40),
-+	REG_SEQ0(CMN_REG(005c), 0x25),
-+	REG_SEQ0(CMN_REG(0089), 0x00),
-+	REG_SEQ0(CMN_REG(0094), 0x00),
-+	REG_SEQ0(CMN_REG(0097), 0x02),
-+	REG_SEQ0(CMN_REG(0099), 0x04),
-+};
-+
-+static const struct reg_sequence rk_hdtpx_frl_lcpll_cmn_init_seq[] = {
-+	REG_SEQ0(CMN_REG(0025), 0x10),
-+	REG_SEQ0(CMN_REG(0027), 0x01),
-+	REG_SEQ0(CMN_REG(0028), 0x0d),
-+	REG_SEQ0(CMN_REG(002e), 0x02),
-+	REG_SEQ0(CMN_REG(002f), 0x0d),
-+	REG_SEQ0(CMN_REG(003d), 0x00),
-+	REG_SEQ0(CMN_REG(0051), 0x00),
-+	REG_SEQ0(CMN_REG(0055), 0x00),
-+	REG_SEQ0(CMN_REG(0059), 0x11),
-+	REG_SEQ0(CMN_REG(005a), 0x03),
-+	REG_SEQ0(CMN_REG(005c), 0x05),
-+	REG_SEQ0(CMN_REG(005e), 0x07),
-+	REG_SEQ0(CMN_REG(0060), 0x01),
-+	REG_SEQ0(CMN_REG(0064), 0x07),
-+	REG_SEQ0(CMN_REG(0065), 0x00),
-+	REG_SEQ0(CMN_REG(0069), 0x00),
-+	REG_SEQ0(CMN_REG(006c), 0x00),
-+	REG_SEQ0(CMN_REG(0070), 0x01),
-+	REG_SEQ0(CMN_REG(0089), 0x02),
-+	REG_SEQ0(CMN_REG(0095), 0x00),
-+	REG_SEQ0(CMN_REG(0097), 0x00),
-+	REG_SEQ0(CMN_REG(0099), 0x00),
-+};
-+
- static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
- 	REG_SEQ0(SB_REG(0114), 0x00),
- 	REG_SEQ0(SB_REG(0115), 0x00),
-@@ -472,6 +564,17 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
- 	REG_SEQ0(LNTOP_REG(0205), 0x1f),
- };
- 
-+static const struct reg_sequence rk_hdtpx_frl_lntop_init_seq[] = {
-+	REG_SEQ0(LNTOP_REG(0200), 0x04),
-+	REG_SEQ0(LNTOP_REG(0201), 0x00),
-+	REG_SEQ0(LNTOP_REG(0202), 0x00),
-+	REG_SEQ0(LNTOP_REG(0203), 0xf0),
-+	REG_SEQ0(LNTOP_REG(0204), 0xff),
-+	REG_SEQ0(LNTOP_REG(0205), 0xff),
-+	REG_SEQ0(LNTOP_REG(0206), 0x05),
-+	REG_SEQ0(LNTOP_REG(0207), 0x0f),
-+};
-+
- static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
- 	REG_SEQ0(LANE_REG(0303), 0x0c),
- 	REG_SEQ0(LANE_REG(0307), 0x20),
-@@ -550,6 +653,40 @@ static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
- 	REG_SEQ0(LANE_REG(0606), 0x1c),
- };
- 
-+static const struct reg_sequence rk_hdtpx_frl_ropll_lane_init_seq[] = {
-+	REG_SEQ0(LANE_REG(0312), 0x3c),
-+	REG_SEQ0(LANE_REG(0412), 0x3c),
-+	REG_SEQ0(LANE_REG(0512), 0x3c),
-+	REG_SEQ0(LANE_REG(0612), 0x3c),
-+};
-+
-+static const struct reg_sequence rk_hdtpx_frl_lcpll_lane_init_seq[] = {
-+	REG_SEQ0(LANE_REG(0312), 0x3c),
-+	REG_SEQ0(LANE_REG(0412), 0x3c),
-+	REG_SEQ0(LANE_REG(0512), 0x3c),
-+	REG_SEQ0(LANE_REG(0612), 0x3c),
-+	REG_SEQ0(LANE_REG(0303), 0x2f),
-+	REG_SEQ0(LANE_REG(0403), 0x2f),
-+	REG_SEQ0(LANE_REG(0503), 0x2f),
-+	REG_SEQ0(LANE_REG(0603), 0x2f),
-+	REG_SEQ0(LANE_REG(0305), 0x03),
-+	REG_SEQ0(LANE_REG(0405), 0x03),
-+	REG_SEQ0(LANE_REG(0505), 0x03),
-+	REG_SEQ0(LANE_REG(0605), 0x03),
-+	REG_SEQ0(LANE_REG(0306), 0xfc),
-+	REG_SEQ0(LANE_REG(0406), 0xfc),
-+	REG_SEQ0(LANE_REG(0506), 0xfc),
-+	REG_SEQ0(LANE_REG(0606), 0xfc),
-+	REG_SEQ0(LANE_REG(0305), 0x4f),
-+	REG_SEQ0(LANE_REG(0405), 0x4f),
-+	REG_SEQ0(LANE_REG(0505), 0x4f),
-+	REG_SEQ0(LANE_REG(0605), 0x4f),
-+	REG_SEQ0(LANE_REG(0304), 0x14),
-+	REG_SEQ0(LANE_REG(0404), 0x14),
-+	REG_SEQ0(LANE_REG(0504), 0x14),
-+	REG_SEQ0(LANE_REG(0604), 0x14),
-+};
-+
- static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
- {
- 	switch (reg) {
-@@ -651,6 +788,47 @@ static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
- 	return 0;
- }
- 
-+static int rk_hdptx_post_power_up(struct rk_hdptx_phy *hdptx)
-+{
-+	u32 val;
-+	int ret;
-+
-+	val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
-+	       HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
-+	regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
-+
-+	usleep_range(10, 15);
-+	reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
-+
-+	usleep_range(10, 15);
-+	val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
-+	regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
-+
-+	usleep_range(10, 15);
-+	reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
-+
-+	ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
-+				       val & HDPTX_O_PLL_LOCK_DONE, 20, 400);
-+	if (ret) {
-+		dev_err(hdptx->dev, "Failed to get PHY PLL lock: %d\n", ret);
-+		return ret;
-+	}
-+
-+	usleep_range(20, 30);
-+	reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
-+
-+	ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
-+				       val & HDPTX_O_PHY_RDY, 100, 5000);
-+	if (ret) {
-+		dev_err(hdptx->dev, "Failed to get PHY ready: %d\n", ret);
-+		return ret;
-+	}
-+
-+	dev_dbg(hdptx->dev, "PHY ready\n");
-+
-+	return 0;
-+}
-+
- static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
- {
- 	u32 val;
-@@ -680,6 +858,99 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
- 	regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
- }
- 
-+static void rk_hdptx_earc_config(struct rk_hdptx_phy *hdptx)
-+{
-+	regmap_update_bits(hdptx->regmap, SB_REG(0113), SB_RX_RCAL_OPT_CODE_MASK,
-+			   FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 1));
-+	regmap_write(hdptx->regmap, SB_REG(011c), 0x04);
-+	regmap_update_bits(hdptx->regmap, SB_REG(011b), SB_AFC_TOL_MASK,
-+			   FIELD_PREP(SB_AFC_TOL_MASK, 3));
-+	regmap_write(hdptx->regmap, SB_REG(0109), 0x05);
-+
-+	regmap_update_bits(hdptx->regmap, SB_REG(0120),
-+			   SB_EARC_EN_MASK | SB_EARC_AFC_EN_MASK,
-+			   FIELD_PREP(SB_EARC_EN_MASK, 1) |
-+			   FIELD_PREP(SB_EARC_AFC_EN_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(011b), SB_EARC_SIG_DET_BYPASS_MASK,
-+			   FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(011f),
-+			   SB_PWM_AFC_CTRL_MASK | SB_RCAL_RSTN_MASK,
-+			   FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0xc) |
-+			   FIELD_PREP(SB_RCAL_RSTN_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0115), SB_READY_DELAY_TIME_MASK,
-+			   FIELD_PREP(SB_READY_DELAY_TIME_MASK, 2));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0113), SB_RX_RTERM_CTRL_MASK,
-+			   FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 3));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK,
-+			   FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 3));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK,
-+			   FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 3));
-+
-+	regmap_write(hdptx->regmap, SB_REG(011a), 0x03);
-+	regmap_write(hdptx->regmap, SB_REG(0118), 0x0a);
-+	regmap_write(hdptx->regmap, SB_REG(011e), 0x6a);
-+	regmap_write(hdptx->regmap, SB_REG(011d), 0x67);
-+
-+	regmap_update_bits(hdptx->regmap, SB_REG(0117), FAST_PULSE_TIME_MASK,
-+			   FIELD_PREP(FAST_PULSE_TIME_MASK, 4));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0114),
-+			   SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK,
-+			   FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 2) |
-+			   FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 2));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK,
-+			   FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 7));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK,
-+			   FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 7));
-+	regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK,
-+			   FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0110), ANA_SB_VREG_REF_SEL_MASK,
-+			   FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0115), SB_TG_OSC_EN_DELAY_TIME_MASK,
-+			   FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 2));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0116), AFC_RSTN_DELAY_TIME_MASK,
-+			   FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 2));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0109), ANA_SB_DMRX_AFC_DIV_RATIO_MASK,
-+			   FIELD_PREP(ANA_SB_DMRX_AFC_DIV_RATIO_MASK, 5));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK,
-+			   FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK,
-+			   FIELD_PREP(OVRD_SB_EN_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK,
-+			   FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0105), OVRD_SB_EARC_CMDC_EN_MASK,
-+			   FIELD_PREP(OVRD_SB_EARC_CMDC_EN_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(010f),
-+			   OVRD_SB_VREG_EN_MASK | OVRD_SB_VREG_LPF_BYPASS_MASK,
-+			   FIELD_PREP(OVRD_SB_VREG_EN_MASK, 1) |
-+			   FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(0123), OVRD_SB_READY_MASK,
-+			   FIELD_PREP(OVRD_SB_READY_MASK, 1));
-+
-+	usleep_range(1000, 1100);
-+	regmap_update_bits(hdptx->regmap, SB_REG(0103), SB_RX_RESCAL_DONE_MASK,
-+			   FIELD_PREP(SB_RX_RESCAL_DONE_MASK, 1));
-+	usleep_range(50, 60);
-+	regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK,
-+			   FIELD_PREP(SB_EN_MASK, 1));
-+	usleep_range(50, 60);
-+	regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK,
-+			   FIELD_PREP(SB_RXTERM_EN_MASK, 1));
-+	usleep_range(50, 60);
-+	regmap_update_bits(hdptx->regmap, SB_REG(0105), SB_EARC_CMDC_EN_MASK,
-+			   FIELD_PREP(SB_EARC_CMDC_EN_MASK, 1));
-+	regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK,
-+			   FIELD_PREP(SB_VREG_EN_MASK, 1));
-+	usleep_range(50, 60);
-+	regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_LPF_BYPASS_MASK,
-+			   FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 1));
-+	usleep_range(250, 300);
-+	regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_LPF_BYPASS_MASK,
-+			   FIELD_PREP(OVRD_SB_VREG_LPF_BYPASS_MASK, 0));
-+	usleep_range(100, 120);
-+	regmap_update_bits(hdptx->regmap, SB_REG(0123), SB_READY_MASK,
-+			   FIELD_PREP(SB_READY_MASK, 1));
-+}
-+
- static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
- 				      struct ropll_config *cfg)
- {
-@@ -755,9 +1026,13 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
- static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
- 					  unsigned int rate)
- {
-+	int i, bus_width = phy_get_bus_width(hdptx->phy);
-+	u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0;
- 	const struct ropll_config *cfg = NULL;
- 	struct ropll_config rc = {0};
-	int i;
-+
-+	if (color_depth)
-+		rate = rate * 10 / 8;
- 
- 	for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
- 		if (rate == ropll_tmds_cfg[i].bit_rate) {
-@@ -813,6 +1088,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
- 	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
- 			   FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
- 
-+	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK,
-+			   FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth));
-+
- 	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,
- 			   PLL_PCG_CLK_EN);
- 
-@@ -853,9 +1131,146 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
- 	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
- 	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
- 
-+	if (hdptx->earc_en)
-+		rk_hdptx_earc_config(hdptx);
-+
- 	return rk_hdptx_post_enable_lane(hdptx);
- }
- 
-+static int rk_hdptx_ropll_frl_mode_config(struct rk_hdptx_phy *hdptx,
-+					  u32 bus_width)
-+{
-+	u32 bit_rate = bus_width & DATA_RATE_MASK;
-+	u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0;
-+	const struct ropll_config *cfg = NULL;
-+	int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(ropll_frl_cfg); i++)
-+		if (bit_rate == ropll_frl_cfg[i].bit_rate) {
-+			cfg = &ropll_frl_cfg[i];
-+			break;
-+		}
-+
-+	if (!cfg) {
-+		dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	rk_hdptx_pre_power_up(hdptx);
-+
-+	reset_control_assert(hdptx->rsts[RST_ROPLL].rstc);
-+	usleep_range(10, 20);
-+	reset_control_deassert(hdptx->rsts[RST_ROPLL].rstc);
-+
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_cmn_init_seq);
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_ropll_cmn_init_seq);
-+
-+	regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
-+	regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
-+	regmap_write(hdptx->regmap, CMN_REG(0059),
-+		     (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
-+	regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4);
-+
-+	regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
-+			   FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en));
-+	if (!cfg->sdm_en)
-+		regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0);
-+
-+	regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK,
-+			   FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign));
-+
-+	regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno);
-+	regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num);
-+
-+	regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
-+			   FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n));
-+
-+	regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num);
-+	regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno);
-+
-+	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
-+			   FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
-+	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK,
-+			   FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth));
-+
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lntop_init_seq);
-+
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_ropll_lane_init_seq);
-+
-+	if (hdptx->earc_en)
-+		rk_hdptx_earc_config(hdptx);
-+
-+	return rk_hdptx_post_power_up(hdptx);
-+}
-+
-+static int rk_hdptx_lcpll_frl_mode_config(struct rk_hdptx_phy *hdptx,
-+					  u32 bus_width)
-+{
-+	u32 bit_rate = bus_width & DATA_RATE_MASK;
-+	u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0;
-+	const struct lcpll_config *cfg = NULL;
-+	int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(lcpll_cfg); i++)
-+		if (bit_rate == lcpll_cfg[i].bit_rate) {
-+			cfg = &lcpll_cfg[i];
-+			break;
-+		}
-+
-+	if (!cfg) {
-+		dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	rk_hdptx_pre_power_up(hdptx);
-+
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_cmn_init_seq);
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lcpll_cmn_init_seq);
-+
-+	regmap_update_bits(hdptx->regmap, CMN_REG(0008),
-+			   LCPLL_EN_MASK | LCPLL_LCVCO_MODE_EN_MASK,
-+			   FIELD_PREP(LCPLL_EN_MASK, 1) |
-+			   FIELD_PREP(LCPLL_LCVCO_MODE_EN_MASK, cfg->lcvco_mode_en));
-+
-+	regmap_update_bits(hdptx->regmap, CMN_REG(001e),
-+			   LCPLL_PI_EN_MASK | LCPLL_100M_CLK_EN_MASK,
-+			   FIELD_PREP(LCPLL_PI_EN_MASK, cfg->pi_en) |
-+			   FIELD_PREP(LCPLL_100M_CLK_EN_MASK, cfg->clk_en_100m));
-+
-+	regmap_write(hdptx->regmap, CMN_REG(0020), cfg->pms_mdiv);
-+	regmap_write(hdptx->regmap, CMN_REG(0021), cfg->pms_mdiv_afc);
-+	regmap_write(hdptx->regmap, CMN_REG(0022),
-+		     (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
-+	regmap_write(hdptx->regmap, CMN_REG(0023),
-+		     (cfg->pms_sdiv << 4) | cfg->pms_sdiv);
-+	regmap_write(hdptx->regmap, CMN_REG(002a), cfg->sdm_deno);
-+	regmap_write(hdptx->regmap, CMN_REG(002b), cfg->sdm_num_sign);
-+	regmap_write(hdptx->regmap, CMN_REG(002c), cfg->sdm_num);
-+
-+	regmap_update_bits(hdptx->regmap, CMN_REG(002d), LCPLL_SDC_N_MASK,
-+			   FIELD_PREP(LCPLL_SDC_N_MASK, cfg->sdc_n));
-+
-+	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
-+			   FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
-+	regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK,
-+			   FIELD_PREP(PLL_PCG_CLK_SEL_MASK, color_depth));
-+
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lntop_init_seq);
-+
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
-+	rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_frl_lcpll_lane_init_seq);
-+
-+	if (hdptx->earc_en)
-+		rk_hdptx_earc_config(hdptx);
-+
-+	return rk_hdptx_post_power_up(hdptx);
-+}
-+
- static int rk_hdptx_phy_power_on(struct phy *phy)
- {
- 	struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
-@@ -865,7 +1280,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
- 	 * from the HDMI bridge driver until phy_configure_opts_hdmi
- 	 * becomes available in the PHY API.
- 	 */
-	unsigned int rate = bus_width & 0xfffffff;
-+	unsigned int rate = bus_width & DATA_RATE_MASK;
- 
- 	dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
- 		__func__, bus_width, rate);
-@@ -876,7 +1291,20 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
- 		return ret;
- 	}
- 
-	ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
-+	if (bus_width & HDMI_EARC_MASK)
-+		hdptx->earc_en = true;
-+	else
-+		hdptx->earc_en = false;
-+
-+	if (bus_width & HDMI_MODE_MASK) {
-+		if (rate > 24000000)
-+			ret = rk_hdptx_lcpll_frl_mode_config(hdptx, bus_width);
-+		else
-+			ret = rk_hdptx_ropll_frl_mode_config(hdptx, bus_width);
-+	} else {
-+		ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
-+	}
-+
- 	if (ret)
- 		pm_runtime_put(hdptx->dev);
- 
-- 
-Armbian
-
--- a/kernel.patches/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch
+++ b/kernel.patches/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch
@@ -1,222 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
-Date: Tue, 16 Jan 2024 19:27:40 +0200
-Subject: phy: phy-rockchip-samsung-hdptx: Add clock provider
-
-The HDMI PHY PLL can be used as an alternative dclk source to SoC CRU.
-It provides more accurate clock rates required to properly support
-various display modes, e.g. those relying on non-integer refresh rates.
-
-Also note this only works for HDMI 2.0 or bellow, e.g. cannot be used to
-support HDMI 2.1 4K@120Hz mode.
-
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 148 +++++++++-
- 1 file changed, 143 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
-index 111111111111..222222222222 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
-+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
-@@ -8,6 +8,7 @@
-  */
- #include <linux/bitfield.h>
- #include <linux/clk.h>
-+#include <linux/clk-provider.h>
- #include <linux/delay.h>
- #include <linux/mfd/syscon.h>
- #include <linux/module.h>
-@@ -279,6 +280,12 @@ struct rk_hdptx_phy {
- 	int nr_clks;
- 	struct reset_control_bulk_data rsts[RST_MAX];
- 	bool earc_en;
-+
-+	/* clk provider */
-+	struct clk_hw hw;
-+	unsigned long rate;
-+	int id;
-+	int count;
- };
- 
- static const struct lcpll_config lcpll_cfg[] = {
-@@ -1031,6 +1038,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
- 	const struct ropll_config *cfg = NULL;
- 	struct ropll_config rc = {0};
- 
-+	hdptx->rate = rate * 100;
-+
- 	if (color_depth)
- 		rate = rate * 10 / 8;
- 
-@@ -1315,11 +1324,13 @@ static int rk_hdptx_phy_power_off(struct phy *phy)
- {
- 	struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
- 	u32 val;
-	int ret;
-+	int ret = 0;
- 
-	ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
-	if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
-		rk_hdptx_phy_disable(hdptx);
-+	if (hdptx->count == 0) {
-+		ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
-+		if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
-+			rk_hdptx_phy_disable(hdptx);
-+	}
- 
- 	pm_runtime_put(hdptx->dev);
- 
-@@ -1332,6 +1343,129 @@ static const struct phy_ops rk_hdptx_phy_ops = {
- 	.owner	   = THIS_MODULE,
- };
- 
-+static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
-+{
-+	return container_of(hw, struct rk_hdptx_phy, hw);
-+}
-+
-+static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
-+{
-+	struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
-+	int ret;
-+
-+	ret = pm_runtime_resume_and_get(hdptx->dev);
-+	if (ret) {
-+		dev_err(hdptx->dev, "Failed to resume phy clk: %d\n", ret);
-+		return ret;
-+	}
-+
-+	if (!hdptx->count && hdptx->rate) {
-+		ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, hdptx->rate / 100);
-+		if (ret < 0) {
-+			dev_err(hdptx->dev, "Failed to init PHY PLL: %d\n", ret);
-+			pm_runtime_put(hdptx->dev);
-+			return ret;
-+		}
-+	}
-+
-+	hdptx->count++;
-+
-+	return 0;
-+}
-+
-+static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
-+{
-+	struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
-+
-+	if (hdptx->count == 1) {
-+		u32 val;
-+		int ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
-+		if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
-+			rk_hdptx_phy_disable(hdptx);
-+	}
-+
-+	hdptx->count--;
-+	pm_runtime_put(hdptx->dev);
-+}
-+
-+static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
-+						  unsigned long parent_rate)
-+{
-+	struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
-+
-+	return hdptx->rate;
-+}
-+
-+static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-+					unsigned long *parent_rate)
-+{
-+	const struct ropll_config *cfg = NULL;
-+	u32 bit_rate = rate / 100;
-+	int i;
-+
-+	if (rate > HDMI20_MAX_RATE)
-+		return rate;
-+
-+	for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
-+		if (bit_rate == ropll_tmds_cfg[i].bit_rate) {
-+			cfg = &ropll_tmds_cfg[i];
-+			break;
-+		}
-+
-+	if (!cfg && !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
-+		return -EINVAL;
-+
-+	return rate;
-+}
-+
-+static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-+				     unsigned long parent_rate)
-+{
-+	struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
-+	u32 val;
-+	int ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
-+	if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
-+		rk_hdptx_phy_disable(hdptx);
-+
-+	return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
-+}
-+
-+static const struct clk_ops hdptx_phy_clk_ops = {
-+	.prepare = rk_hdptx_phy_clk_prepare,
-+	.unprepare = rk_hdptx_phy_clk_unprepare,
-+	.recalc_rate = rk_hdptx_phy_clk_recalc_rate,
-+	.round_rate = rk_hdptx_phy_clk_round_rate,
-+	.set_rate = rk_hdptx_phy_clk_set_rate,
-+};
-+
-+static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
-+{
-+	struct device *dev = hdptx->dev;
-+	const char *name, *pname;
-+	struct clk *refclk;
-+	int ret;
-+
-+	refclk = devm_clk_get(dev, "ref");
-+	if (IS_ERR(refclk))
-+		return dev_err_probe(dev, PTR_ERR(refclk),
-+				     "Failed to get ref clock\n");
-+
-+	pname = __clk_get_name(refclk);
-+	name = hdptx->id ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
-+	hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
-+				     CLK_GET_RATE_NOCACHE);
-+
-+	ret = devm_clk_hw_register(dev, &hdptx->hw);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to register clock\n");
-+
-+	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
-+	if (ret)
-+		return dev_err_probe(dev, ret,
-+				     "Failed to register clk provider\n");
-+	return 0;
-+}
-+
- static int rk_hdptx_phy_runtime_suspend(struct device *dev)
- {
- 	struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
-@@ -1367,6 +1501,10 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
- 
- 	hdptx->dev = dev;
- 
-+	hdptx->id = of_alias_get_id(dev->of_node, "hdptxphy");
-+	if (hdptx->id < 0)
-+		hdptx->id = 0;
-+
- 	regs = devm_platform_ioremap_resource(pdev, 0);
- 	if (IS_ERR(regs))
- 		return dev_err_probe(dev, PTR_ERR(regs),
-@@ -1426,7 +1564,7 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
- 	reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
- 	reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
- 
-	return 0;
-+	return rk_hdptx_phy_clk_register(hdptx);
- }
- 
- static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
-- 
-Armbian
-
--- a/kernel.patches/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch
+++ b/kernel.patches/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch
@@ -1,679 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
-Date: Fri, 3 Nov 2023 19:58:02 +0200
-Subject: drm/rockchip: vop2: Improve display modes handling on rk3588
-
-The initial vop2 support for rk3588 in mainline is not able to handle
-all display modes supported by connected displays, e.g.
-2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz.
-
-Additionally, it doesn't cope with non-integer refresh rates like 59.94,
-29.97, 23.98, etc.
-
-Improve HDMI0 clocking in order to support the additional display modes.
-
-Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 553 +++++++++-
- 1 file changed, 552 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-@@ -5,6 +5,8 @@
-  */
- #include <linux/bitfield.h>
- #include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/clkdev.h>
- #include <linux/component.h>
- #include <linux/delay.h>
- #include <linux/iopoll.h>
-@@ -212,6 +214,10 @@ struct vop2 {
- 	struct clk *hclk;
- 	struct clk *aclk;
- 	struct clk *pclk;
-+	// [CC:] hack to support additional display modes
-+	struct clk *hdmi0_phy_pll;
-+	/* list_head of internal clk */
-+	struct list_head clk_list_head;
- 
- 	/* optional internal rgb encoder */
- 	struct rockchip_rgb *rgb;
-@@ -220,6 +226,19 @@ struct vop2 {
- 	struct vop2_win win[];
- };
- 
-+struct vop2_clk {
-+	struct vop2 *vop2;
-+	struct list_head list;
-+	unsigned long rate;
-+	struct clk_hw hw;
-+	struct clk_divider div;
-+	int div_val;
-+	u8 parent_index;
-+};
-+
-+#define to_vop2_clk(_hw) container_of(_hw, struct vop2_clk, hw)
-+#define VOP2_MAX_DCLK_RATE	600000 /* kHz */
-+
- #define vop2_output_if_is_hdmi(x)	((x) == ROCKCHIP_VOP2_EP_HDMI0 || \
- 					 (x) == ROCKCHIP_VOP2_EP_HDMI1)
- 
-@@ -1476,9 +1495,30 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
- 				 const struct drm_display_mode *mode,
- 				 struct drm_display_mode *adj_mode)
- {
-+	struct vop2_video_port *vp = to_vop2_video_port(crtc);
-+	struct drm_connector *connector;
-+	struct drm_connector_list_iter conn_iter;
-+	struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
- 	drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V |
- 					CRTC_STEREO_DOUBLE);
- 
-+	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
-+		adj_mode->crtc_clock *= 2;
-+
-+	drm_connector_list_iter_begin(crtc->dev, &conn_iter);
-+	drm_for_each_connector_iter(connector, &conn_iter) {
-+		if ((new_crtc_state->connector_mask & drm_connector_mask(connector)) &&
-+		    ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
-+		     (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))) {
-+			drm_connector_list_iter_end(&conn_iter);
-+			return true;
-+		}
-+	}
-+	drm_connector_list_iter_end(&conn_iter);
-+
-+	if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE)
-+		adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
-+						    adj_mode->crtc_clock * 1000), 1000);
- 	return true;
- }
- 
-@@ -1663,6 +1703,31 @@ static unsigned long rk3588_calc_dclk(unsigned long child_clk, unsigned long max
- 		return 0;
- }
- 
-+static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name);
-+
-+static int vop2_cru_set_rate(struct vop2_clk *if_pixclk, struct vop2_clk *if_dclk)
-+{
-+	int ret = 0;
-+
-+	if (if_pixclk) {
-+		ret =  clk_set_rate(if_pixclk->hw.clk, if_pixclk->rate);
-+		if (ret < 0) {
-+			DRM_DEV_ERROR(if_pixclk->vop2->dev, "set %s to %ld failed: %d\n",
-+				      clk_hw_get_name(&if_pixclk->hw), if_pixclk->rate, ret);
-+			return ret;
-+		}
-+	}
-+
-+	if (if_dclk) {
-+		ret = clk_set_rate(if_dclk->hw.clk, if_dclk->rate);
-+		if (ret < 0)
-+			DRM_DEV_ERROR(if_dclk->vop2->dev, "set %s to %ld failed %d\n",
-+				      clk_hw_get_name(&if_dclk->hw), if_dclk->rate, ret);
-+	}
-+
-+	return ret;
-+}
-+
- /*
-  * 4 pixclk/cycle on rk3588
-  * RGB/eDP/HDMI: if_pixclk >= dclk_core
-@@ -1686,6 +1751,72 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
- 	int K = 1;
- 
- 	if (vop2_output_if_is_hdmi(id)) {
-+		if (vop2->data->soc_id == 3588 && id == ROCKCHIP_VOP2_EP_HDMI0 &&
-+		    vop2->hdmi0_phy_pll) {
-+			const char *clk_src_name = "hdmi_edp0_clk_src";
-+			const char *clk_parent_name = "dclk";
-+			const char *pixclk_name = "hdmi_edp0_pixclk";
-+			const char *dclk_name = "hdmi_edp0_dclk";
-+			struct vop2_clk *if_clk_src, *if_clk_parent, *if_pixclk, *if_dclk, *dclk, *dclk_core, *dclk_out;
-+			char clk_name[32];
-+			int ret;
-+
-+			if_clk_src = vop2_clk_get(vop2, clk_src_name);
-+			snprintf(clk_name, sizeof(clk_name), "%s%d", clk_parent_name, vp->id);
-+			if_clk_parent = vop2_clk_get(vop2, clk_name);
-+			if_pixclk = vop2_clk_get(vop2, pixclk_name);
-+			if_dclk = vop2_clk_get(vop2, dclk_name);
-+			if (!if_pixclk || !if_clk_parent) {
-+				DRM_DEV_ERROR(vop2->dev, "failed to get connector interface clk\n");
-+				return -ENODEV;
-+			}
-+
-+			ret = clk_set_parent(if_clk_src->hw.clk, if_clk_parent->hw.clk);
-+			if (ret < 0) {
-+				DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
-+					      __clk_get_name(if_clk_parent->hw.clk),
-+					      __clk_get_name(if_clk_src->hw.clk), ret);
-+				return ret;
-+			}
-+
-+			if (output_mode == ROCKCHIP_OUT_MODE_YUV420)
-+				K = 2;
-+
-+			if_pixclk->rate = (dclk_core_rate << 1) / K;
-+			if_dclk->rate = dclk_core_rate / K;
-+
-+			snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
-+			dclk_core = vop2_clk_get(vop2, clk_name);
-+
-+			snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
-+			dclk_out = vop2_clk_get(vop2, clk_name);
-+
-+			snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
-+			dclk = vop2_clk_get(vop2, clk_name);
-+			if (v_pixclk <= (VOP2_MAX_DCLK_RATE * 1000)) {
-+				if (output_mode == ROCKCHIP_OUT_MODE_YUV420)
-+					v_pixclk = v_pixclk >> 1;
-+			} else {
-+				v_pixclk = v_pixclk >> 2;
-+			}
-+			clk_set_rate(dclk->hw.clk, v_pixclk);
-+
-+			if (dclk_core_rate > if_pixclk->rate) {
-+				clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
-+				ret = vop2_cru_set_rate(if_pixclk, if_dclk);
-+			} else {
-+				ret = vop2_cru_set_rate(if_pixclk, if_dclk);
-+				clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
-+			}
-+
-+			*dclk_core_div = dclk_core->div_val;
-+			*dclk_out_div = dclk_out->div_val;
-+			*if_pixclk_div = if_pixclk->div_val;
-+			*if_dclk_div = if_dclk->div_val;
-+
-+			return dclk->rate;
-+		}
-+
- 		/*
- 		 * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate
- 		 * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate
-@@ -1917,6 +2048,22 @@ static int us_to_vertical_line(struct drm_display_mode *mode, int us)
- 	return us * mode->clock / mode->htotal / 1000;
- }
- 
-+// [CC:] rework virtual clock
-+static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name)
-+{
-+	struct vop2_clk *clk, *n;
-+
-+	if (!name)
-+		return NULL;
-+
-+	list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) {
-+		if (!strcmp(clk_hw_get_name(&clk->hw), name))
-+			return clk;
-+	}
-+
-+	return NULL;
-+}
-+
- static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
- 				    struct drm_atomic_state *state)
- {
-@@ -1944,6 +2091,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
- 	u32 val, polflags;
- 	int ret;
- 	struct drm_encoder *encoder;
-+	char clk_name[32];
-+	struct vop2_clk *dclk;
- 
- 	drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
- 		hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
-@@ -2044,11 +2193,38 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
- 
- 	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
- 		dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
-		clock *= 2;
-+		// [CC:] done via mode_fixup
-+		// clock *= 2;
- 	}
- 
- 	vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
- 
-+	snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
-+	dclk = vop2_clk_get(vop2, clk_name);
-+	if (dclk) {
-+		/*
-+		 * use HDMI_PHY_PLL as dclk source under 4K@60 if it is available,
-+		 * otherwise use system cru as dclk source.
-+		 */
-+		drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
-+			struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
-+
-+			// [CC:] Using PHY PLL to handle all display modes
-+			if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) {
-+				clk_get_rate(vop2->hdmi0_phy_pll);
-+
-+				if (mode->crtc_clock <= VOP2_MAX_DCLK_RATE) {
-+					ret = clk_set_parent(vp->dclk, vop2->hdmi0_phy_pll);
-+					if (ret < 0)
-+						DRM_WARN("failed to set clock parent for %s\n",
-+							 __clk_get_name(vp->dclk));
-+				}
-+
-+				clock = dclk->rate;
-+			}
-+		}
-+	}
-+
- 	clk_set_rate(vp->dclk, clock);
- 
- 	vop2_post_config(crtc);
-@@ -2504,7 +2680,43 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc,
- 	spin_unlock_irq(&crtc->dev->event_lock);
- }
- 
-+static enum drm_mode_status
-+vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
-+{
-+	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
-+	struct vop2_video_port *vp = to_vop2_video_port(crtc);
-+	struct vop2 *vop2 = vp->vop2;
-+	const struct vop2_data *vop2_data = vop2->data;
-+	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
-+	int request_clock = mode->clock;
-+	int clock;
-+
-+	if (mode->hdisplay > vp_data->max_output.width)
-+		return MODE_BAD_HVALUE;
-+
-+	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
-+		request_clock *= 2;
-+
-+	if (request_clock <= VOP2_MAX_DCLK_RATE) {
-+		clock = request_clock;
-+	} else {
-+		request_clock = request_clock >> 2;
-+		clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000;
-+	}
-+
-+	/*
-+	 * Hdmi or DisplayPort request a Accurate clock.
-+	 */
-+	if (vcstate->output_type == DRM_MODE_CONNECTOR_HDMIA ||
-+	    vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort)
-+		if (clock != request_clock)
-+			return MODE_CLOCK_RANGE;
-+
-+	return MODE_OK;
-+}
-+
- static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
-+	.mode_valid = vop2_crtc_mode_valid,
- 	.mode_fixup = vop2_crtc_mode_fixup,
- 	.atomic_check = vop2_crtc_atomic_check,
- 	.atomic_begin = vop2_crtc_atomic_begin,
-@@ -3074,6 +3286,336 @@ static const struct regmap_config vop2_regmap_config = {
- 	.cache_type	= REGCACHE_MAPLE,
- };
- 
-+/*
-+ * BEGIN virtual clock
-+ */
-+#define PLL_RATE_MIN	30000000
-+
-+#define cru_dbg(format, ...) do {				\
-+		if (cru_debug)					\
-+			pr_info("%s: " format, __func__, ## __VA_ARGS__); \
-+	} while (0)
-+
-+#define PNAME(x) static const char *const x[]
-+
-+enum vop_clk_branch_type {
-+	branch_mux,
-+	branch_divider,
-+	branch_factor,
-+	branch_virtual,
-+};
-+
-+#define VIR(cname)						\
-+	{							\
-+		.branch_type	= branch_virtual,		\
-+		.name		= cname,			\
-+	}
-+
-+
-+#define MUX(cname, pnames, f)			\
-+	{							\
-+		.branch_type	= branch_mux,			\
-+		.name		= cname,			\
-+		.parent_names	= pnames,			\
-+		.num_parents	= ARRAY_SIZE(pnames),		\
-+		.flags		= f,				\
-+	}
-+
-+#define FACTOR(cname, pname,  f)			\
-+	{							\
-+		.branch_type	= branch_factor,		\
-+		.name		= cname,			\
-+		.parent_names	= (const char *[]){ pname },	\
-+		.num_parents	= 1,				\
-+		.flags		= f,				\
-+	}
-+
-+#define DIV(cname, pname, f, w)			\
-+	{							\
-+		.branch_type	= branch_divider,		\
-+		.name		= cname,			\
-+		.parent_names	= (const char *[]){ pname },	\
-+		.num_parents	= 1,				\
-+		.flags		= f,				\
-+		.div_width	= w,				\
-+	}
-+
-+struct vop2_clk_branch {
-+	enum vop_clk_branch_type	branch_type;
-+	const char			*name;
-+	const char			*const *parent_names;
-+	u8				num_parents;
-+	unsigned long			flags;
-+	u8				div_shift;
-+	u8				div_width;
-+	u8				div_flags;
-+};
-+
-+PNAME(mux_port0_dclk_src_p)		= { "dclk0", "dclk1" };
-+PNAME(mux_port2_dclk_src_p)		= { "dclk2", "dclk1" };
-+PNAME(mux_dp_pixclk_p)			= { "dclk_out0", "dclk_out1", "dclk_out2" };
-+PNAME(mux_hdmi_edp_clk_src_p)		= { "dclk0", "dclk1", "dclk2" };
-+PNAME(mux_mipi_clk_src_p)		= { "dclk_out1", "dclk_out2", "dclk_out3" };
-+PNAME(mux_dsc_8k_clk_src_p)		= { "dclk0", "dclk1", "dclk2", "dclk3" };
-+PNAME(mux_dsc_4k_clk_src_p)		= { "dclk0", "dclk1", "dclk2", "dclk3" };
-+
-+/*
-+ * We only use this clk driver calculate the div
-+ * of dclk_core/dclk_out/if_pixclk/if_dclk and
-+ * the rate of the dclk from the soc.
-+ *
-+ * We don't touch the cru in the vop here, as
-+ * these registers has special read andy write
-+ * limits.
-+ */
-+static struct vop2_clk_branch rk3588_vop_clk_branches[] = {
-+	VIR("dclk0"),
-+	VIR("dclk1"),
-+	VIR("dclk2"),
-+	VIR("dclk3"),
-+
-+	MUX("port0_dclk_src", mux_port0_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+	DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
-+	DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
-+
-+	FACTOR("port1_dclk_src", "dclk1", CLK_SET_RATE_PARENT),
-+	DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
-+	DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
-+
-+	MUX("port2_dclk_src", mux_port2_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+	DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
-+	DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
-+
-+	FACTOR("port3_dclk_src", "dclk3", CLK_SET_RATE_PARENT),
-+	DIV("dclk_core3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
-+	DIV("dclk_out3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
-+
-+	MUX("dp0_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+	MUX("dp1_pixclk", mux_dp_pixclk_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+
-+	MUX("hdmi_edp0_clk_src", mux_hdmi_edp_clk_src_p,
-+	    CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+	DIV("hdmi_edp0_dclk", "hdmi_edp0_clk_src", 0, 2),
-+	DIV("hdmi_edp0_pixclk", "hdmi_edp0_clk_src", CLK_SET_RATE_PARENT, 1),
-+
-+	MUX("hdmi_edp1_clk_src", mux_hdmi_edp_clk_src_p,
-+	    CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+	DIV("hdmi_edp1_dclk", "hdmi_edp1_clk_src", 0, 2),
-+	DIV("hdmi_edp1_pixclk", "hdmi_edp1_clk_src", CLK_SET_RATE_PARENT, 1),
-+
-+	MUX("mipi0_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+	DIV("mipi0_pixclk", "mipi0_clk_src", CLK_SET_RATE_PARENT, 2),
-+
-+	MUX("mipi1_clk_src", mux_mipi_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+	DIV("mipi1_pixclk", "mipi1_clk_src", CLK_SET_RATE_PARENT, 2),
-+
-+	FACTOR("rgb_pixclk", "port3_dclk_src", CLK_SET_RATE_PARENT),
-+
-+	MUX("dsc_8k_txp_clk_src", mux_dsc_8k_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+	DIV("dsc_8k_txp_clk", "dsc_8k_txp_clk_src", 0, 2),
-+	DIV("dsc_8k_pxl_clk", "dsc_8k_txp_clk_src", 0, 2),
-+	DIV("dsc_8k_cds_clk", "dsc_8k_txp_clk_src", 0, 2),
-+
-+	MUX("dsc_4k_txp_clk_src", mux_dsc_4k_clk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
-+	DIV("dsc_4k_txp_clk", "dsc_4k_txp_clk_src", 0, 2),
-+	DIV("dsc_4k_pxl_clk", "dsc_4k_txp_clk_src", 0, 2),
-+	DIV("dsc_4k_cds_clk", "dsc_4k_txp_clk_src", 0, 2),
-+};
-+
-+static unsigned long clk_virtual_recalc_rate(struct clk_hw *hw,
-+		unsigned long parent_rate)
-+{
-+	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
-+
-+	return (unsigned long)vop2_clk->rate;
-+}
-+
-+static long clk_virtual_round_rate(struct clk_hw *hw, unsigned long rate,
-+				unsigned long *prate)
-+{
-+	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
-+
-+	vop2_clk->rate = rate;
-+
-+	return rate;
-+}
-+
-+static int clk_virtual_set_rate(struct clk_hw *hw, unsigned long rate,
-+				unsigned long parent_rate)
-+{
-+	return 0;
-+}
-+
-+const struct clk_ops clk_virtual_ops = {
-+	.round_rate = clk_virtual_round_rate,
-+	.set_rate = clk_virtual_set_rate,
-+	.recalc_rate = clk_virtual_recalc_rate,
-+};
-+
-+static u8 vop2_mux_get_parent(struct clk_hw *hw)
-+{
-+	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
-+
-+	// cru_dbg("%s index: %d\n", clk_hw_get_name(hw), vop2_clk->parent_index);
-+	return vop2_clk->parent_index;
-+}
-+
-+static int vop2_mux_set_parent(struct clk_hw *hw, u8 index)
-+{
-+	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
-+
-+	vop2_clk->parent_index = index;
-+
-+	// cru_dbg("%s index: %d\n", clk_hw_get_name(hw), index);
-+	return 0;
-+}
-+
-+static int vop2_clk_mux_determine_rate(struct clk_hw *hw,
-+			     struct clk_rate_request *req)
-+{
-+	// cru_dbg("%s  %ld(min: %ld max: %ld)\n",
-+	//        clk_hw_get_name(hw), req->rate, req->min_rate, req->max_rate);
-+	return __clk_mux_determine_rate(hw, req);
-+}
-+
-+static const struct clk_ops vop2_mux_clk_ops = {
-+	.get_parent = vop2_mux_get_parent,
-+	.set_parent = vop2_mux_set_parent,
-+	.determine_rate = vop2_clk_mux_determine_rate,
-+};
-+
-+#define div_mask(width)	((1 << (width)) - 1)
-+
-+static int vop2_div_get_val(unsigned long rate, unsigned long parent_rate)
-+{
-+	unsigned int div, value;
-+
-+	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
-+
-+	value = ilog2(div);
-+
-+	return value;
-+}
-+
-+static unsigned long vop2_clk_div_recalc_rate(struct clk_hw *hw,
-+					  unsigned long parent_rate)
-+{
-+	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
-+	unsigned long rate;
-+	unsigned int div;
-+
-+	div =  1 << vop2_clk->div_val;
-+	rate = parent_rate / div;
-+
-+	// cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, parent_rate);
-+	return rate;
-+}
-+
-+static long vop2_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
-+				unsigned long *prate)
-+{
-+	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
-+
-+	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
-+		if (*prate < rate)
-+			*prate = rate;
-+		if ((*prate >> vop2_clk->div.width) > rate)
-+			*prate = rate;
-+
-+		if ((*prate % rate))
-+			*prate = rate;
-+
-+		/* SOC PLL can't output a too low pll freq */
-+		if (*prate < PLL_RATE_MIN)
-+			*prate = rate << vop2_clk->div.width;
-+	}
-+
-+	// cru_dbg("%s rate: %ld(prate: %ld)\n", clk_hw_get_name(hw), rate, *prate);
-+	return rate;
-+}
-+
-+static int vop2_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
-+{
-+	struct vop2_clk *vop2_clk = to_vop2_clk(hw);
-+	int div_val;
-+
-+	div_val = vop2_div_get_val(rate, parent_rate);
-+	vop2_clk->div_val = div_val;
-+
-+	// cru_dbg("%s prate: %ld rate: %ld div_val: %d\n",
-+	//        clk_hw_get_name(hw), parent_rate, rate, div_val);
-+	return 0;
-+}
-+
-+static const struct clk_ops vop2_div_clk_ops = {
-+	.recalc_rate = vop2_clk_div_recalc_rate,
-+	.round_rate = vop2_clk_div_round_rate,
-+	.set_rate = vop2_clk_div_set_rate,
-+};
-+
-+static struct clk *vop2_clk_register(struct vop2 *vop2, struct vop2_clk_branch *branch)
-+{
-+	struct clk_init_data init = {};
-+	struct vop2_clk *vop2_clk;
-+	struct clk *clk;
-+
-+	vop2_clk = devm_kzalloc(vop2->dev, sizeof(*vop2_clk), GFP_KERNEL);
-+	if (!vop2_clk)
-+		return ERR_PTR(-ENOMEM);
-+
-+	vop2_clk->vop2 = vop2;
-+	vop2_clk->hw.init = &init;
-+	vop2_clk->div.shift = branch->div_shift;
-+	vop2_clk->div.width = branch->div_width;
-+
-+	init.name = branch->name;
-+	init.flags = branch->flags;
-+	init.num_parents = branch->num_parents;
-+	init.parent_names = branch->parent_names;
-+	if (branch->branch_type == branch_divider) {
-+		init.ops = &vop2_div_clk_ops;
-+	} else if (branch->branch_type == branch_virtual) {
-+		init.ops = &clk_virtual_ops;
-+		init.num_parents = 0;
-+		init.parent_names = NULL;
-+	} else {
-+		init.ops = &vop2_mux_clk_ops;
-+	}
-+
-+	clk = devm_clk_register(vop2->dev, &vop2_clk->hw);
-+	if (!IS_ERR(clk))
-+		list_add_tail(&vop2_clk->list, &vop2->clk_list_head);
-+	else
-+		DRM_DEV_ERROR(vop2->dev, "Register %s failed\n", branch->name);
-+
-+	return clk;
-+}
-+
-+static int vop2_clk_init(struct vop2 *vop2)
-+{
-+	struct vop2_clk_branch *branch = rk3588_vop_clk_branches;
-+	unsigned int nr_clk = ARRAY_SIZE(rk3588_vop_clk_branches);
-+	unsigned int idx;
-+	struct vop2_clk *clk, *n;
-+
-+	INIT_LIST_HEAD(&vop2->clk_list_head);
-+
-+	if (vop2->data->soc_id < 3588 || vop2->hdmi0_phy_pll == NULL)
-+		return 0;
-+
-+	list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) {
-+		list_del(&clk->list);
-+	}
-+
-+	for (idx = 0; idx < nr_clk; idx++, branch++)
-+		vop2_clk_register(vop2, branch);
-+
-+	return 0;
-+}
-+/*
-+ * END virtual clock
-+ */
-+
- static int vop2_bind(struct device *dev, struct device *master, void *data)
- {
- 	struct platform_device *pdev = to_platform_device(dev);
-@@ -3167,6 +3709,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
- 		return PTR_ERR(vop2->pclk);
- 	}
- 
-+	vop2->hdmi0_phy_pll = devm_clk_get_optional(vop2->drm->dev, "hdmi0_phy_pll");
-+	if (IS_ERR(vop2->hdmi0_phy_pll)) {
-+		DRM_DEV_ERROR(vop2->dev, "failed to get hdmi0_phy_pll source\n");
-+		return PTR_ERR(vop2->hdmi0_phy_pll);
-+	}
-+
- 	vop2->irq = platform_get_irq(pdev, 0);
- 	if (vop2->irq < 0) {
- 		drm_err(vop2->drm, "cannot find irq for vop2\n");
-@@ -3183,6 +3731,9 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
- 	if (ret)
- 		return ret;
- 
-+	// [CC:] rework virtual clock
-+	vop2_clk_init(vop2);
-+
- 	ret = vop2_find_rgb_encoder(vop2);
- 	if (ret >= 0) {
- 		vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
-- 
-Armbian
-
--- a/kernel.patches/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch
+++ b/kernel.patches/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch
@@ -1,34 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Mon, 13 May 2024 20:29:49 +0300
-Subject: arm64: dts: rockchip: rk3588: add VDPU and RGA2 nodes
-
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 ++++++++++
- 1 file changed, 11 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -726,6 +726,17 @@ mmu600_php: iommu@fcb00000 {
- 		status = "disabled";
- 	};
- 
-+	rga: rga@fdb80000 {
-+		compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
-+		reg = <0x0 0xfdb80000 0x0 0x1000>;
-+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>;
-+		clock-names = "aclk", "hclk", "sclk";
-+		resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>;
-+		reset-names = "core", "axi", "ahb";
-+		power-domains = <&power RK3588_PD_VDPU>;
-+	};
-+
- 	pmu1grf: syscon@fd58a000 {
- 		compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
- 		reg = <0x0 0xfd58a000 0x0 0x10000>;
-- 
-Armbian
-
--- a/kernel.patches/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch
+++ b/kernel.patches/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch
--- a/kernel.patches/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch
+++ b/kernel.patches/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch
@@ -1,25 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: ColorfulRhino <unknown-email@domain.tld>
-Date: Wed, 12 Jun 2024 12:17:18 +0200
-Subject: Fix HDMI controller patch at
- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
-
---
- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
-index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
-+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
-@@ -5,6 +5,7 @@
-  *      Algea Cao <algea.cao@rock-chips.com>
-  */
- #include <linux/clk.h>
-+#include <linux/debugfs.h>
- #include <linux/delay.h>
- #include <linux/dma-mapping.h>
- #include <linux/err.h>
-- 
-Armbian
-
--- a/kernel.patches/0170-drm-rockchip-vop2-add-clocks-reset-support.patch
+++ b/kernel.patches/0170-drm-rockchip-vop2-add-clocks-reset-support.patch
@@ -1,190 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Detlev Casanova <detlev.casanova@collabora.com>
-Date: Fri, 3 May 2024 14:27:39 -0400
-Subject: vop2: Add clock resets support
-
-At the end of initialization, each VP clock needs to be reset before
-they can be used.
-
-Failing to do so can put the VOP in an undefined state where the
-generated HDMI signal is either lost or not matching the selected mode.
-
-Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 30 ++++++++++
- 1 file changed, 30 insertions(+)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-@@ -19,6 +19,7 @@
- #include <linux/platform_device.h>
- #include <linux/pm_runtime.h>
- #include <linux/regmap.h>
-+#include <linux/reset.h>
- #include <linux/swab.h>
- 
- #include <drm/drm.h>
-@@ -159,6 +160,7 @@ struct vop2_win {
- struct vop2_video_port {
- 	struct drm_crtc crtc;
- 	struct vop2 *vop2;
-+	struct reset_control *dclk_rst;
- 	struct clk *dclk;
- 	unsigned int id;
- 	const struct vop2_video_port_data *data;
-@@ -2064,6 +2066,26 @@ static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name)
- 	return NULL;
- }
- 
-+static int vop2_clk_reset(struct vop2_video_port *vp)
-+{
-+	struct reset_control *rstc = vp->dclk_rst;
-+	struct vop2 *vop2 = vp->vop2;
-+	int ret;
-+
-+	if (!rstc)
-+		return 0;
-+
-+	ret = reset_control_assert(rstc);
-+	if (ret < 0)
-+		drm_warn(vop2->drm, "failed to assert reset\n");
-+	udelay(10);
-+	ret = reset_control_deassert(rstc);
-+	if (ret < 0)
-+		drm_warn(vop2->drm, "failed to deassert reset\n");
-+
-+	return ret;
-+}
-+
- static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
- 				    struct drm_atomic_state *state)
- {
-@@ -2233,6 +2255,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
- 
- 	vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
- 
-+	vop2_clk_reset(vp);
-+
- 	drm_crtc_vblank_on(crtc);
- 
- 	vop2_unlock(vop2);
-@@ -2920,6 +2944,12 @@ static int vop2_create_crtcs(struct vop2 *vop2)
- 		vp->data = vp_data;
- 
- 		snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
-+		vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, dclk_name);
-+		if (IS_ERR(vp->dclk_rst)) {
-+		        drm_err(vop2->drm, "failed to get %s reset\n", dclk_name);
-+		        return PTR_ERR(vp->dclk_rst);
-+		}
-+
- 		vp->dclk = devm_clk_get(vop2->dev, dclk_name);
- 		if (IS_ERR(vp->dclk)) {
- 			drm_err(vop2->drm, "failed to get %s\n", dclk_name);
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Detlev Casanova <detlev.casanova@collabora.com>
-Date: Fri, 3 May 2024 14:28:12 -0400
-Subject: arm64: dts: rockchip: Add VOP clock resets for rk3588s
-
-This adds the needed clock resets for all rk3588(s) based SOCs.
-
-Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1429,6 +1429,14 @@ vop: vop@fdd90000 {
- 			      "pclk_vop";
- 		iommus = <&vop_mmu>;
- 		power-domains = <&power RK3588_PD_VOP>;
-+		resets = <&cru SRST_D_VOP0>,
-+			 <&cru SRST_D_VOP1>,
-+			 <&cru SRST_D_VOP2>,
-+			 <&cru SRST_D_VOP3>;
-+		reset-names = "dclk_vp0",
-+			      "dclk_vp1",
-+			      "dclk_vp2",
-+			      "dclk_vp3";
- 		rockchip,grf = <&sys_grf>;
- 		rockchip,vop-grf = <&vop_grf>;
- 		rockchip,vo1-grf = <&vo1_grf>;
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Detlev Casanova <detlev.casanova@collabora.com>
-Date: Mon, 6 May 2024 13:54:01 -0400
-Subject: dt-bindings: display: vop2: Add VP clock resets
-
-Add the documentation for VOP2 video ports reset clocks.
-One reset can be set per video port.
-
-Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
- Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 27 ++++++++++
- 1 file changed, 27 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
-index 111111111111..222222222222 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
-+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
-@@ -65,6 +65,22 @@ properties:
-       - const: dclk_vp3
-       - const: pclk_vop
- 
-+  resets:
-+    minItems: 3
-+    items:
-+      - description: Pixel clock reset for video port 0.
-+      - description: Pixel clock reset for video port 1.
-+      - description: Pixel clock reset for video port 2.
-+      - description: Pixel clock reset for video port 3.
-+
-+  reset-names:
-+    minItems: 3
-+    items:
-+      - const: dclk_vp0
-+      - const: dclk_vp1
-+      - const: dclk_vp2
-+      - const: dclk_vp3
-+
-   rockchip,grf:
-     $ref: /schemas/types.yaml#/definitions/phandle
-     description:
-@@ -128,6 +144,11 @@ allOf:
-         clock-names:
-           minItems: 7
- 
-+        resets:
-+          minItems: 4
-+        reset-names:
-+          minItems: 4
-+
-         ports:
-           required:
-             - port@0
-@@ -183,6 +204,12 @@ examples:
-                               "dclk_vp0",
-                               "dclk_vp1",
-                               "dclk_vp2";
-+                resets = <&cru SRST_VOP0>,
-+                         <&cru SRST_VOP1>,
-+                         <&cru SRST_VOP2>;
-+                reset-names = "dclk_vp0",
-+                              "dclk_vp1",
-+                              "dclk_vp2";
-                 power-domains = <&power RK3568_PD_VO>;
-                 iommus = <&vop_mmu>;
-                 vop_out: ports {
-- 
-Armbian
-
--- a/kernel.patches/0801-wireless-add-bcm43752.patch
+++ b/kernel.patches/0801-wireless-add-bcm43752.patch
@@ -1,74 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <unknown-email@domain.tld>
-Date: Wed, 28 Feb 2024 20:59:15 +0100
-Subject: net: wireless: brcmfmac: Add support for AP6275P
-
-This module features BCM43752A2 chipset. The firmware requires
-randomness seeding, so enabled it.
-
-Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
- drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c       | 5 ++++-
- drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 2 ++
- 2 files changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
-index 111111111111..222222222222 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
-+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
-@@ -70,6 +70,7 @@ BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie");
- BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie");
- BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie");
- BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie");
-+BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-pcie");
- 
- /* firmware config files */
- MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt");
-@@ -104,6 +105,7 @@ static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
- 	BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
- 	BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C),
- 	BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
-+	BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752),
- 	BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */
- 	BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */
- 	BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */
-@@ -1720,7 +1722,7 @@ static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
- 		memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
- 		brcmf_fw_nvram_free(nvram);
- 
-		if (devinfo->otp.valid) {
-+		if (devinfo->otp.valid || devinfo->ci->chip == BRCM_CC_43752_CHIP_ID) {
- 			size_t rand_len = BRCMF_RANDOM_SEED_LENGTH;
- 			struct brcmf_random_seed_footer footer = {
- 				.length = cpu_to_le32(rand_len),
-@@ -2700,6 +2702,7 @@ static const struct pci_device_id brcmf_pcie_devid_table[] = {
- 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA),
- 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC),
- 	BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW),
-+	BRCMF_PCIE_DEVICE(BRCM_PCIE_43752_DEVICE_ID, WCC),
- 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC),
- 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC),
- 	BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC),
-diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
-index 111111111111..222222222222 100644
--- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
-+++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
-@@ -52,6 +52,7 @@
- #define BRCM_CC_43664_CHIP_ID		43664
- #define BRCM_CC_43666_CHIP_ID		43666
- #define BRCM_CC_4371_CHIP_ID		0x4371
-+#define BRCM_CC_43752_CHIP_ID		43752
- #define BRCM_CC_4377_CHIP_ID		0x4377
- #define BRCM_CC_4378_CHIP_ID		0x4378
- #define BRCM_CC_4387_CHIP_ID		0x4387
-@@ -94,6 +95,7 @@
- #define BRCM_PCIE_4366_5G_DEVICE_ID	0x43c5
- #define BRCM_PCIE_4371_DEVICE_ID	0x440d
- #define BRCM_PCIE_43596_DEVICE_ID	0x4415
-+#define BRCM_PCIE_43752_DEVICE_ID	0x449d
- #define BRCM_PCIE_4377_DEVICE_ID	0x4488
- #define BRCM_PCIE_4378_DEVICE_ID	0x4425
- #define BRCM_PCIE_4387_DEVICE_ID	0x4433
-- 
-Armbian
-
--- a/kernel.patches/0802-wireless-add-clk-property.patch
+++ b/kernel.patches/0802-wireless-add-clk-property.patch
@@ -1,51 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <unknown-email@domain.tld>
-Date: Wed, 28 Feb 2024 21:09:51 +0100
-Subject: net: wireless: brcmfmac: Add optional 32k clock enable support
-
-WiFi modules often require 32kHz clock to function. Add support to
-enable the clock to pcie driver.
-
-Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
- drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
-index 111111111111..222222222222 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
-+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
-@@ -3,6 +3,7 @@
-  * Copyright (c) 2014 Broadcom Corporation
-  */
- 
-+#include <linux/clk.h>
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/firmware.h>
-@@ -2413,6 +2414,7 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
- 	struct brcmf_pciedev *pcie_bus_dev;
- 	struct brcmf_core *core;
- 	struct brcmf_bus *bus;
-+	struct clk *clk;
- 
- 	if (!id) {
- 		id = pci_match_id(brcmf_pcie_devid_table, pdev);
-@@ -2424,6 +2426,14 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
- 
- 	brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
- 
-+	clk = devm_clk_get_optional_enabled(&pdev->dev, "32k");
-+	if (IS_ERR(clk))
-+		return PTR_ERR(clk);
-+	if (clk) {
-+		dev_info(&pdev->dev, "enabling 32kHz clock\n");
-+		clk_set_rate(clk, 32768);
-+	}
-+
- 	ret = -ENOMEM;
- 	devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
- 	if (devinfo == NULL)
-- 
-Armbian
-
--- a/kernel.patches/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch
+++ b/kernel.patches/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch
@@ -1,37 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: amazingfate <liujianfeng1994@gmail.com>
-Date: Wed, 27 Dec 2023 15:03:57 +0800
-Subject: arm64: dts: rock-5b: Slow down emmc to hs200 and add tsadc node
-
---
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -371,8 +371,7 @@ &sdhci {
- 	no-sdio;
- 	no-sd;
- 	non-removable;
-	mmc-hs400-1_8v;
-	mmc-hs400-enhanced-strobe;
-+	mmc-hs200-1_8v;
- 	status = "okay";
- };
- 
-@@ -412,6 +411,10 @@ &sdio {
- 	status = "okay";
- };
- 
-+&tsadc {
-+	status = "okay";
-+};
-+
- &uart6 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
-- 
-Armbian
-
--- a/kernel.patches/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch
+++ b/kernel.patches/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch
@@ -1,52 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: lanefu <lane@lane-fu.com>
-Date: Sat, 20 Jan 2024 17:16:20 +0000
-Subject: rock-5b enable SPI flash in device tree
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-
-Signed-off-by: lanefu <lane@lane-fu.com>
---
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 27 ++++++++++
- 1 file changed, 27 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -421,6 +421,33 @@ &uart6 {
- 	status = "okay";
- };
- 
-+&sfc {
-+	status = "okay";
-+
-+		spi_flash: spi-flash@0 {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		compatible = "jedec,spi-nor";
-+		reg = <0x0>;
-+		spi-max-frequency = <50000000>;
-+		spi-tx-bus-width = <1>;
-+		spi-rx-bus-width = <4>;
-+		status = "okay";
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			loader@0 {
-+				label = "loader";
-+				reg = <0x0 0x1000000>;
-+			};
-+		};
-+	};
-+
-+};
-+
- &spi2 {
- 	status = "okay";
- 	assigned-clocks = <&cru CLK_SPI2>;
-- 
-Armbian
-
--- a/kernel.patches/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch
+++ b/kernel.patches/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch
@@ -1,67 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
-Date: Mon, 15 Jan 2024 22:51:17 +0200
-Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5b
-
-Add the necessary DT changes to enable HDMI0 on Rock 5B.
-
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 ++++++++++
- 1 file changed, 30 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -4,6 +4,7 @@
- 
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/leds/common.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
- #include "rk3588.dtsi"
- 
- / {
-@@ -185,6 +186,20 @@ &gpu {
- 	status = "okay";
- };
- 
-+&hdmi0 {
-+	status = "okay";
-+};
-+
-+&hdmi0_in {
-+	hdmi0_in_vp0: endpoint {
-+		remote-endpoint = <&vp0_out_hdmi0>;
-+	};
-+};
-+
-+&hdptxphy_hdmi0 {
-+	status = "okay";
-+};
-+
- &i2c0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&i2c0m2_xfer>;
-@@ -837,3 +852,18 @@ &usb_host1_xhci {
- &usb_host2_xhci {
- 	status = "okay";
- };
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&vop {
-+	status = "okay";
-+};
-+
-+&vp0 {
-+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+		remote-endpoint = <&hdmi0_in_vp0>;
-+	};
-+};
-- 
-Armbian
-
--- a/kernel.patches/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch
+++ b/kernel.patches/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch
@@ -1,41 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
-Date: Fri, 3 Nov 2023 20:05:05 +0200
-Subject: arm64: dts: rockchip: Make use of HDMI0 PHY PLL on rock-5b
-
-The initial vop2 support for rk3588 in mainline is not able to handle
-all display modes supported by connected displays, e.g.
-2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz.
-
-Additionally, it doesn't cope with non-integer refresh rates like 59.94,
-29.97, 23.98, etc.
-
-Make use of the HDMI0 PHY PLL to support the additional display modes.
-
-Note this requires commit "drm/rockchip: vop2: Improve display modes
-handling on rk3588", which needs a rework to be upstreamable.
-
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -186,6 +186,11 @@ &gpu {
- 	status = "okay";
- };
- 
-+&display_subsystem {
-+	clocks = <&hdptxphy_hdmi0>;
-+	clock-names = "hdmi0_phy_pll";
-+};
-+
- &hdmi0 {
- 	status = "okay";
- };
-- 
-Armbian
-
--- a/kernel.patches/1015-board-rock5b-automatic-fan-control.patch
+++ b/kernel.patches/1015-board-rock5b-automatic-fan-control.patch
@@ -1,68 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 6 May 2024 13:36:35 +0400
-Subject: arm64: dts: rockchip: enable automatic fan control on Rock 5B
-
-This links the PWM fan on Radxa Rock 5B as an active cooling device
-managed automatically by the thermal subsystem, with a target SoC
-temperature of 65C and a minimum-spin interval from 55C to 65C to
-ensure airflow when the system gets warm
-
-Helped-by: Dragan Simic <dsimic@manjaro.org>
-Reviewed-by: Dragan Simic <dsimic@manjaro.org>
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 +++++++++-
- 1 file changed, 29 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -53,7 +53,7 @@ led_rgb_b {
- 
- 	fan: pwm-fan {
- 		compatible = "pwm-fan";
-		cooling-levels = <0 95 145 195 255>;
-+		cooling-levels = <0 120 150 180 210 240 255>;
- 		fan-supply = <&vcc5v0_sys>;
- 		pwms = <&pwm1 0 50000 0>;
- 		#cooling-cells = <2>;
-@@ -299,6 +299,34 @@ i2s0_8ch_p0_0: endpoint {
- 	};
- };
- 
-+&package_thermal {
-+	polling-delay = <1000>;
-+
-+	trips {
-+		package_fan0: package-fan0 {
-+			temperature = <55000>;
-+			hysteresis = <2000>;
-+			type = "active";
-+		};
-+		package_fan1: package-fan1 {
-+			temperature = <65000>;
-+			hysteresis = <2000>;
-+			type = "active";
-+		};
-+	};
-+
-+	cooling-maps {
-+		map1 {
-+			trip = <&package_fan0>;
-+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
-+		};
-+		map2 {
-+			trip = <&package_fan1>;
-+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
-+		};
-+	};
-+};
-+
- &pcie2x1l0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&pcie2_0_rst>;
-- 
-Armbian
-
--- a/kernel.patches/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch
+++ b/kernel.patches/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch
@@ -1,57 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Tue, 27 Feb 2024 16:04:42 +0300
-Subject: Add HDMI and VOP2 to Rock 5A
-
---
- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 30 ++++++++++
- 1 file changed, 30 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -5,6 +5,7 @@
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/leds/common.h>
- #include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
- #include "rk3588s.dtsi"
- 
- / {
-@@ -765,3 +766,32 @@ &usb_host1_ohci {
- &usb_host2_xhci {
- 	status = "okay";
- };
-+
-+&hdmi0 {
-+	status = "okay";
-+};
-+
-+&hdptxphy_hdmi0 {
-+	status = "okay";
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&hdmi0_in {
-+	hdmi0_in_vp0: endpoint {
-+		remote-endpoint = <&vp0_out_hdmi0>;
-+	};
-+};
-+
-+&vop {
-+	status = "okay";
-+};
-+
-+&vp0 {
-+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+		remote-endpoint = <&hdmi0_in_vp0>;
-+	};
-+};
-- 
-Armbian
-
--- a/kernel.patches/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch
+++ b/kernel.patches/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch
@@ -1,36 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: amazingfate <liujianfeng1994@gmail.com>
-Date: Thu, 28 Mar 2024 00:41:34 +0800
-Subject: arch: arm64: dts: enable gpu node for rock-5a
-
---
- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -281,6 +281,11 @@ &gmac1_rgmii_clk
- 	status = "okay";
- };
- 
-+&gpu {
-+	mali-supply = <&vdd_gpu_s0>;
-+	status = "okay";
-+};
-+
- &mdio1 {
- 	rgmii_phy1: ethernet-phy@1 {
- 		/* RTL8211F */
-@@ -434,6 +439,7 @@ rk806_dvs3_null: dvs3-null-pins {
- 		regulators {
- 			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
- 				regulator-name = "vdd_gpu_s0";
-+				regulator-always-on;
- 				regulator-boot-on;
- 				regulator-min-microvolt = <550000>;
- 				regulator-max-microvolt = <950000>;
-- 
-Armbian
-
--- a/kernel.patches/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch
+++ b/kernel.patches/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch
@@ -1,265 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Thu, 16 Nov 2023 18:15:09 +0300
-Subject: arm64: dts: Add missing nodes to Orange Pi 5 Plus
-
---
- arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 182 +++++++++-
- 1 file changed, 181 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
-@@ -10,6 +10,7 @@
- #include <dt-bindings/input/input.h>
- #include <dt-bindings/pinctrl/rockchip.h>
- #include <dt-bindings/usb/pd.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
- #include "rk3588.dtsi"
- 
- / {
-@@ -158,6 +159,20 @@ daicodec: simple-audio-card,codec {
- 		};
- 	};
- 
-+	wlan-rfkill {
-+		compatible = "rfkill-gpio";
-+		label = "rfkill-wlan";
-+		radio-type = "wlan";
-+		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
-+	};
-+
-+	bluetooth-rfkill {
-+		compatible = "rfkill-gpio";
-+		label = "rfkill-bluetooth";
-+		radio-type = "bluetooth";
-+		shutdown-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
-+	};
-+
- 	vcc3v3_pcie30: vcc3v3-pcie30-regulator {
- 		compatible = "regulator-fixed";
- 		enable-active-high;
-@@ -199,6 +214,18 @@ vcc5v0_sys: vcc5v0-sys-regulator {
- 		regulator-max-microvolt = <5000000>;
- 	};
- 
-+	vbus5v0_typec: vbus5v0-typec-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
-+		regulator-name = "vbus5v0_typec";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&typec5v_pwren>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
- 	vcc5v0_usb20: vcc5v0-usb20-regulator {
- 		compatible = "regulator-fixed";
- 		enable-active-high;
-@@ -311,6 +338,53 @@ hym8563: rtc@51 {
- 		pinctrl-0 = <&hym8563_int>;
- 		wakeup-source;
- 	};
-+
-+	usbc0: usb-typec@22 {
-+		compatible = "fcs,fusb302";
-+		reg = <0x22>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&usbc0_int>;
-+		vbus-supply = <&vbus5v0_typec>;
-+
-+		usb_con: connector {
-+			compatible = "usb-c-connector";
-+			label = "USB-C";
-+			data-role = "dual";
-+			power-role = "dual";
-+			try-power-role = "source";
-+			op-sink-microwatt = <1000000>;
-+			sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
-+			source-pdos = <PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
-+
-+			ports {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				port@0 {
-+					reg = <0>;
-+					usbc0_hs: endpoint {
-+						remote-endpoint = <&usb_host0_xhci_drd_sw>;
-+					};
-+				};
-+
-+				port@1 {
-+					reg = <1>;
-+					usbc0_ss: endpoint {
-+						remote-endpoint = <&usbdp_phy0_typec_ss>;
-+					};
-+				};
-+
-+				port@2 {
-+					reg = <2>;
-+					usbc0_sbu: endpoint {
-+						remote-endpoint = <&usbdp_phy0_typec_sbu>;
-+					};
-+				};
-+			};
-+		};
-+	};
- };
- 
- &i2c7 {
-@@ -385,7 +459,7 @@ &pcie3x4 {
- &pinctrl {
- 	hym8563 {
- 		hym8563_int: hym8563-int {
-			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
- 		};
- 	};
- 
-@@ -408,6 +482,14 @@ hp_detect: hp-detect {
- 	};
- 
- 	usb {
-+		typec5v_pwren: typec5v-pwren {
-+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		usbc0_int: usbc0-int {
-+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+
- 		vcc5v0_usb20_en: vcc5v0-usb20-en {
- 			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- 		};
-@@ -803,6 +885,22 @@ &tsadc {
- 	status = "okay";
- };
- 
-+&u2phy0 {
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
-+&u2phy1 {
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	status = "okay";
-+};
-+
- &u2phy2 {
- 	status = "okay";
- };
-@@ -831,6 +929,35 @@ &uart9 {
- 	status = "okay";
- };
- 
-+&usbdp_phy0 {
-+	orientation-switch;
-+	mode-switch;
-+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
-+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
-+	status = "okay";
-+	svid = <0xff01>;
-+
-+	port {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		usbdp_phy0_typec_ss: endpoint@0 {
-+			reg = <0>;
-+			remote-endpoint = <&usbc0_ss>;
-+		};
-+
-+		usbdp_phy0_typec_sbu: endpoint@1 {
-+			reg = <1>;
-+			remote-endpoint = <&usbc0_sbu>;
-+		};
-+	};
-+};
-+
-+&usbdp_phy1 {
-+	rockchip,dp-lane-mux = <2 3>;
-+	status = "okay";
-+};
-+
- &usb_host0_ehci {
- 	status = "okay";
- };
-@@ -839,6 +966,20 @@ &usb_host0_ohci {
- 	status = "okay";
- };
- 
-+&usb_host0_xhci {
-+	dr_mode = "otg";
-+	usb-role-switch;
-+	status = "okay";
-+
-+	port {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		usb_host0_xhci_drd_sw: endpoint {
-+			remote-endpoint = <&usbc0_hs>;
-+		};
-+	};
-+};
-+
- &usb_host1_ehci {
- 	status = "okay";
- };
-@@ -846,3 +987,42 @@ &usb_host1_ehci {
- &usb_host1_ohci {
- 	status = "okay";
- };
-+
-+&usb_host1_xhci {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu_s0>;
-+	status = "okay";
-+};
-+
-+&hdmi0 {
-+	status = "okay";
-+};
-+
-+&hdptxphy_hdmi0 {
-+	status = "okay";
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&hdmi0_in {
-+	hdmi0_in_vp0: endpoint {
-+		remote-endpoint = <&vp0_out_hdmi0>;
-+	};
-+};
-+
-+&vop {
-+	status = "okay";
-+};
-+
-+&vp0 {
-+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+		remote-endpoint = <&hdmi0_in_vp0>;
-+	};
-+};
-- 
-Armbian
-
--- a/kernel.patches/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch
+++ b/kernel.patches/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch
@@ -1,39 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: amazingfate <liujianfeng1994@gmail.com>
-Date: Thu, 28 Mar 2024 16:07:18 +0800
-Subject: arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5a
-
---
- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -115,6 +115,10 @@ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
- 	};
- };
- 
-+&combphy0_ps {
-+	status = "okay";
-+};
-+
- &combphy2_psu {
- 	status = "okay";
- };
-@@ -299,6 +303,11 @@ rgmii_phy1: ethernet-phy@1 {
- 	};
- };
- 
-+&pcie2x1l2 {
-+	status = "okay";
-+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
-+};
-+
- &pinctrl {
- 	leds {
- 		io_led: io-led {
-- 
-Armbian
-
--- a/kernel.patches/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch
+++ b/kernel.patches/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch
@@ -1,64 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jianfeng Liu <liujianfeng1994@gmail.com>
-Date: Thu, 6 Jun 2024 23:28:01 +0800
-Subject: arm64: dts: rockchip: Add HDMI support to ArmSoM Sige7
-
---
- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 30 ++++++++++
- 1 file changed, 30 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-@@ -4,6 +4,7 @@
- 
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/leds/common.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
- #include "rk3588.dtsi"
- 
- / {
-@@ -164,6 +165,20 @@ &gpu {
- 	status = "okay";
- };
- 
-+&hdmi0 {
-+	status = "okay";
-+};
-+
-+&hdmi0_in {
-+	hdmi0_in_vp0: endpoint {
-+		remote-endpoint = <&vp0_out_hdmi0>;
-+	};
-+};
-+
-+&hdptxphy_hdmi0 {
-+	status = "okay";
-+};
-+
- &i2c0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&i2c0m2_xfer>;
-@@ -723,3 +738,18 @@ &usb_host1_xhci {
- 	dr_mode = "host";
- 	status = "okay";
- };
-+
-+&vop {
-+	status = "okay";
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&vp0 {
-+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+		remote-endpoint = <&hdmi0_in_vp0>;
-+	};
-+};
-- 
-Armbian
-
--- a/kernel.patches/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch
+++ b/kernel.patches/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch
@@ -1,39 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jianfeng Liu <liujianfeng1994@gmail.com>
-Date: Thu, 6 Jun 2024 23:29:39 +0800
-Subject: arm64: dts: rockchip: Add ap6275p wireless support to ArmSoM Sige7
-
---
- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 16 ++++++++++
- 1 file changed, 16 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-@@ -283,6 +283,22 @@ &pcie2x1l0 {
- &pcie2x1l1 {
- 	reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
- 	status = "okay";
-+
-+	pcie@0,0 {
-+		reg = <0x300000 0 0 0 0>;
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		ranges;
-+		device_type = "pci";
-+		bus-range = <0x30 0x3f>;
-+
-+		wifi: wifi@0,0 {
-+			compatible = "pci14e4,449d";
-+			reg = <0x310000 0 0 0 0>;
-+			clocks = <&hym8563>;
-+			clock-names = "32k";
-+		};
-+	};
- };
- 
- /* phy0 - left ethernet port */
-- 
-Armbian
-
--- a/kernel.patches/1040-board-khadas-edge2-add-nodes.patch
+++ b/kernel.patches/1040-board-khadas-edge2-add-nodes.patch
@@ -1,325 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Mon, 12 Feb 2024 17:35:13 +0300
-Subject: arm64: dts: rockchip: Add USB-C to Khadas Edge 2
-
-Khadas Edge 2 has 2x Type-C port. One just supports PD and
-controlled by MCU. The other one supports PD, DP Alt mode and DRD. This
-commit adds support for DRD.
-
-Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com>
---
- arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 120 ++++++++++
- 1 file changed, 120 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-@@ -6,6 +6,7 @@
- #include <dt-bindings/input/input.h>
- #include <dt-bindings/pinctrl/rockchip.h>
- #include <dt-bindings/leds/common.h>
-+#include <dt-bindings/usb/pd.h>
- #include "rk3588s.dtsi"
- 
- / {
-@@ -76,6 +77,18 @@ blue_led: led-2 {
- 		};
- 	};
- 
-+	vbus5v0_typec: vbus5v0-typec-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vbus5v0_typec";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		enable-active-high;
-+		gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
-+		vin-supply = <&vcc5v0_sys>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&typec5v_pwren>;
-+	};
-+
- 	vcc3v3_pcie_wl: vcc3v3-pcie-wl-regulator {
- 		compatible = "regulator-fixed";
- 		enable-active-high;
-@@ -224,6 +237,56 @@ regulator-state-mem {
- &i2c2 {
- 	status = "okay";
- 
-+	usbc0: usb-typec@22 {
-+		compatible = "fcs,fusb302";
-+		reg = <0x22>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&usbc0_int>;
-+		vbus-supply = <&vbus5v0_typec>;
-+		status = "okay";
-+
-+		usb_con: connector {
-+			compatible = "usb-c-connector";
-+			label = "USB-C";
-+			data-role = "dual";
-+			power-role = "dual";
-+			try-power-role = "source";
-+			op-sink-microwatt = <1000000>;
-+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
-+					PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
-+					PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
-+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-+
-+			ports {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				port@0 {
-+					reg = <0>;
-+					usbc0_orien_sw: endpoint {
-+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
-+					};
-+				};
-+
-+				port@1 {
-+					reg = <1>;
-+					usbc0_role_sw: endpoint {
-+						remote-endpoint = <&dwc3_0_role_switch>;
-+					};
-+				};
-+
-+				port@2 {
-+					reg = <2>;
-+					dp_altmode_mux: endpoint {
-+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
-+					};
-+				};
-+			};
-+		};
-+	};
-+
- 	hym8563: rtc@51 {
- 		compatible = "haoyu,hym8563";
- 		reg = <0x51>;
-@@ -256,6 +319,16 @@ vcc5v0_host_en: vcc5v0-host-en {
- 		};
- 	};
- 
-+	usb-typec {
-+		usbc0_int: usbc0-int {
-+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+
-+		typec5v_pwren: typec5v-pwren {
-+			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
- 	ir-receiver {
- 		ir_receiver_pin: ir-receiver-pin {
- 			rockchip,pins = <1  RK_PA7  RK_FUNC_GPIO  &pcfg_pull_none>;
-@@ -681,6 +754,15 @@ &uart9 {
- 	status = "okay";
- };
- 
-+&u2phy0 {
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
-+
- &u2phy2 {
- 	status = "okay";
- };
-@@ -707,6 +789,44 @@ &usb_host0_ohci {
- 	status = "okay";
- };
- 
-+&usbdp_phy0 {
-+	orientation-switch;
-+	mode-switch;
-+	svid = <0xff01>;
-+	sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
-+	sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
-+	status = "okay";
-+
-+	port {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		usbdp_phy0_orientation_switch: endpoint@0 {
-+			reg = <0>;
-+			remote-endpoint = <&usbc0_orien_sw>;
-+		};
-+
-+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
-+			reg = <1>;
-+			remote-endpoint = <&dp_altmode_mux>;
-+		};
-+	};
-+};
-+
-+&usb_host0_xhci {
-+	usb-role-switch;
-+	status = "okay";
-+
-+	port {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		dwc3_0_role_switch: endpoint@0 {
-+			reg = <0>;
-+			remote-endpoint = <&usbc0_role_sw>;
-+		};
-+	};
-+};
-+
- &usb_host1_ehci {
- 	status = "okay";
- };
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Mon, 12 Feb 2024 17:35:13 +0300
-Subject: arm64: dts: rockchip: Add bluetooth rfkill to Khadas Edge 2
-
---
- arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-@@ -116,6 +116,15 @@ vcc5v0_host: vcc5v0-host-regulator {
- 		vin-supply = <&vcc5v0_sys>;
- 	};
- 
-+	bluetooth-rfkill {
-+		compatible = "rfkill-gpio";
-+		label = "rfkill-bluetooth";
-+		radio-type = "bluetooth";
-+		shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&bt_reset_pin>;
-+	};
-+
- 	vcc5v0_sys: vcc5v0-sys-regulator {
- 		compatible = "regulator-fixed";
- 		regulator-name = "vcc5v0_sys";
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Mon, 19 Feb 2024 23:32:11 +0300
-Subject: arm64: dts: rockchip: Add HDMI & VOP2 to Khadas Edge 2
-
---
- arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 36 ++++++++++
- 1 file changed, 36 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-@@ -7,6 +7,7 @@
- #include <dt-bindings/pinctrl/rockchip.h>
- #include <dt-bindings/leds/common.h>
- #include <dt-bindings/usb/pd.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
- #include "rk3588s.dtsi"
- 
- / {
-@@ -823,6 +824,7 @@ usbdp_phy0_dp_altmode_mux: endpoint@1 {
- };
- 
- &usb_host0_xhci {
-+	dr-mode = "otg";
- 	usb-role-switch;
- 	status = "okay";
- 
-@@ -847,3 +849,37 @@ &usb_host1_ohci {
- &usb_host2_xhci {
- 	status = "okay";
- };
-+
-+&hdmi0 {
-+	status = "okay";
-+};
-+
-+&hdptxphy_hdmi0 {
-+	status = "okay";
-+};
-+
-+&display_subsystem {
-+	clocks = <&hdptxphy_hdmi0>;
-+	clock-names = "hdmi0_phy_pll";
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&hdmi0_in {
-+	hdmi0_in_vp0: endpoint {
-+		remote-endpoint = <&vp0_out_hdmi0>;
-+	};
-+};
-+
-+&vop {
-+	status = "okay";
-+};
-+
-+&vp0 {
-+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+		remote-endpoint = <&hdmi0_in_vp0>;
-+	};
-+};
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Sat, 2 Mar 2024 19:13:59 +0300
-Subject: arm64: dts: rockchip: Add AP6275P wireless support to Khadas Edge 2
-
---
- arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 17 ++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-@@ -366,6 +366,23 @@ &pcie2x1l2 {
- 	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
- 	vpcie3v3-supply = <&vcc3v3_pcie_wl>;
- 	status = "okay";
-+
-+	pcie@0,0 {
-+		reg = <0x400000 0 0 0 0>;
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		ranges;
-+		device_type = "pci";
-+		bus-range = <0x40 0x4f>;
-+
-+		wifi: wifi@0,0 {
-+			compatible = "pci14e4,449d";
-+			reg = <0x410000 0 0 0 0>;
-+			clocks = <&hym8563>;
-+			clock-names = "32k";
-+		};
-+	};
-+
- };
- 
- &pwm11 {
-- 
-Armbian
-
--- a/kernel.patches/1041-board-khadas-edge2-mcu.patch
+++ b/kernel.patches/1041-board-khadas-edge2-mcu.patch
@@ -1,441 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Wed, 6 Mar 2024 00:09:25 +0300
-Subject: mfd: khadas-mcu: add Edge2 registers
-
---
- drivers/mfd/khadas-mcu.c       |  8 +++-
- include/linux/mfd/khadas-mcu.h | 24 ++++++++++
- 2 files changed, 30 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c
-index 111111111111..222222222222 100644
--- a/drivers/mfd/khadas-mcu.c
-+++ b/drivers/mfd/khadas-mcu.c
-@@ -26,6 +26,10 @@ static bool khadas_mcu_reg_volatile(struct device *dev, unsigned int reg)
- 	case KHADAS_MCU_CHECK_USER_PASSWD_REG:
- 	case KHADAS_MCU_WOL_INIT_START_REG:
- 	case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG:
-+	case KHADAS_MCU_LED_ON_RAM_REG:
-+	case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2:
-+	case KHADAS_MCU_WDT_EN_REG:
-+	case KHADAS_MCU_SYS_RST_REG:
- 		return true;
- 	default:
- 		return false;
-@@ -69,14 +73,14 @@ static const struct regmap_config khadas_mcu_regmap_config = {
- 	.reg_bits	= 8,
- 	.reg_stride	= 1,
- 	.val_bits	= 8,
-	.max_register	= KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG,
-+	.max_register	= KHADAS_MCU_SYS_RST_REG,
- 	.volatile_reg	= khadas_mcu_reg_volatile,
- 	.writeable_reg	= khadas_mcu_reg_writeable,
- 	.cache_type	= REGCACHE_MAPLE,
- };
- 
- static struct mfd_cell khadas_mcu_fan_cells[] = {
-	/* VIM1/2 Rev13+ and VIM3 only */
-+	/* VIM1/2 Rev13+, VIM3 and Edge2 only */
- 	{ .name = "khadas-mcu-fan-ctrl", },
- };
- 
-diff --git a/include/linux/mfd/khadas-mcu.h b/include/linux/mfd/khadas-mcu.h
-index 111111111111..222222222222 100644
--- a/include/linux/mfd/khadas-mcu.h
-+++ b/include/linux/mfd/khadas-mcu.h
-@@ -35,26 +35,45 @@
- #define KHADAS_MCU_FACTORY_TEST_REG		0x16 /* R */
- #define KHADAS_MCU_BOOT_MODE_REG		0x20 /* RW */
- #define KHADAS_MCU_BOOT_EN_WOL_REG		0x21 /* RW */
-+#define KHADAS_MCU_BOOT_EN_DCIN_REG_V2		0x21 /* RW */
- #define KHADAS_MCU_BOOT_EN_RTC_REG		0x22 /* RW */
- #define KHADAS_MCU_BOOT_EN_EXP_REG		0x23 /* RW */
-+#define KHADAS_MCU_LED_MODE_ON_REG_V2		0x23 /* RW */
-+#define KHADAS_MCU_LED_MODE_OFF_REG_V2		0x24 /* RW */
- #define KHADAS_MCU_BOOT_EN_IR_REG		0x24 /* RW */
- #define KHADAS_MCU_BOOT_EN_DCIN_REG		0x25 /* RW */
-+#define KHADAS_MCU_RGB_ON_R_REG			0x25 /* RW */
-+#define KHADAS_MCU_RGB_ON_G_REG			0x26 /* RW */
- #define KHADAS_MCU_BOOT_EN_KEY_REG		0x26 /* RW */
-+#define KHADAS_MCU_RGB_ON_B_REG			0x27 /* RW */
- #define KHADAS_MCU_KEY_MODE_REG			0x27 /* RW */
-+#define KHADAS_MCU_RGB_OFF_R_REG		0x28 /* RW */
- #define KHADAS_MCU_LED_MODE_ON_REG		0x28 /* RW */
-+#define KHADAS_MCU_RGB_OFF_G_REG		0x29 /* RW */
- #define KHADAS_MCU_LED_MODE_OFF_REG		0x29 /* RW */
-+#define KHADAS_MCU_RGB_OFF_B_REG		0x2a /* RW */
- #define KHADAS_MCU_SHUTDOWN_NORMAL_REG		0x2c /* RW */
- #define KHADAS_MCU_MAC_SWITCH_REG		0x2d /* RW */
-+#define KHADAS_MCU_REST_CONF_REG		0x2e /* RW */
- #define KHADAS_MCU_MCU_SLEEP_MODE_REG		0x2e /* RW */
-+#define KHADAS_MCU_BOOT_EN_IR_REG_V2		0x2f /* RW */
- #define KHADAS_MCU_IR_CODE1_0_REG		0x2f /* RW */
- #define KHADAS_MCU_IR_CODE1_1_REG		0x30 /* RW */
-+#define KHADAS_MCU_IR1_CUST1_REG		0x30 /* RW */
- #define KHADAS_MCU_IR_CODE1_2_REG		0x31 /* RW */
-+#define KHADAS_MCU_IR1_CUST2_REG		0x31 /* RW */
- #define KHADAS_MCU_IR_CODE1_3_REG		0x32 /* RW */
-+#define KHADAS_MCU_IR1_ORDER1_REG		0x32 /* RW */
- #define KHADAS_MCU_USB_PCIE_SWITCH_REG		0x33 /* RW */
-+#define KHADAS_MCU_IR1_ORDER2_REG		0x33 /* RW */
-+#define KHADAS_MCU_IR2_CUST1_REG		0x34 /* RW */
- #define KHADAS_MCU_IR_CODE2_0_REG		0x34 /* RW */
- #define KHADAS_MCU_IR_CODE2_1_REG		0x35 /* RW */
-+#define KHADAS_MCU_IR2_CUST2_REG		0x35 /* RW */
- #define KHADAS_MCU_IR_CODE2_2_REG		0x36 /* RW */
-+#define KHADAS_MCU_IR2_ORDER1_REG		0x36 /* RW */
- #define KHADAS_MCU_IR_CODE2_3_REG		0x37 /* RW */
-+#define KHADAS_MCU_IR2_ORDER2_REG		0x36 /* RW */
- #define KHADAS_MCU_PASSWD_USER_0_REG		0x40 /* RW */
- #define KHADAS_MCU_PASSWD_USER_1_REG		0x41 /* RW */
- #define KHADAS_MCU_PASSWD_USER_2_REG		0x42 /* RW */
-@@ -69,6 +88,10 @@
- #define KHADAS_MCU_SHUTDOWN_NORMAL_STATUS_REG	0x86 /* RO */
- #define KHADAS_MCU_WOL_INIT_START_REG		0x87 /* WO */
- #define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG	0x88 /* WO */
-+#define KHADAS_MCU_LED_ON_RAM_REG		0x89 /* WO */
-+#define KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2	0x8A /* WO */
-+#define KHADAS_MCU_WDT_EN_REG			0x8B /* WO */
-+#define KHADAS_MCU_SYS_RST_REG			0x91 /* WO */
- 
- enum {
- 	KHADAS_BOARD_VIM1 = 0x1,
-@@ -76,6 +99,7 @@ enum {
- 	KHADAS_BOARD_VIM3,
- 	KHADAS_BOARD_EDGE = 0x11,
- 	KHADAS_BOARD_EDGE_V,
-+	KHADAS_BOARD_EDGE2,
- };
- 
- /**
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Wed, 6 Mar 2024 00:09:58 +0300
-Subject: mfd: khadas-mcu: drop unused code
-
---
- drivers/mfd/khadas-mcu.c | 11 ----------
- 1 file changed, 11 deletions(-)
-
-diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c
-index 111111111111..222222222222 100644
--- a/drivers/mfd/khadas-mcu.c
-+++ b/drivers/mfd/khadas-mcu.c
-@@ -84,10 +84,6 @@ static struct mfd_cell khadas_mcu_fan_cells[] = {
- 	{ .name = "khadas-mcu-fan-ctrl", },
- };
- 
-static struct mfd_cell khadas_mcu_cells[] = {
-	{ .name = "khadas-mcu-user-mem", },
-};
-
- static int khadas_mcu_probe(struct i2c_client *client)
- {
- 	struct device *dev = &client->dev;
-@@ -109,13 +105,6 @@ static int khadas_mcu_probe(struct i2c_client *client)
- 		return ret;
- 	}
- 
-	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
-				   khadas_mcu_cells,
-				   ARRAY_SIZE(khadas_mcu_cells),
-				   NULL, 0, NULL);
-	if (ret)
-		return ret;
-
- 	if (of_property_present(dev->of_node, "#cooling-cells"))
- 		return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
- 					    khadas_mcu_fan_cells,
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Wed, 6 Mar 2024 00:13:10 +0300
-Subject: thermal: khadas_mcu_fan: add support for Khadas Edge 2
-
---
- drivers/thermal/khadas_mcu_fan.c | 77 +++++++++-
- 1 file changed, 73 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/thermal/khadas_mcu_fan.c b/drivers/thermal/khadas_mcu_fan.c
-index 111111111111..222222222222 100644
--- a/drivers/thermal/khadas_mcu_fan.c
-+++ b/drivers/thermal/khadas_mcu_fan.c
-@@ -15,10 +15,16 @@
- #include <linux/thermal.h>
- 
- #define MAX_LEVEL 3
-+#define MAX_SPEED 0x64
- 
- struct khadas_mcu_fan_ctx {
- 	struct khadas_mcu *mcu;
- 	unsigned int level;
-+
-+	unsigned int fan_max_level;
-+	unsigned int fan_register;
-+	unsigned int *fan_cooling_levels;
-+
- 	struct thermal_cooling_device *cdev;
- };
- 
-@@ -26,9 +32,21 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx,
- 				    unsigned int level)
- {
- 	int ret;
-+	unsigned int write_level = level;
-+
-+	if (level > ctx->fan_max_level)
-+		return -EINVAL;
-+
-+	if (ctx->fan_cooling_levels != NULL) {
-+		write_level = ctx->fan_cooling_levels[level];
-+
-+		if (write_level > MAX_SPEED)
-+			return -EINVAL;
-+	}
-+
-+	ret = regmap_write(ctx->mcu->regmap, ctx->fan_register,
-+			   write_level);
- 
-	ret = regmap_write(ctx->mcu->regmap, KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG,
-			   level);
- 	if (ret)
- 		return ret;
- 
-@@ -40,7 +58,9 @@ static int khadas_mcu_fan_set_level(struct khadas_mcu_fan_ctx *ctx,
- static int khadas_mcu_fan_get_max_state(struct thermal_cooling_device *cdev,
- 					unsigned long *state)
- {
-	*state = MAX_LEVEL;
-+	struct khadas_mcu_fan_ctx *ctx = cdev->devdata;
-+
-+	*state = ctx->fan_max_level;
- 
- 	return 0;
- }
-@@ -61,7 +81,7 @@ khadas_mcu_fan_set_cur_state(struct thermal_cooling_device *cdev,
- {
- 	struct khadas_mcu_fan_ctx *ctx = cdev->devdata;
- 
-	if (state > MAX_LEVEL)
-+	if (state > ctx->fan_max_level)
- 		return -EINVAL;
- 
- 	if (state == ctx->level)
-@@ -76,6 +96,48 @@ static const struct thermal_cooling_device_ops khadas_mcu_fan_cooling_ops = {
- 	.set_cur_state = khadas_mcu_fan_set_cur_state,
- };
- 
-+// Khadas Edge 2 sets fan level by passing fan speed(0-100). So we need different logic here like pwm-fan cooling-levels.
-+// This is optional and just necessary for Edge 2.
-+static int khadas_mcu_fan_get_cooling_data_edge2(struct khadas_mcu_fan_ctx *ctx, struct device *dev) {
-+	struct device_node *np = ctx->mcu->dev->of_node;
-+	int num, i, ret;
-+
-+	if (!of_property_present(np, "cooling-levels"))
-+		return 0;
-+
-+	ret = of_property_count_u32_elems(np, "cooling-levels");
-+	if (ret <= 0) {
-+		dev_err(dev, "Wrong data!\n");
-+		return ret ? : -EINVAL;
-+	}
-+
-+	num = ret;
-+	ctx->fan_cooling_levels = devm_kcalloc(dev, num, sizeof(u32),
-+						   GFP_KERNEL);
-+	if (!ctx->fan_cooling_levels)
-+		return -ENOMEM;
-+
-+	ret = of_property_read_u32_array(np, "cooling-levels",
-+					 ctx->fan_cooling_levels, num);
-+	if (ret) {
-+		dev_err(dev, "Property 'cooling-levels' cannot be read!\n");
-+		return ret;
-+	}
-+
-+	for (i = 0; i < num; i++) {
-+		if (ctx->fan_cooling_levels[i] > MAX_SPEED) {
-+			dev_err(dev, "PWM fan state[%d]:%d > %d\n", i,
-+				ctx->fan_cooling_levels[i], MAX_SPEED);
-+			return -EINVAL;
-+		}
-+	}
-+
-+	ctx->fan_max_level = num - 1;
-+	ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG_V2;
-+
-+	return 0;
-+}
-+
- static int khadas_mcu_fan_probe(struct platform_device *pdev)
- {
- 	struct khadas_mcu *mcu = dev_get_drvdata(pdev->dev.parent);
-@@ -90,6 +152,13 @@ static int khadas_mcu_fan_probe(struct platform_device *pdev)
- 	ctx->mcu = mcu;
- 	platform_set_drvdata(pdev, ctx);
- 
-+	ctx->fan_max_level = MAX_LEVEL;
-+	ctx->fan_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG;
-+
-+	ret = khadas_mcu_fan_get_cooling_data_edge2(ctx, dev);
-+	if (ret)
-+		return ret;
-+
- 	cdev = devm_thermal_of_cooling_device_register(dev->parent,
- 			dev->parent->of_node, "khadas-mcu-fan", ctx,
- 			&khadas_mcu_fan_cooling_ops);
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Wed, 6 Mar 2024 00:14:58 +0300
-Subject: dt-bindings: mfd: khadas-mcu: add cooling-levels property
-
---
- Documentation/devicetree/bindings/mfd/khadas,mcu.yaml | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
-index 111111111111..222222222222 100644
--- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
-+++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
-@@ -11,7 +11,7 @@ maintainers:
- 
- description: |
-   Khadas embeds a microcontroller on their VIM and Edge boards adding some
-  system feature as PWM Fan control (for VIM2 rev14 or VIM3), User memory
-+  system feature as PWM Fan control (for VIM2 rev14, VIM3, Edge2), User memory
-   storage, IR/Key resume control, system power LED control and more.
- 
- properties:
-@@ -22,6 +22,11 @@ properties:
-   "#cooling-cells": # Only needed for boards having FAN control feature
-     const: 2
- 
-+  cooling-levels:
-+    description: Max speed of PWM fan. This property is necessary for Khadas Edge 2.
-+    items:
-+      maximum: 100
-+
-   reg:
-     maxItems: 1
- 
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Wed, 6 Mar 2024 00:17:58 +0300
-Subject: arm64: dts: rockchip: Add MCU to Khadas Edge 2
-
---
- arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-@@ -304,6 +304,13 @@ hym8563: rtc@51 {
- 		clock-output-names = "hym8563";
- 		wakeup-source;
- 	};
-+
-+	khadas_mcu: system-controller@18 {
-+		compatible = "khadas,mcu";
-+		reg = <0x18>;
-+		cooling-levels = <0 50 72 100>;
-+		#cooling-cells = <2>;
-+	};
- };
- 
- &pinctrl {
-- 
-Armbian
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Mon, 25 Mar 2024 22:41:26 +0300
-Subject: arm64: dts: rockchip: Add automatic fan control to Khadas Edge 2
-
---
- arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 56 ++++++++++
- 1 file changed, 56 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-@@ -313,6 +313,62 @@ khadas_mcu: system-controller@18 {
- 	};
- };
- 
-+&package_thermal {
-+	polling-delay = <1000>;
-+
-+	trips {
-+		package_fan0: package-fan0 {
-+			temperature = <45000>;
-+			hysteresis = <5000>;
-+			type = "active";
-+		};
-+
-+		package_fan1: package-fan1 {
-+			temperature = <55000>;
-+			hysteresis = <5000>;
-+			type = "active";
-+		};
-+
-+		package_fan2: package-fan2 {
-+			temperature = <60000>;
-+			hysteresis = <5000>;
-+			type = "active";
-+		};
-+
-+		package_fan3: package-fan3 {
-+			temperature = <70000>;
-+			hysteresis = <5000>;
-+			type = "active";
-+		};
-+	};
-+
-+	cooling-maps {
-+		map0 {
-+			trip = <&package_fan0>;
-+			cooling-device = <&khadas_mcu 0 1>;
-+			contribution = <1024>;
-+		};
-+
-+		map1 {
-+			trip = <&package_fan1>;
-+			cooling-device = <&khadas_mcu 1 2>;
-+			contribution = <1024>;
-+		};
-+
-+		map2 {
-+			trip = <&package_fan2>;
-+			cooling-device = <&khadas_mcu 2 3>;
-+			contribution = <1024>;
-+		};
-+
-+		map3 {
-+			trip = <&package_fan3>;
-+			cooling-device = <&khadas_mcu 3 THERMAL_NO_LIMIT>;
-+			contribution = <1024>;
-+		};
-+	};
-+};
-+
- &pinctrl {
- 	vdd_sd {
- 		vdd_sd_en: vdd-sd-en {
-- 
-Armbian
-
--- a/kernel.patches/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch
+++ b/kernel.patches/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch
@@ -1,38 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ricardo Pardini <ricardo@pardini.net>
-Date: Thu, 6 Jun 2024 23:00:05 +0200
-Subject: arm64: dts: rockchip: Add NanoPC T6 SPI Flash
-
-Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 14 ++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -576,6 +576,20 @@ &sdmmc {
- 	status = "okay";
- };
- 
-+&sfc {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&fspim1_pins>;
-+	status = "okay";
-+
-+	flash@0 {
-+		compatible = "jedec,spi-nor";
-+		reg = <0x0>;
-+		spi-max-frequency = <50000000>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <1>;
-+	};
-+};
-+
- &spi2 {
- 	status = "okay";
- 	assigned-clocks = <&cru CLK_SPI2>;
-- 
-Armbian
-
--- a/lib/modules/6.18.6/kernel/drivers/dma/bcm-sba-raid.ko
+++ b/lib/modules/6.18.6/kernel/drivers/dma/bcm-sba-raid.ko
--- a/lib/modules/6.18.6/kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.ko
+++ b/lib/modules/6.18.6/kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.ko
--- a/lib/modules/6.18.6/modules.alias
+++ b/lib/modules/6.18.6/modules.alias
@@ -0,0 +1,9 @@
+# Aliases extracted from modules themselves.
+alias of:N*T*Cbrcm,iproc-sba-v2C* bcm_sba_raid
+alias of:N*T*Cbrcm,iproc-sba-v2 bcm_sba_raid
+alias of:N*T*Cbrcm,iproc-sbaC* bcm_sba_raid
+alias of:N*T*Cbrcm,iproc-sba bcm_sba_raid
+alias of:N*T*Csophgo,sg2044-dwmacC* dwmac_sophgo
+alias of:N*T*Csophgo,sg2044-dwmac dwmac_sophgo
+alias of:N*T*Csophgo,sg2042-dwmacC* dwmac_sophgo
+alias of:N*T*Csophgo,sg2042-dwmac dwmac_sophgo
--- a/lib/modules/6.18.6/modules.alias.bin
+++ b/lib/modules/6.18.6/modules.alias.bin
--- a/lib/modules/6.18.6/modules.builtin
+++ b/lib/modules/6.18.6/modules.builtin
--- a/lib/modules/6.18.6/modules.builtin.alias.bin
+++ b/lib/modules/6.18.6/modules.builtin.alias.bin
--- a/lib/modules/6.18.6/modules.builtin.bin
+++ b/lib/modules/6.18.6/modules.builtin.bin
--- a/lib/modules/6.18.6/modules.builtin.modinfo
+++ b/lib/modules/6.18.6/modules.builtin.modinfo
--- a/lib/modules/6.18.6/modules.dep
+++ b/lib/modules/6.18.6/modules.dep
@@ -0,0 +1,2 @@
+kernel/drivers/dma/bcm-sba-raid.ko:
+kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.ko:
--- a/lib/modules/6.18.6/modules.dep.bin
+++ b/lib/modules/6.18.6/modules.dep.bin
--- a/lib/modules/6.18.6/modules.devname
+++ b/lib/modules/6.18.6/modules.devname
--- a/lib/modules/6.18.6/modules.order
+++ b/lib/modules/6.18.6/modules.order
@@ -0,0 +1,2 @@
+kernel/drivers/dma/bcm-sba-raid.ko
+kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.ko
--- a/lib/modules/6.18.6/modules.softdep
+++ b/lib/modules/6.18.6/modules.softdep
@@ -0,0 +1 @@
+# Soft dependencies extracted from modules themselves.
--- a/lib/modules/6.18.6/modules.symbols
+++ b/lib/modules/6.18.6/modules.symbols
@@ -0,0 +1 @@
+# Aliases for symbols, used by symbol_request().
--- a/lib/modules/6.18.6/modules.symbols.bin
+++ b/lib/modules/6.18.6/modules.symbols.bin
--- a/lib/modules/6.18.6/modules.weakdep
+++ b/lib/modules/6.18.6/modules.weakdep
@@ -0,0 +1 @@
+# Weak dependencies extracted from modules themselves.
--- a/rk3588-friendlyelec-cm3588-nas.dtb
+++ b/rk3588-friendlyelec-cm3588-nas.dtb
--- a/u-boot-rockchip.bin
+++ b/u-boot-rockchip.bin
--- a/BIN
+++ b/BIN
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Timmy Welch	119674f0ac	Update uboot Fix final uboot location Remove unnecessary dtb copies	2026-01-19 23:11:27 -08:00
Timmy Welch	51ac993792	Undo quirks	2026-01-19 23:09:50 -08:00
Timmy Welch	d9f241f304	Update to 6.18.5	2026-01-19 19:38:31 -08:00
Timmy Welch	e0aea21341	Merge gokr-build-uboot into gokr-rebuild-uboot	2026-01-19 19:31:46 -08:00
Timmy Welch	0e1b7b2846	Add quirks for adata sd card	2026-01-19 18:45:47 -08:00
Timmy Welch	5c5b71cda4	Make build commands more robust	2026-01-19 18:41:18 -08:00
Timmy Welch	3f9569c706	Fix bootscript	2026-01-19 18:41:18 -08:00
Timmy Welch	ef7d105368	Update to 6.18.5	2026-01-19 18:41:18 -08:00
Timmy Welch	7aa87ab30f	Updates	2026-01-19 18:40:17 -08:00
Timmy Welch	7e9d9749de	Install dtbs	2025-04-05 16:53:56 -07:00
Timmy Welch	85ba69a109	Pull gokr-build-kernel from https://github.com/gokrazy/autoupdate	2025-04-05 16:39:04 -07:00
Timmy Welch	dc7eed91d7	Merge branch 'old-main'	2025-04-05 14:08:20 -07:00
Timmy Welch	002960a834	update config Some checks failed Update u-boot revision / CI (push) Has been cancelled Details Update kernel ref / CI (push) Has been cancelled Details	2024-07-22 20:02:05 -07:00
Timmy Welch	ab5cf8a34e	Update kernel and firmware	2024-07-22 19:58:35 -07:00
Timmy Welch	2e5cddd245	update go.mod	2024-07-18 00:13:19 -07:00
				`@@ -0,0 +1 @@`
				`https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-6.18.6.tar.xz`
				`@@ -0,0 +1 @@`
				`# Soft dependencies extracted from modules themselves.`
				`@@ -0,0 +1 @@`
				`# Aliases for symbols, used by symbol_request().`
				`@@ -0,0 +1 @@`
				`# Weak dependencies extracted from modules themselves.`