From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 3 Nov 2023 20:05:05 +0200 Subject: arm64: dts: rockchip: Make use of HDMI0 PHY PLL on rock-5b The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of the HDMI0 PHY PLL to support the additional display modes. Note this requires commit "drm/rockchip: vop2: Improve display modes handling on rk3588", which needs a rework to be upstreamable. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -186,6 +186,11 @@ &gpu { status = "okay"; }; +&display_subsystem { + clocks = <&hdptxphy_hdmi0>; + clock-names = "hdmi0_phy_pll"; +}; + &hdmi0 { status = "okay"; }; -- Armbian